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[/] [m32632/] [trunk/] [rtl/] [DCACHE.v] - Blame information for rev 47

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Line No. Rev Author Line
1 29 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 9 ns32kum
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6 23 ns32kum
//      Filename:       DCACHE.v
7 29 ns32kum
//  Version:    3.0 Cache Interface reworked
8
//      History:        2.1 bug fix of November 2016
9
//                              2.0 50 MHz release of 14 August 2016
10
//                              1.1 bug fix of 7 October 2015
11 23 ns32kum
//                              1.0 first release of 30 Mai 2015
12 29 ns32kum
//      Date:           2 December 2018
13 9 ns32kum
//
14 29 ns32kum
// Copyright (C) 2018 Udo Moeller
15 9 ns32kum
// 
16
// This source file may be used and distributed without 
17
// restriction provided that this copyright statement is not 
18
// removed from the file and that any derivative work contains 
19
// the original copyright notice and the associated disclaimer.
20
// 
21
// This source file is free software; you can redistribute it 
22
// and/or modify it under the terms of the GNU Lesser General 
23
// Public License as published by the Free Software Foundation;
24
// either version 2.1 of the License, or (at your option) any 
25
// later version. 
26
// 
27
// This source is distributed in the hope that it will be 
28
// useful, but WITHOUT ANY WARRANTY; without even the implied 
29
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
30
// PURPOSE. See the GNU Lesser General Public License for more 
31
// details. 
32
// 
33
// You should have received a copy of the GNU Lesser General 
34
// Public License along with this source; if not, download it 
35
// from http://www.opencores.org/lgpl.shtml 
36
// 
37 29 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
38 9 ns32kum
//
39
//      Modules contained in this file:
40
//      DCACHE          the data cache of M32632
41
//
42 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
43 9 ns32kum
 
44 29 ns32kum
module DCACHE(  BCLK, DRAMSZ, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, CTRL_QW, PSR_USER, WRITE, READ, RMW,
45
                                QWATWO, ENWR, IC_PREQ, DMA_CHK, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR,
46
                                MCR_FLAGS, PACKET, SIZE, VADR, INHIBIT, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET,
47 23 ns32kum
                                HLDA, ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
48 9 ns32kum
                                RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
49
 
50
input                   BCLK;
51 23 ns32kum
input    [2:0]   DRAMSZ;
52 9 ns32kum
input                   MDONE;
53
input                   BRESET;
54
input                   PTB_WR;
55
input                   PTB_SEL;
56
input                   IO_READY;
57 29 ns32kum
input    [1:0]   CTRL_QW;
58 9 ns32kum
input                   PSR_USER;
59
input                   WRITE;
60
input                   READ;
61
input                   ZTEST;
62
input                   RMW;
63 12 ns32kum
input                   QWATWO;
64 9 ns32kum
input                   ENWR;
65
input                   IC_PREQ;
66 23 ns32kum
input                   DMA_CHK;
67 9 ns32kum
input    [1:0]   CFG;
68
input    [1:0]   CINVAL;
69 29 ns32kum
input   [28:4]  DMA_AA;
70 9 ns32kum
input   [63:0]   DP_Q;
71 29 ns32kum
input  [127:0]   DRAM_Q;
72 9 ns32kum
input  [31:12]  IC_VA;
73
input    [3:0]   ICTODC;
74
input   [31:0]   IO_Q;
75
input    [1:0]   IVAR;
76
input    [3:0]   MCR_FLAGS;
77
input    [3:0]   PACKET;
78
input    [1:0]   SIZE;
79
input   [31:0]   VADR;
80 29 ns32kum
input                   INHIBIT;
81 9 ns32kum
input    [2:0]   RWVAL;
82
input   [40:2]  DBG_IN;
83
input                   ENDRAM;
84
 
85
output                  IO_RD;
86
output                  IO_WR;
87
output                  DRAM_ACC;
88
output                  DRAM_WR;
89
output                  INIT_RUN;
90
output   [1:0]   PTE_STAT;
91
output                  KDET;
92
output                  HLDA;
93
output                  RWVFLAG;
94
output   [5:0]   ACC_STAT;
95
output  [31:0]   DP_DI;
96
output   [3:1]  IACC_STAT;
97
output   [1:0]   IC_SIGS;
98 29 ns32kum
output  [28:4]  KOLLI_A;
99 9 ns32kum
output  [23:0]   MMU_DIN;
100 29 ns32kum
output reg      [28:0]   DRAM_A;
101 9 ns32kum
output reg      [35:0]   DRAM_DI;
102
output reg      [31:0]   IO_A;
103
output reg       [3:0]   IO_BE;
104
output reg      [31:0]   IO_DI;
105
output                  DBG_HIT;
106
 
107
reg             [31:0]   DFFE_IOR;
108
reg             [31:0]   CAPDAT;
109
reg             [31:0]   VADR_R;
110
reg                             AUX_ALT;
111
reg                             DFF_QWEXT;
112 29 ns32kum
reg             [11:4]  KOLLI_AR;
113 9 ns32kum
 
114 29 ns32kum
wire    [28:4]  ADDR;
115 9 ns32kum
wire                    ADR_EQU;
116
wire                    AUX_DAT;
117
wire                    CA_HIT;
118
wire                    CA_SET;
119
wire                    CUPDATE;
120
wire                    DMA_MUX;
121
wire     [3:0]   ENBYTE;
122
wire                    HIT_ALL;
123
wire                    INIT_CA_RUN;
124
wire                    IO_ACC;
125
wire                    IO_SPACE;
126
wire                    KOMUX;
127
wire                    MMU_HIT;
128
wire                    NEW_PTB;
129
wire                    PTB_ONE;
130 29 ns32kum
wire    [28:0]   PTE_ADR;
131 9 ns32kum
wire   [31:12]  RADR;
132
wire    [11:4]  TAGA;
133
wire    [23:0]   UPDATE_C;
134
wire    [31:0]   UPDATE_M;
135
wire                    USE_CA;
136
wire                    USER;
137
wire                    WB_ACC;
138
wire                    WEMV;
139
wire                    WR_MRAM;
140
wire    [31:0]   WRDATA;
141
wire                    VIRT_A;
142
wire                    PTE_MUX;
143
wire                    WE_CV;
144
wire    [23:0]   DAT_CV;
145
wire     [4:0]   WADR_CV;
146
wire                    WRSET0;
147 29 ns32kum
wire    [15:0]   BE_SET;
148
wire   [127:0]   DAT_SET;
149
wire    [31:0]   CAP_Q;
150 9 ns32kum
wire                    WRSET1;
151
wire                    SEL_PTB1;
152
wire                    CI;
153 29 ns32kum
wire    [28:0]   ADR_MX;
154 9 ns32kum
wire                    LD_DRAM_A;
155
wire                    VIRTUELL;
156
wire                    NEW_PTB_RUN;
157
wire                    KILL;
158
wire                    LAST_MUX;
159
wire    [31:0]   SET_DAT;
160
wire    [31:0]   ALT_DAT;
161
wire    [31:0]   DAT_MV;
162
wire     [3:0]   RADR_MV;
163
wire     [3:0]   WADR_MV;
164
wire    [31:0]   LAST_DAT;
165
wire                    WRCRAM0;
166
wire                    WRCRAM1;
167
wire                    PROT_ERROR;
168
wire                    AUX_QW;
169
wire                    PD_MUX;
170
wire    [19:0]   PTE_DAT;
171
wire                    PKEEP;
172 29 ns32kum
wire                    XADDR2;
173
wire   [28:12]  TAGDAT;
174 9 ns32kum
 
175
// +++++++++++++++++++ Memories ++++++++++++++++++++
176
 
177 29 ns32kum
reg              [7:0]   DATA0_P [0:255]; // Data Set 0 : 4 kBytes
178
reg              [7:0]   DATA0_O [0:255];
179
reg              [7:0]   DATA0_N [0:255];
180
reg              [7:0]   DATA0_M [0:255];
181
reg              [7:0]   DATA0_L [0:255]; // Data Set 0 : 4 kBytes
182
reg              [7:0]   DATA0_K [0:255];
183
reg              [7:0]   DATA0_J [0:255];
184
reg              [7:0]   DATA0_I [0:255];
185
reg              [7:0]   DATA0_H [0:255]; // Data Set 0 : 4 kBytes
186
reg              [7:0]   DATA0_G [0:255];
187
reg              [7:0]   DATA0_F [0:255];
188
reg              [7:0]   DATA0_E [0:255];
189
reg              [7:0]   DATA0_D [0:255]; // Data Set 0 : 4 kBytes
190
reg              [7:0]   DATA0_C [0:255];
191
reg              [7:0]   DATA0_B [0:255];
192
reg              [7:0]   DATA0_A [0:255];
193
reg        [127:0]       RDDATA0;
194 9 ns32kum
reg             [31:0]   SET_DAT0;
195
 
196 29 ns32kum
reg              [7:0]   DATA1_P [0:255]; // Data Set 1 : 4 kBytes
197
reg              [7:0]   DATA1_O [0:255];
198
reg              [7:0]   DATA1_N [0:255];
199
reg              [7:0]   DATA1_M [0:255];
200
reg              [7:0]   DATA1_L [0:255]; // Data Set 1 : 4 kBytes
201
reg              [7:0]   DATA1_K [0:255];
202
reg              [7:0]   DATA1_J [0:255];
203
reg              [7:0]   DATA1_I [0:255];
204
reg              [7:0]   DATA1_H [0:255]; // Data Set 1 : 4 kBytes
205
reg              [7:0]   DATA1_G [0:255];
206
reg              [7:0]   DATA1_F [0:255];
207
reg              [7:0]   DATA1_E [0:255];
208
reg              [7:0]   DATA1_D [0:255]; // Data Set 1 : 4 kBytes
209
reg              [7:0]   DATA1_C [0:255];
210
reg              [7:0]   DATA1_B [0:255];
211
reg              [7:0]   DATA1_A [0:255];
212
reg        [127:0]       RDDATA1;
213 9 ns32kum
reg             [31:0]   SET_DAT1;
214
 
215 29 ns32kum
reg             [16:0]   TAGSET_0 [0:255];        // Tag Set for Data Set 0 : 256 entries of 17 bits
216
reg             [16:0]   TAG0;
217 9 ns32kum
 
218 29 ns32kum
reg             [16:0]   TAGSET_1 [0:255];        // Tag Set for Data Set 1 : 256 entries of 17 bits
219
reg             [16:0]   TAG1;
220 9 ns32kum
 
221 23 ns32kum
wire    [23:0]   CVALID;
222 9 ns32kum
 
223
reg             [35:0]   MMU_TAGS [0:255];        // Tag Set for MMU : 256 entries of 36 bits
224
reg             [35:0]   MMU_Q;
225
 
226
reg             [31:0]   MMU_VALID [0:15];        // Valid bits for MMU Tag Set : 16 entries of 32 bits
227
reg             [31:0]   MVALID;
228
 
229
assign  ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
230
 
231
assign  RADR    = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
232
 
233 29 ns32kum
assign  ADR_MX  = PTE_MUX ? PTE_ADR : {RADR[28:12],VADR_R[11:2],USE_CA,CA_SET} ;
234 9 ns32kum
 
235 29 ns32kum
assign  KOLLI_A = DMA_MUX ? DMA_AA : DRAM_A[28:4] ;
236 9 ns32kum
 
237
assign  SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
238
 
239
assign  VIRT_A  = ~CINVAL[0] & VIRTUELL;
240
 
241
assign  USER    = ~MCR_FLAGS[3] & PSR_USER;
242
 
243 29 ns32kum
assign  ADDR    = KDET ? {KOLLI_A[28:12],KOLLI_AR} : {RADR[28:12],VADR_R[11:4]} ;
244 9 ns32kum
 
245
assign  TAGA    = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
246
 
247
assign  INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
248
 
249
assign  LAST_MUX = AUX_ALT | AUX_DAT | AUX_QW;
250
 
251
assign  LAST_DAT = LAST_MUX ? ALT_DAT : SET_DAT ;
252
 
253
assign  LD_DRAM_A = ~(DRAM_ACC | PKEEP);
254
 
255
assign  ACC_STAT[4] = IO_ACC;
256
assign  ACC_STAT[5] = CA_HIT;
257
 
258 29 ns32kum
assign  XADDR2 = VADR_R[2] ^ CTRL_QW[1];
259
 
260
always @(posedge BCLK) KOLLI_AR <= KOLLI_A[11:4];
261
 
262 9 ns32kum
always @(posedge BCLK)
263
        if (IO_ACC)
264
                begin
265
                        IO_BE <= ENBYTE;
266
                        IO_DI <= WRDATA;
267 29 ns32kum
                        IO_A  <= {RADR[31:12],VADR_R[11:3],XADDR2,VADR_R[1:0]};
268 9 ns32kum
                end
269
 
270 29 ns32kum
always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[28:0] <= ADR_MX[28:0];
271 9 ns32kum
 
272
always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
273
 
274
always @(posedge BCLK)
275
        begin
276
                DRAM_DI   <= {(PD_MUX ? PTE_DAT[19:16] : ENBYTE),WRDATA[31:16],
277
                                          (PD_MUX ? PTE_DAT[15:0]  : WRDATA[15:0])};
278
                AUX_ALT   <= DFF_QWEXT | IO_RD;
279
                DFF_QWEXT <= IO_RD & SIZE[0] & SIZE[1];
280
                VADR_R    <= VADR;
281
        end
282
 
283 29 ns32kum
always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q;
284 9 ns32kum
 
285
// +++++++++++++++++++++++++  Cache Valid  +++++++++++++++++++
286
 
287 23 ns32kum
NEU_VALID       VALID_RAM(
288
        .BCLK(BCLK),
289
        .VALIN(DAT_CV),
290
        .WADR(WADR_CV),
291
        .WREN(WE_CV),
292
        .RADR(TAGA[11:7]),
293
        .VALOUT(CVALID) );
294 9 ns32kum
 
295
// +++++++++++++++++++++++++  Tag Set 0  +++++++++++++++++++++
296
 
297
always @(posedge BCLK) TAG0 <= TAGSET_0[TAGA];
298
 
299 29 ns32kum
always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= TAGDAT;
300 9 ns32kum
 
301
// +++++++++++++++++++++++++  Tag Set 1  +++++++++++++++++++++
302
 
303
always @(posedge BCLK) TAG1 <= TAGSET_1[TAGA];
304
 
305 29 ns32kum
always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= TAGDAT;
306 9 ns32kum
 
307 29 ns32kum
// +++++++++++++++++++++++++  DIN MUX  +++++++++++++++++++++++
308
 
309
WRPORT  DINMUX(
310
        .WRITE(WRITE),
311
        .DRAM_Q(DRAM_Q),
312
        .DADDR(DRAM_A[3:2]),
313
        .VADDR(VADR_R[3:2]),
314
        .WRDATA(WRDATA),
315
        .ENBYTE(ENBYTE),
316
        .CAP_Q(CAP_Q),
317
        .WDAT(DAT_SET),
318
        .ENB(BE_SET) );
319
 
320 9 ns32kum
// +++++++++++++++++++++++++  Data Set 0  ++++++++++++++++++++
321
 
322
always @(posedge BCLK)
323
        begin
324 29 ns32kum
                RDDATA0[127:120]        <= DATA0_P[VADR[11:4]];
325
                RDDATA0[119:112]        <= DATA0_O[VADR[11:4]];
326
                RDDATA0[111:104]        <= DATA0_N[VADR[11:4]];
327
                RDDATA0[103:96]         <= DATA0_M[VADR[11:4]];
328
                RDDATA0[95:88]          <= DATA0_L[VADR[11:4]];
329
                RDDATA0[87:80]          <= DATA0_K[VADR[11:4]];
330
                RDDATA0[79:72]          <= DATA0_J[VADR[11:4]];
331
                RDDATA0[71:64]          <= DATA0_I[VADR[11:4]];
332
                RDDATA0[63:56]          <= DATA0_H[VADR[11:4]];
333
                RDDATA0[55:48]          <= DATA0_G[VADR[11:4]];
334
                RDDATA0[47:40]          <= DATA0_F[VADR[11:4]];
335
                RDDATA0[39:32]          <= DATA0_E[VADR[11:4]];
336
                RDDATA0[31:24]          <= DATA0_D[VADR[11:4]];
337
                RDDATA0[23:16]          <= DATA0_C[VADR[11:4]];
338
                RDDATA0[15:8]           <= DATA0_B[VADR[11:4]];
339
                RDDATA0[7:0]             <= DATA0_A[VADR[11:4]];
340 9 ns32kum
        end
341
 
342 29 ns32kum
always @(RDDATA0 or VADR_R)
343
        case (VADR_R[3:2])
344
          2'b00 : SET_DAT0 <= RDDATA0[31:0];
345
          2'b01 : SET_DAT0 <= RDDATA0[63:32];
346
          2'b10 : SET_DAT0 <= RDDATA0[95:64];
347
          2'b11 : SET_DAT0 <= RDDATA0[127:96];
348
        endcase
349
 
350
always @(posedge BCLK)
351 9 ns32kum
        if (WRSET0)
352
                begin
353 29 ns32kum
                        if (BE_SET[15]) DATA0_P[VADR_R[11:4]] <= DAT_SET[127:120];
354
                        if (BE_SET[14]) DATA0_O[VADR_R[11:4]] <= DAT_SET[119:112];
355
                        if (BE_SET[13]) DATA0_N[VADR_R[11:4]] <= DAT_SET[111:104];
356
                        if (BE_SET[12]) DATA0_M[VADR_R[11:4]] <= DAT_SET[103:96];
357
                        if (BE_SET[11]) DATA0_L[VADR_R[11:4]] <= DAT_SET[95:88];
358
                        if (BE_SET[10]) DATA0_K[VADR_R[11:4]] <= DAT_SET[87:80];
359
                        if (BE_SET[9])  DATA0_J[VADR_R[11:4]] <= DAT_SET[79:72];
360
                        if (BE_SET[8])  DATA0_I[VADR_R[11:4]] <= DAT_SET[71:64];
361
                        if (BE_SET[7])  DATA0_H[VADR_R[11:4]] <= DAT_SET[63:56];
362
                        if (BE_SET[6])  DATA0_G[VADR_R[11:4]] <= DAT_SET[55:48];
363
                        if (BE_SET[5])  DATA0_F[VADR_R[11:4]] <= DAT_SET[47:40];
364
                        if (BE_SET[4])  DATA0_E[VADR_R[11:4]] <= DAT_SET[39:32];
365
                        if (BE_SET[3])  DATA0_D[VADR_R[11:4]] <= DAT_SET[31:24];
366
                        if (BE_SET[2])  DATA0_C[VADR_R[11:4]] <= DAT_SET[23:16];
367
                        if (BE_SET[1])  DATA0_B[VADR_R[11:4]] <= DAT_SET[15:8];
368
                        if (BE_SET[0])  DATA0_A[VADR_R[11:4]] <= DAT_SET[7:0];
369 9 ns32kum
                end
370
 
371
// +++++++++++++++++++++++++  Data Set 1  ++++++++++++++++++++
372
 
373
always @(posedge BCLK)
374
        begin
375 29 ns32kum
                RDDATA1[127:120]        <= DATA1_P[VADR[11:4]];
376
                RDDATA1[119:112]        <= DATA1_O[VADR[11:4]];
377
                RDDATA1[111:104]        <= DATA1_N[VADR[11:4]];
378
                RDDATA1[103:96]         <= DATA1_M[VADR[11:4]];
379
                RDDATA1[95:88]          <= DATA1_L[VADR[11:4]];
380
                RDDATA1[87:80]          <= DATA1_K[VADR[11:4]];
381
                RDDATA1[79:72]          <= DATA1_J[VADR[11:4]];
382
                RDDATA1[71:64]          <= DATA1_I[VADR[11:4]];
383
                RDDATA1[63:56]          <= DATA1_H[VADR[11:4]];
384
                RDDATA1[55:48]          <= DATA1_G[VADR[11:4]];
385
                RDDATA1[47:40]          <= DATA1_F[VADR[11:4]];
386
                RDDATA1[39:32]          <= DATA1_E[VADR[11:4]];
387
                RDDATA1[31:24]          <= DATA1_D[VADR[11:4]];
388
                RDDATA1[23:16]          <= DATA1_C[VADR[11:4]];
389
                RDDATA1[15:8]           <= DATA1_B[VADR[11:4]];
390
                RDDATA1[7:0]             <= DATA1_A[VADR[11:4]];
391 9 ns32kum
        end
392
 
393 29 ns32kum
always @(RDDATA1 or VADR_R)
394
        case (VADR_R[3:2])
395
          2'b00 : SET_DAT1 <= RDDATA1[31:0];
396
          2'b01 : SET_DAT1 <= RDDATA1[63:32];
397
          2'b10 : SET_DAT1 <= RDDATA1[95:64];
398
          2'b11 : SET_DAT1 <= RDDATA1[127:96];
399
        endcase
400
 
401
always @(posedge BCLK)
402 9 ns32kum
        if (WRSET1)
403
                begin
404 29 ns32kum
                        if (BE_SET[15]) DATA1_P[VADR_R[11:4]] <= DAT_SET[127:120];
405
                        if (BE_SET[14]) DATA1_O[VADR_R[11:4]] <= DAT_SET[119:112];
406
                        if (BE_SET[13]) DATA1_N[VADR_R[11:4]] <= DAT_SET[111:104];
407
                        if (BE_SET[12]) DATA1_M[VADR_R[11:4]] <= DAT_SET[103:96];
408
                        if (BE_SET[11]) DATA1_L[VADR_R[11:4]] <= DAT_SET[95:88];
409
                        if (BE_SET[10]) DATA1_K[VADR_R[11:4]] <= DAT_SET[87:80];
410
                        if (BE_SET[9])  DATA1_J[VADR_R[11:4]] <= DAT_SET[79:72];
411
                        if (BE_SET[8])  DATA1_I[VADR_R[11:4]] <= DAT_SET[71:64];
412
                        if (BE_SET[7])  DATA1_H[VADR_R[11:4]] <= DAT_SET[63:56];
413
                        if (BE_SET[6])  DATA1_G[VADR_R[11:4]] <= DAT_SET[55:48];
414
                        if (BE_SET[5])  DATA1_F[VADR_R[11:4]] <= DAT_SET[47:40];
415
                        if (BE_SET[4])  DATA1_E[VADR_R[11:4]] <= DAT_SET[39:32];
416
                        if (BE_SET[3])  DATA1_D[VADR_R[11:4]] <= DAT_SET[31:24];
417
                        if (BE_SET[2])  DATA1_C[VADR_R[11:4]] <= DAT_SET[23:16];
418
                        if (BE_SET[1])  DATA1_B[VADR_R[11:4]] <= DAT_SET[15:8];
419
                        if (BE_SET[0])  DATA1_A[VADR_R[11:4]] <= DAT_SET[7:0];
420 9 ns32kum
                end
421
 
422
DCACHE_SM       DC_SM(
423
        .BCLK(BCLK),
424
        .BRESET(BRESET),
425
        .VIRTUELL(VIRTUELL),
426
        .IO_SPACE(IO_SPACE),
427
        .MDONE(MDONE),
428
        .MMU_HIT(MMU_HIT),
429
        .CA_HIT(CA_HIT),
430
        .READ(READ),
431
        .WRITE(WRITE),
432
        .ZTEST(ZTEST),
433
        .RMW(RMW),
434 12 ns32kum
        .QWATWO(QWATWO),
435 9 ns32kum
        .USE_CA(USE_CA),
436
        .PTB_WR(PTB_WR),
437
        .PTB_SEL(PTB_SEL),
438
        .SEL_PTB1(SEL_PTB1),
439
        .IO_READY(IO_READY),
440
        .USER(USER),
441
        .PROTECT(ACC_STAT[3]),
442
        .PROT_ERROR(PROT_ERROR),
443
        .ENWR(ENWR),
444
        .WB_ACC(WB_ACC),
445
        .ADR_EQU(ADR_EQU),
446
        .IC_PREQ(IC_PREQ),
447
        .CAPDAT(CAPDAT[31:0]),
448 29 ns32kum
        .CPU_OUT(DP_Q[60:44]),
449 23 ns32kum
        .DMA_CHK(DMA_CHK),
450 9 ns32kum
        .IC_VA(IC_VA),
451
        .ICTODC(ICTODC),
452
        .VADR_R(VADR_R[31:12]),
453
        .NEW_PTB(NEW_PTB),
454
        .PTB_ONE(PTB_ONE),
455
        .DRAM_ACC(DRAM_ACC),
456
        .DRAM_WR(DRAM_WR),
457
        .IO_ACC(IO_ACC),
458
        .IO_RD(IO_RD),
459
        .IO_WR(IO_WR),
460
        .PTE_STAT(PTE_STAT),
461
        .ABORT(ACC_STAT[1]),
462
        .WR_MRAM(WR_MRAM),
463
        .CUPDATE(CUPDATE),
464
        .AUX_DAT(AUX_DAT),
465
        .PTE_MUX(PTE_MUX),
466
        .ACC_OK(ACC_STAT[0]),
467
        .ABO_LEVEL1(ACC_STAT[2]),
468
        .IACC_STAT(IACC_STAT),
469
        .KOMUX(KOMUX),
470
        .KDET(KDET),
471
        .HIT_ALL(HIT_ALL),
472
        .DMA_MUX(DMA_MUX),
473
        .HLDA(HLDA),
474
        .RWVAL(RWVAL[1:0]),
475
        .RWVFLAG(RWVFLAG),
476
        .IC_SIGS(IC_SIGS),
477
        .MMU_DIN(MMU_DIN),
478
        .PD_MUX(PD_MUX),
479
        .PKEEP(PKEEP),
480
        .PTE_ADR(PTE_ADR),
481
        .PTE_DAT(PTE_DAT));
482
 
483
CA_MATCH        DCA_COMPARE(
484
        .INVAL_L(CINVAL[0]),
485
        .CI(CI),
486
        .MMU_HIT(MMU_HIT),
487
        .WRITE(WRITE),
488
        .KDET(KDET),
489 29 ns32kum
        .ADDR({RADR[31:29],ADDR}),
490 9 ns32kum
        .CFG(CFG),
491
        .ENDRAM(ENDRAM),
492
        .CVALID(CVALID),
493
        .TAG0(TAG0),
494
        .TAG1(TAG1),
495
        .CA_HIT(CA_HIT),
496
        .CA_SET(CA_SET),
497
        .WB_ACC(WB_ACC),
498
        .USE_CA(USE_CA),
499 23 ns32kum
        .DRAMSZ(DRAMSZ),
500 9 ns32kum
        .IO_SPACE(IO_SPACE),
501
        .KILL(KILL),
502
        .DC_ILO(RWVAL[2]),
503
        .UPDATE(UPDATE_C));
504
 
505
DCA_CONTROL     DCA_CTRL(
506
        .BCLK(BCLK),
507
        .BRESET(BRESET),
508
        .CA_SET(CA_SET),
509
        .HIT_ALL(HIT_ALL),
510
        .UPDATE(UPDATE_C),
511
        .VADR_R(ADDR[11:7]),
512
        .DRAM_ACC(DRAM_ACC),
513
        .CUPDATE(CUPDATE),
514
        .KILL(KILL),
515
        .WRITE(WRITE),
516 29 ns32kum
        .USE_CA(DRAM_A[1]),
517
        .INHIBIT(INHIBIT),
518 9 ns32kum
        .INVAL_A(CINVAL[1]),
519 29 ns32kum
        .MDONE(MDONE),
520 9 ns32kum
        .DAT_CV(DAT_CV),
521
        .WADR_CV(WADR_CV),
522
        .WE_CV(WE_CV),
523
        .INIT_CA_RUN(INIT_CA_RUN),
524
        .WRCRAM0(WRCRAM0),
525
        .WRCRAM1(WRCRAM1),
526
        .WRSET0(WRSET0),
527
        .WRSET1(WRSET1));
528
 
529
MMU_MATCH       MMU_COMPARE(
530
        .USER(USER),
531
        .WRITE(WRITE),
532
        .READ(READ),
533
        .RMW(RMW),
534
        .IVAR(IVAR),
535
        .MCR_FLAGS(MCR_FLAGS[2:0]),
536
        .MMU_VA(MMU_Q[35:20]),
537
        .MVALID(MVALID),
538
        .VADR_R(VADR_R[31:12]),
539
        .MMU_HIT(MMU_HIT),
540
        .PROT_ERROR(PROT_ERROR),
541
        .VIRTUELL(VIRTUELL),
542
        .CI(CI),
543
        .SEL_PTB1(SEL_PTB1),
544
        .UPDATE(UPDATE_M));
545
 
546
MMU_UP  MMU_CTRL(
547
        .BCLK(BCLK),
548
        .BRESET(BRESET),
549
        .NEW_PTB(NEW_PTB),
550
        .IVAR(IVAR[1]),
551
        .PTB1(PTB_ONE),
552
        .WR_MRAM(WR_MRAM),
553
        .MVALID(MVALID),
554
        .UPDATE(UPDATE_M),
555
        .VADR(VADR[19:16]),
556
        .VADR_R(VADR_R[19:16]),
557
        .WE_MV(WEMV),
558
        .NEW_PTB_RUN(NEW_PTB_RUN),
559
        .DAT_MV(DAT_MV),
560
        .RADR_MV(RADR_MV),
561
        .WADR_MV(WADR_MV));
562
 
563
// +++++++++++++++++++++++++  MMU Valid  +++++++++++++++++++++
564
 
565
always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];
566
 
567
always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;
568
 
569
// +++++++++++++++++++++++++  MMU Tags  ++++++++++++++++++++++
570
 
571
always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];
572
 
573
always @(negedge BCLK) if (WR_MRAM) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};
574
 
575
RD_ALIGNER      RD_ALI(
576
        .BCLK(BCLK),
577
        .ACC_OK(ACC_STAT[0]),
578 29 ns32kum
        .REG_OUT(CTRL_QW[0]),
579 9 ns32kum
        .PACKET(PACKET),
580
        .RDDATA(LAST_DAT),
581
        .SIZE(SIZE),
582
        .CA_HIT(CA_HIT),
583
        .DP_DI(DP_DI),
584
        .AUX_QW(AUX_QW));
585
 
586
WR_ALIGNER      WR_ALI(
587
        .DP_Q(DP_Q),
588
        .PACKET(PACKET),
589
        .SIZE(SIZE),
590
        .ENBYTE(ENBYTE),
591
        .WRDATA(WRDATA));
592
 
593 29 ns32kum
DEBUG_AE  DBGAE(
594 9 ns32kum
        .DBG_IN(DBG_IN),
595
        .READ(READ),
596
        .WRITE(WRITE),
597
        .USER(USER),
598
        .VIRTUELL(VIRTUELL),
599
        .ACC_OK(ACC_STAT[0]),
600
        .VADR_R(VADR_R[31:2]),
601
        .MMU_Q(MMU_Q[19:0]),
602
        .ENBYTE(ENBYTE),
603
        .DBG_HIT(DBG_HIT));
604 29 ns32kum
 
605
FILTCMP  FILT_CMP(
606
        .RADR({RADR[28:12],VADR_R[11:4]}),
607
        .DRAMSZ(DRAMSZ),
608
        .DRAM_A(DRAM_A[28:4]),
609
        .TAGDAT(TAGDAT),
610
        .ADR_EQU(ADR_EQU));
611 9 ns32kum
 
612
endmodule

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