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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

// This file is part of the M32632 project

// http://opencores.org/project,m32632

//

// Filename: DECODER.v

// Version:  1.1 bug fix

// History:  1.0 first release of 30 Mai 2015

// Date:     21 January 2016

//

// Copyright (C) 2016 Udo Moeller

// 

// This source file may be used and distributed without 

// restriction provided that this copyright statement is not 

// removed from the file and that any derivative work contains 

// the original copyright notice and the associated disclaimer.

// 

// This source file is free software; you can redistribute it 

// and/or modify it under the terms of the GNU Lesser General 

// Public License as published by the Free Software Foundation;

// either version 2.1 of the License, or (at your option) any 

// later version. 

// 

// This source is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied 

// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 

// PURPOSE. See the GNU Lesser General Public License for more 

// details. 

// 

// You should have received a copy of the GNU Lesser General 

// Public License along with this source; if not, download it 

// from http://www.opencores.org/lgpl.shtml 

// 

// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      Modules contained in this file:

//      DECODER         Instruction Decoding and Flow Control

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module DECODER ( BCLK, BRESET, INT_N, NMI_N, ANZ_VAL, OPREG, CFG, PSR, ACC_DONE, DC_ABORT, IC_ABORT, ACB_ZERO, DONE,

                                 PC_SAVE, STRING, INIT_DONE, ILL, UNDEF, TRAPS, IC_READ, STOP_CINV,

                                 GENSTAT, DISP, IMME_Q, DISP_BR, USED, NEW, LOAD_PC, NEXT_PCA, RDAA, RDAB, OPER, START, LD_OUT, LD_DIN, LD_IMME,

                                 INFO_AU, ACC_FELD, WREN, WRADR, WMASKE, WR_REG, DETOIP, MMU_UPDATE, RESTART, STOP_IC, RWVAL, ENA_HK, ILO, COP_OP );

        input                   BCLK,BRESET;

        input                   INT_N,NMI_N;    // external inputs

        input    [2:0]   ANZ_VAL;

        input   [55:0]   OPREG;                  // the OPREG contains the bytes to decode, OPREG[55:32] are don't care

        input    [8:0]   CFG;                    // CONFIG : many bits are don't-care

        input   [11:0]   PSR;

        input                   ACC_DONE;

        input                   DC_ABORT,IC_ABORT;

        input                   ACB_ZERO;

        input                   DONE;

        input   [31:0]   PC_SAVE;

        input    [4:0]   STRING;

        input                   INIT_DONE;

        input                   ILL,UNDEF;

        input    [5:0]   TRAPS;

        input                   IC_READ;

        input                   STOP_CINV;              // not to mix it up with STOP_IC

        output   [2:0]   GENSTAT;

        output  [31:0]   DISP,IMME_Q,DISP_BR;    // three main data busses : Displacement, Immediate and Displacement for Branch

        output   [2:0]   USED;

        output                  NEW;

        output                  LOAD_PC;

        output                  NEXT_PCA;

        output   [7:0]   RDAA,RDAB;

        output  [10:0]   OPER;

        output   [1:0]   START,LD_OUT;

        output                  LD_DIN,LD_IMME;

        output   [6:0]   INFO_AU;

        output  [14:0]   ACC_FELD;

        output                  WREN;

        output   [5:0]   WRADR;

        output   [1:0]   WMASKE;

        output  reg             WR_REG;

        output  [12:0]   DETOIP;

        output   [1:0]   MMU_UPDATE;

        output                  RESTART;

        output                  STOP_IC;

        output   [2:0]   RWVAL;

        output                  ENA_HK;

        output  reg             ILO;

        output  [23:0]   COP_OP;

        reg             [31:0]   DISP,disp_val;

        reg             [10:0]   oper_i;

        reg              [2:0]   USED;

        reg             [14:0]   ACC_FELD;

        reg              [1:0]   ldoreg;

        reg                             wren_i;

        reg              [5:0]   wradr_i;

        reg              [1:0]   wmaske_i;

        reg              [1:0]   START;

        reg             [23:0]   COP_OP;

        reg                             spupd_i;

        reg              [3:0]   disp_sel;

        reg             [52:0]   op1_feld;

        reg             [47:0]   op2_feld;

        reg             [47:0]   op3_feld;

        reg             [47:0]   op_feld_reg;

        reg             [31:0]   imme_i;

        reg              [2:0]   valid;

        reg              [7:0]   phase_reg;

        reg              [3:0]   di_stat;        // Displacement Status

        reg              [3:0]   cc_feld;

        reg              [1:0]   ex_br_op;

        reg                             acb_reg;

        reg                             jsr_flag;

        reg              [8:0]   waitop,wait_reg;

        reg                             branch;

        reg              [3:0]   dim_feld;

        reg             [66:0]   new_op;

        reg                             short_op_reg;

        reg             [15:0]   idx_reg;

        reg             [35:0]   gen_src1;

        reg             [33:0]   gen_src2;

        reg                             qw_flag;

        reg                             long_reg;

        reg                             new_spsel;

        reg                             s_user,old_su;

        reg              [1:0]   stack_sel;      // Stack select for USER and SUPERVISOR

        reg              [1:0]   s_mod;          // Modifier for Stack select

        reg                             upd_info,dw_info;

        reg              [2:0]   rpointer;

        reg              [5:0]   resto;          // for RESTORE

        reg                             init_rlist;

        reg                             new_fp;

        reg                             format1;

        reg                             ldpc_phase;

        reg                             reti_flag;

        reg                             no_t2p;

        reg                             iabort,ia_save;

        reg                             mmu_sel;

        reg              [1:0]   nmi_reg;

        reg                             nmi_flag,int_flag;

        reg                             type_nmi;

        reg              [3:0]   exc_vector;

        reg                             phase_exc;

        reg              [3:0]   ovf_pipe;

        reg                             dbg_s,dbg_trap,dbg_en,addr_cmp;

        reg                             ssrc_flag,sdest_flag;

        reg                             op_setcfg,setcfg_lsb;

        reg                             inss_op;

        reg                             exin_cmd,extract;       // EXT/INS

        reg                             bit_reg;        // Flag for Bit opcodes : Source2 = Reg

        reg                             kurz_st;        // Flag for MOVM/CMPM

        reg                             kill_opt;       // Flag for optimized MOVS

        reg                             cmps_flag;      // Flag for CMPS

        reg                             skps_flag;      // Flag for SKPS

        reg                             mt_flag;        // Flag for Match and Translate

        reg                             spu_block;      // block of SP update at Long operation

        reg                             dia_op,dia_flag;        // Flag for DIA

        reg                             m_ussu,m_usel,dc_user;  // MOVUS/SU

        reg                             rwval_flag,wrval_flag;  // RDVAL/WRVAL

        reg                             cinv_flag;      // Flag for CINV

        reg              [5:0]   lmrreg;

        reg                             no_init,a_ivar;

        reg                             index_cmd;

        reg                             stop_d;

        reg                             dc_ilo;

        wire                    PHASE_0;

        wire     [7:0]   phase_ein;      // Phase after ABORT has changed the content to 0

        wire                    de_flag,ivec_flag;

        wire                    next;

        wire    [18:0]   new_addr,pop_fp,save_pc;

        wire    [13:0]   new_regs;

        wire     [7:0]   new_ph,ppfp;

        wire     [7:0]   new_nx;

        wire                    op_1byte,op_12byte,op_2byte,op_3byte;

        wire                    jump;

        wire                    short_op,short_def;

        wire                    acb_op,acb_flag;

        wire                    zero,carry_psr,negativ,larger,flag;

        wire                    valid_size;

        wire                    op_ok;

        wire                    stop;

        wire    [47:0]   opc_bits;

        wire    [47:0]   op_feld;

        wire     [2:0]   atys,atyd;

        wire     [3:0]   auop_s,auop_d;

        wire                    long,src2_flag,dest_flag;

        wire     [6:0]   src_1,src_2,src_1l,src_2l;

        wire     [1:0]   src1_le,src2_le;

        wire                    acc1,acc2;

        wire                    spupd;

        wire     [6:0]   saver;  // for SAVE

        wire     [2:0]   reg_nr;

        wire                    save_reg;

        wire                    ld_disp,disp_ok;

        wire                    store_pc;

        wire                    do_xor;

        wire                    do_long;

        wire     [1:0]   idx_n,n_idx;

        wire                    idx;

        wire     [1:0]   otype;

        wire    [10:0]   opera,op_str,op_sho;

        wire     [5:0]   dest_r,dest_rl;

        wire                    phase_idx;

        wire    [15:0]   idx_bytes,idx_feld;

        wire     [3:0]   idx_1,idx_2;

        wire     [4:0]   src1_addr,src2_addr;

        wire     [6:0]   usp_1,usp_2;

        wire    [33:0]   tos_oper;

        wire    [18:0]   adrd1,exr11,exr12,adrd2,adwr2,exr22,exw22,re_wr,st_src,st_src2,st_dest,st_len,st_trde,st_trs2;

        wire     [7:0]   phrd1,phrd2,phwr2;

        wire     [6:0]   rega1,irrw1,rega2,irrw2;

        wire     [3:0]   nxrd1,nxrw2;

        wire                    rmw;

        wire     [6:0]   quei1,quet1;            // Registeradr

        wire     [7:0]   endea,goacb,dowait;     // Phase

        wire     [3:0]   diacb;                          // DIMM access

        wire                    qword;

        wire     [6:0]   stack,no_modul,ttstak;

        wire    [12:0]   pop_1;

        wire                    mpoi_1,mpoi_2;

        wire     [1:0]   src1_tos;               // the code for REUSE is 2'b11

        wire                    svc_flag,bpt_flag,flag_flag,trac_flag;

        wire     [3:0]   misc_vectors;

        wire     [2:0]   psr_code;

        wire                    exception;

        wire                    interrupt;

        wire                    abort;          // DC_ABORT | iabort;

        wire                    abo_int;

        wire                    iabo_fall;

        wire                    abbruch,fpu_trap,dvz_trap;

        wire                    abbruch2;

        wire                    dbg_flag;

        wire                    ovf_op,ovf2_op,ovf_flag;

        wire                    pc_match;

        wire                    no_trap;

        wire    [10:0]   op_psr,op_scp;

        wire    [30:0]   ai_next;

        wire                    set_src,set_dest,clr_sflag;

        wire     [7:0]   rrepa;  // Repair Phase of Abort for String opcodes

        wire     [7:0]   ph_str; // working phase String

        wire                    ph_match;

        wire                    t2p;

        wire                    rw_bit,op_ilo;

        wire                    setcfg;

        wire                    string_ende;

        wire                    wlor;   // Flag to generate WR_REG signal

        wire     [5:0]   wstr0,wstr1,wstr2;

        wire     [6:0]   rstr0,rstr1,rstr2;

        wire                    rett_exc;

        wire                    chk_rmw;

        // Variables for 2- and 3-Byte Dekoder :

        reg              [5:0]   hzr_c;  // CASE Statement

        wire     [1:0]   hzl_a;

        wire     [2:0]   hzl_b;

        wire     [5:0]   hzr_a,hzr_b,hzr_s;

        wire                    hdx_a;

        wire                    hdo_b;

        wire     [3:0]   hdo_a,hdo_c,hdo_e;

        wire     [7:0]   hdo_d;

        wire     [1:0]   hdl_b,hdl_d,hdl_f,hdl_g,hdl_h;

        wire     [2:0]   hdl_a,hdl_c,hdl_e;

        wire     [5:0]   hdr_a,hdr_b,hdr_c,hdr_d,hdr_e,hdr_f,hdr_g,hdr_m;

        wire    [66:0]   state_0,state_group_50,state_group_60;  // for the Gruppe 2 opcodes

        // Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2

        parameter addr_nop      = 19'b10_0000_0000_0_0000_0000; // all parameter to 0

        parameter push_op       = 19'b10_0111_0000_1_1010_0000; // i.e. for BSR, ENTER ...

        parameter push_ea       = 19'b10_0111_0000_1_1010_0011; // SAVE middle

        parameter pop_op        = 19'b10_1011_0010_1_0000_1000; // RET/RESTORE

        parameter adddisp       = 19'b10_0010_0000_0_0000_0011; // for RET : reuse of EA

        parameter adddispn      = 19'b10_0010_0000_0_0000_0000; // for RETT : add Disp to Stack

        parameter save_sp       = 19'b10_0000_0000_1_0000_0000; // u.a. RET : update of Stack

        parameter next_po       = 19'b10_1011_0010_1_0000_1011; // RESTORE middle

        parameter dispmin       = 19'b10_0010_0000_0_0100_0011; // Reuse for ENTER

        parameter rmod_rxp      = 19'b10_1001_0000_1_0000_0100; // MODUL+0 read : SB , SP Update , therefore no LDEA

        parameter rmod_rtt      = 19'b10_1001_0000_0_0000_0100; // MODUL+0 read : SB , no LDEA

        parameter rmod_4        = 19'b10_1011_0000_0_0001_0100; // MODUL+4 read : Link Table Base

        parameter rmod_8        = 19'b10_1011_0000_0_0010_0100; // MODUL+8 read : Program Base

        parameter rdltab        = 19'b10_1010_0000_0_1000_0000; // Link table read - EA Phase

        parameter ea_push       = 19'b10_0110_0000_0_1010_0011; // CXP : 2. Push EA Phase

        parameter ea_min8       = 19'b10_1010_0000_0_1011_0011; // CXP : reuse of MOD+8

        parameter pop_ru        = 19'b10_1010_0010_0_0000_1011; // RXP : EA Phase MOD POP

        parameter rd_icu        = 19'b00_1001_0000_0_1100_0010; // Read ICU : Byte of fix address

        parameter get_vec       = 19'b10_1001_0000_0_01xx_0000; // Read Exception-Vector : Index Exception No.

        parameter get_veci      = 19'b10_1001_0110_0_0000_0000; // Read Exception-Vector : Index external Interrupt

        parameter load_ea       = 19'b10_0010_0000_0_0000_0000; // used for store of TEAR and MSR

        parameter save_msr      = 19'b10_0010_0001_0_0000_0000; // used for store of TEAR and MSR

        parameter ivar_adr      = 19'b10_0000_0100_0_0000_0010; // only pass SRC1

        parameter st_trans      = 19'b00_1001_0100_0_0000_0000; // Translate at String : SRC1 + SRC2 , Byte

        parameter src_x         = 7'hxx;

        parameter dest_x        = 6'hxx;

        parameter imme          = {1'b1,6'hxx};

        parameter frame         = 7'h18;

        parameter ibase         = 7'h1E;

        parameter modul         = 7'h1F;

        parameter w_msr         = 6'h0A;

        parameter w_tear        = 6'h0B;

        parameter fsr_r         = 6'h17;        // not defined register for FSR for opcodes LFSR and SFSR

        parameter temp_l        = 6'h3C;

        parameter temp_h        = 6'h3D;        // second last space for 8B TEMP register

        parameter temp_1        = 6'h3E;        // Backup for register at String operations

        parameter temp_2        = 6'h3F;

        parameter rtmpl         = 7'h3C;

        parameter rtmph         = 7'h3D;

        parameter rtmp1         = 7'h3E;

        parameter rtmp2         = 7'h3F;

        parameter op_mov        = 11'h345;

        parameter op_adr        = 11'h349;

        parameter op_add        = 11'h340;      // for CXP

        parameter op_flip       = 11'h364;      // for CXP : LSHD -16,Ri

        parameter op_lmr        = 11'h36A;      // for LPR CFG, LMR and CINV

        parameter op_wrp        = 11'h387;      // for CXP : write PSR , used also for Exception processing

        parameter op_ldp        = 11'h388;      // for RETT and RETI : load of PSR from Stack

        parameter op_zex        = 11'h076;      // Zero Extension for ICU Vector - is also used at String Option "T"

        parameter op_cop        = 8'hDD;        // Coprozessor Opcode

        // ++++++++++++++++++++++++++  The switch logic for the state machine  +++++++++++++++++++++++++++++

        always @(ANZ_VAL)

                case (ANZ_VAL)

                  3'd0  : valid = 3'b000;

                  3'd1  : valid = 3'b001;

                  3'd2  : valid = 3'b011;

                default : valid = 3'b111;

                endcase

        assign next = ( PHASE_0 ? op_ok :               // Opcode decoded or Exception processed

                                                // Displacement or Immediate operand and external memory access can happen in parallel

                                                // i.e. addressing mode Memory Relative

                                    (  ((~dim_feld[0] | ACC_DONE) & (~dim_feld[3] | di_stat[0]))  // ACC_DONE resets dim_feld

                                                // long operation

                                     & ~(long_reg & ~DONE) ) )

                                                // hard break : abort or fpu_trap or dvz_trap or ovf_flag

                                  | abbruch ;

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) long_reg <= 1'b0;

                  else

                        long_reg <= next ? do_long : long_reg;  // START[1]

        always @(posedge BCLK or negedge BRESET)        // the central phase register

                if (!BRESET) phase_reg <= 8'h0;

                  else

                        if (next) phase_reg <= new_op[47:40];

        always @(*)     // next switch of micro program counter

                casex ({PHASE_0,op_ok,dim_feld[3],di_stat[0]})

                  4'b11_xx : USED = {1'b0,~op_1byte,(op_1byte | op_3byte)};

                  4'b0x_11 : USED = di_stat[3:1];

                  default  : USED = 3'd0;

                endcase

        // Special phases

        assign PHASE_0 = (phase_reg == 8'h00);  // During Phase 0 the opcode is decoded

        assign NEXT_PCA = PHASE_0 & ~ovf_flag & ~dbg_flag;

        // Pulse to transfer from Trace Bit to Pending Trace Bit, only once in the beginning of phase 0

        // The priority is such that a TRACE exception is served before an UNDEFINED/ILLEGAL exception

        always @(posedge BCLK) no_t2p <= PHASE_0 & ~op_ok;

        assign t2p = PHASE_0 & ~no_t2p; // signal to I_PFAD

        // ++++++++++++++++++++++++++  global control signals  ++++++++++++++++

        assign de_flag   = CFG[8];

        assign ivec_flag = CFG[0];

        assign dvz_trap  = TRAPS[1];

        assign fpu_trap  = TRAPS[0];

        always @(posedge BCLK) nmi_reg  <= {nmi_reg[0],NMI_N};   // one clock sync and than falling edge detection

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) nmi_flag <= 1'b0;

                  else nmi_flag <= (nmi_reg == 2'b10) | (nmi_flag & ~(phase_reg == 8'h82));

        always @(posedge BCLK) int_flag <= PSR[11] & ~INT_N;    // one clock to synchronise

        assign stop              = (int_flag | nmi_flag) &   PHASE_0 & ~stop_d;         // neccesary if FPU_TRAP and INT at the same time

        assign interrupt = (int_flag | nmi_flag) & (~PHASE_0 |  stop_d);

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) stop_d <= 1'd0;

                  else stop_d <= stop;

        // ++++++++++++++++++++++++++  Exception processing  +++++++++++++++

        // IC_ABORT is valid if Opcode Decoder cannot continue

        assign iabo_fall = IC_ABORT & (PHASE_0 ? ~op_ok : (~di_stat[0] & dim_feld[3]));

        always @(posedge BCLK) iabort  <= iabo_fall & ~ia_save; // DC_ABORT ist a pulse

        always @(posedge BCLK) ia_save <= iabo_fall;

        // mmu_sel is used in ADDR_UNIT

        always @(posedge BCLK) mmu_sel <= DC_ABORT | (mmu_sel & ~iabort);       // 1 = DCACHE , 0 = ICACHE

        assign MMU_UPDATE[0] = mmu_sel;

        assign abort = DC_ABORT | iabort;

        // that is the end of String loops where interrupts are checked : 8'hC7 & 8'hCF

        assign string_ende = (phase_reg[7:4] == 4'hC) & (phase_reg[2:0] == 3'b111);      // attention : 8'hCF does not exist

        always @(posedge BCLK) if (PHASE_0 || string_ende) type_nmi <= nmi_flag;        // during processing kept stable

        assign svc_flag  = (OPREG[7:0] == 8'hE2) & valid[0];      // Vector  5 : 0101 , Illegal Vector  4 : 0100

        assign bpt_flag  = (OPREG[7:0] == 8'hF2) & valid[0];      // Vector  8 : 1000 , Undefined Vec. 10 : 1010

        assign flag_flag = (phase_reg  == 8'h89) & flag;                // Vector  7 - has an own state

        assign trac_flag = t2p & PSR[10];                                               // Vector  9 : 1001 , PSR[10] = P Bit , Pending Trace

        assign ovf_flag  = (ovf_pipe[3] & flag) | (ovf_pipe[1] & TRAPS[2]);             // Vector 13 : 1101

        assign dbg_flag  = dbg_trap | (dbg_s & PHASE_0);                // Vector 14 : 1110

        // abort + dvz_trap during a opcode, fpu_trap + ovf_flag + dbg_flag later

        assign abbruch  = abort | fpu_trap | dvz_trap | ovf_flag | dbg_flag;    // this 5 stop everything

        assign abbruch2 = abort | fpu_trap | dvz_trap | ovf_flag;       // for exc_vector generation

        // forces the next step of state machine (op_ok), generates otype="11" for Trap Service

        assign exception = interrupt | svc_flag | bpt_flag | ILL | UNDEF | trac_flag | abbruch;

        // a TRACE Exception is done before the opcode execution

        assign misc_vectors = trac_flag ? 4'h9 : {(bpt_flag | UNDEF),(svc_flag | ILL),UNDEF,svc_flag};  // the vectors are exclusiv

        always @(posedge BCLK)

                if (PHASE_0 || abbruch) // ABORTs, fpu_trap, dvz_trap + ovf_flag can happen every time

                  begin

                        exc_vector <= abbruch ? (abbruch2  ? {ovf_flag,(dvz_trap | ovf_flag),~ovf_flag,(fpu_trap | ovf_flag)} : 4'hE)

                                                                  : (interrupt ? {3'b0,nmi_flag} : misc_vectors);       // misc_vectors is default

                  end

                  else

                    if (flag_flag) exc_vector <= 4'h7;  // FLAG-Trap

                      else

                                if (interrupt && string_ende) exc_vector <= {3'b0,nmi_flag};

        assign psr_code[2] = ~psr_code[1];                                              // Absicht : codiert das Sichern des PSR bei Exception-Entry 

        assign psr_code[1] = abort | ILL | UNDEF | trac_flag;   // enable for reseting the P-Bit during write of PSR to stack

        assign psr_code[0] = (interrupt & ~fpu_trap) | abort;    // enable for reseting the I-Bit of new PSR

        // valid codes are x'89 to x'8F

        assign op_psr = {8'b0_00_1000_1,psr_code};      // is used during first clock cylce after exception, is transfered as OPCODE to I_PFAD

        // Specialitiies : ABORT stores address & flags , the Interrrupts read vectors : all is used in big CASE

        assign abo_int = (exc_vector == 4'h2) | (exc_vector[3:1] == 3'b000);

        assign ai_next = (exc_vector == 4'h2) ? {load_ea,8'h84,4'h0} : {rd_icu,8'h82,4'h1};

        assign save_pc = {7'b10_0010_0,dia_flag,7'b00_0_0000,dia_flag,3'b001};  // Exception : PC_ARCHI => EA, special case DIA

        assign no_trap = ~fpu_trap & ~ovf_flag & ~dbg_flag;     // suppresion of WREN and LD_OUT[1] and ADDR_UNIT operation

        // ++++++++++++++++++++++++++  Overflow Trap  ++++++++++++++

        always @(posedge BCLK)

                if (ovf_flag || !PSR[4]) ovf_pipe <= 4'd0;

                  else

                        if (PHASE_0) ovf_pipe <= {ovf_pipe[2],(ovf_op & op_ok),ovf_pipe[0],(ovf2_op & op_ok)};   // V-Bit switches on

        assign ovf_op =  ( ((OPREG[6:2] == 5'b000_11)   // ADDQi

                                          | (OPREG[3:2] == 2'b00)) & (OPREG[1:0] != 2'b10))              // ADDi,ADDCi,SUBi,SUBCi

                                        | ((OPREG[7:0] == 8'h4E) & OPREG[13] & (OPREG[11:10] == 2'b00))  // NEGi,ABSi

                                        | ((OPREG[7:0] == 8'hEE) & ~OPREG[10]);  // CHECKi

        assign ovf2_op =  ((OPREG[6:2] == 5'b100_11) & (OPREG[1:0] != 2'b10))    // ACBi, these overflows have no FLAG

                                        | ((OPREG[13:10] == 4'h1) & (OPREG[7:0] == 8'h4E))       // ASHi

                                        | ( OPREG[13] & (OPREG[11] == OPREG[10]) & (OPREG[7:0] == 8'hCE)); // MULi,DEIi,QUOi,DIVi

        // ++++++++++++++++++++++++++  Debug Trap  ++++++++++++++

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) dbg_s <= 1'b0;

                  else dbg_s <= dbg_trap | (dbg_s & ~((exc_vector == 4'hE) & (phase_reg == 8'h81)));

        always @(posedge BCLK) dbg_en <= op_ok | ~PHASE_0;

        assign pc_match = dbg_en & TRAPS[3] & PHASE_0 & ~exception;     // TRAPS[3] is only combinatorical

        always @(posedge BCLK) dbg_trap <= (pc_match | (addr_cmp & PHASE_0)) & TRAPS[5];        // TRAPS[5] = Enable Trap

        always @(posedge BCLK) addr_cmp <= TRAPS[4] | (addr_cmp & ~PHASE_0);    // TRAPS[4] = CAR HIT

        // ++++++++++++++++++++++++++  Special case String Abort  ++++++++++++++

        // Flags cleared if entry and exit of string operation and during  Abort sequence, not valid for MOVM/CMPM

        // special case UNTIL/WHILE : reset if exit (op_feld_reg[17] = 1 = UNTIL)

        assign clr_sflag =         (phase_reg == 8'hC0) | (phase_reg == 8'hC7) | (phase_reg == 8'hC8) | (phase_reg == 8'h81)

                                           | (((phase_reg == 8'hD7) | (phase_reg == 8'hDF)) & ~(STRING[3] ^ op_feld_reg[17])) ;

        assign set_src   =     (phase_reg == 8'hC1) | (phase_reg == 8'hC9);

        assign set_dest  =     (phase_reg == 8'hC4) | (phase_reg == 8'hCC);

        always @(posedge BCLK or negedge BRESET)        // R1 is modified

                if (!BRESET) ssrc_flag <= 1'b0;

                  else ssrc_flag <= (set_src & ~kurz_st) | (ssrc_flag & ~clr_sflag);

        always @(posedge BCLK or negedge BRESET)        // R2 is modified

                if (!BRESET) sdest_flag <= 1'b0;

                  else sdest_flag <= (set_dest & ~kurz_st) | (sdest_flag & ~clr_sflag);

        assign rrepa = {7'b1000_011,~sdest_flag};       // R1 and if necessary R2 restore

        // ++++++++++++++++++++++++++  The one byte opcodes  +++++++++++++++++++

        // The one byte opcodes have a special case : one byte opcode but the second byte should be valid too

        // Used with SAVE, RESTORE, ENTER and EXIT with their reg list. 

        // The advantage is that the reg list is store in op_feld_reg.

        //      [52:34] addressing

        //      [33:20] register

        //      [19:18] 1 or 2 Byte opcode

        //      [17:16] BSR/BR

        //       [15:8] next phase

        //        [7:4] START + LD_OUT

        //        [3:0] operand access : Displacement or Speicher

        always @(*)             // SVC (E2) and BPT (F2) decode as exception

                casex (OPREG[7:0])

                        8'hxA : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b01,8'h01,4'h0,4'hE};       // Bcc , DISP read

                        8'h02 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b10,8'h01,4'h0,4'hE};       // BSR , DISP read

                        8'h12 : op1_feld = {pop_op  , src_x, stack, 2'b01,2'b00,8'h2A,4'h0,4'h1};       // RET , DISP later

                        8'h22 : op1_feld = {rmod_4      , src_x, modul, 2'b01,2'b00,8'h35,4'h0,4'h1};   // CXP

                        8'h32 : op1_feld = {pop_op,   src_x, stack, 2'b01,2'b00,8'h40,4'h0,4'h1};       // RXP

                        8'h42 : op1_feld = {pop_op,       src_x, stack, 2'b01,2'b00,8'h46,4'h0,4'h1};   // RETT