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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

// This file is part of the M32632 project

// http://opencores.org/project,m32632

//

// Filename: DP_FPU.v

// Version:  1.0

// Date:     30 May 2015

//

// Copyright (C) 2015 Udo Moeller

// 

// This source file may be used and distributed without 

// restriction provided that this copyright statement is not 

// removed from the file and that any derivative work contains 

// the original copyright notice and the associated disclaimer.

// 

// This source file is free software; you can redistribute it 

// and/or modify it under the terms of the GNU Lesser General 

// Public License as published by the Free Software Foundation;

// either version 2.1 of the License, or (at your option) any 

// later version. 

// 

// This source is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied 

// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 

// PURPOSE. See the GNU Lesser General Public License for more 

// details. 

// 

// You should have received a copy of the GNU Lesser General 

// Public License along with this source; if not, download it 

// from http://www.opencores.org/lgpl.shtml 

// 

// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      Modules contained in this file:

//      1. PREPDATA     Prepare data for the big multiplier

//      2. BCDADDER     4 bit BCD adder

//      3. DFPU_BCD             Binary coded decimal (BCD) adder and subtractor

//      4. DFPU_ADDSUB  Double precision floating point adder and subtractor

//      5. DFPU_MISC    Double precision floating point miscellaneous operations 

//      6. DFPU_MUL             Double precision floating point multiplier

//      7. DIVI_PREP    Prepare data for the divider

//      8. DFPU_DIV             The divider for all divide opcodes : double, single and integer

//      9. DP_LOGIK             Control logic and result path for different functions

// 10. DP_FPU           Top level of long operations datapath

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      1. PREPDATA     Prepare data for the big multiplier

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module PREPDATA ( START, MEI, DFLOAT, BWD, SRC1, SRC2,

                                  MSD_1, MSD_2, LSD_1, LSD_2, LOAD_MSD, LOAD_LSD1, LOAD_LSD2 );

        input    [1:0]   START;

        input                   MEI,DFLOAT;

        input    [1:0]   BWD;

        input   [31:0]   SRC1,SRC2;

        output [52:32]  MSD_1,MSD_2;

        output  [31:0]   LSD_1,LSD_2;

        output                  LOAD_MSD,LOAD_LSD1,LOAD_LSD2;

        reg             [31:0]   LSD_1,LSD_2;

        assign MSD_1 = MEI ? 21'h0 : {1'b1,SRC1[19:0]};

        assign MSD_2 = MEI ? 21'h0 : {1'b1,SRC2[19:0]};

        always @(MEI or BWD or SRC1)

                casex ({MEI,BWD})

                  3'b100 : LSD_1 = {24'h000000,SRC1[7:0]};

                  3'b101 : LSD_1 = {16'h0000,SRC1[15:0]};

                 default : LSD_1 = SRC1;

                endcase

        always @(MEI or BWD or SRC2)

                casex ({MEI,BWD})

                  3'b100 : LSD_2 = {24'h000000,SRC2[7:0]};

                  3'b101 : LSD_2 = {16'h0000,SRC2[15:0]};

                 default : LSD_2 = SRC2;

                endcase

        assign LOAD_MSD  = (START[0] & MEI) | (START[0] & DFLOAT);        // 1. step data load at DFLOAT

        assign LOAD_LSD1 = (START[0] & MEI) | (START[1] & DFLOAT);       // 2. step execute at DFLOAT

        assign LOAD_LSD2 = (START[1] & MEI) | (START[1] & DFLOAT);      // 2. step execute at DFLOAT

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      2. BCDADDER     4 bit BCD adder

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module BCDADDER ( A_IN, B_IN, CY_IN, SUBP, OUT, CY_OUT );

        input    [3:0]   A_IN,B_IN;

        input                   CY_IN;

        input                   SUBP;

        output   [3:0]   OUT;

        output                  CY_OUT;

        wire     [4:0]   result;

        wire                    over;

        assign result = SUBP ? ({1'b0,A_IN} - {1'b0,B_IN} - {4'b0,CY_IN})

                                                 : ({1'b0,A_IN} + {1'b0,B_IN} + {4'b0,CY_IN});

        assign over = result[4] | (result[3] & (result[2] | result[1]));

                                                                //              if result<0 : -6                                if result>9 : -10

        assign OUT = result[3:0] - (SUBP ? {1'b0,result[4],result[4],1'b0} : {over,1'b0,over,1'b0});

        assign CY_OUT = SUBP ? result[4] : over;

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      3. DFPU_BCD             Binary coded decimal (BCD) adder and subtractor

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module DFPU_BCD ( BCLK, BRESET, START, DO_BCD, BWD, SRC1, SRC2, CY_IN, SUBP, BCD_Q, CY_OUT, BCD_DONE );

        // Byte : 3 cycles in shortest case REG-REG, Word : 4 cycles and Double : 6 cycles

        input                   BCLK;

        input                   BRESET;

        input                   START;  // START[1]

        input                   DO_BCD; // BCD Opcode is valid

        input    [1:0]   BWD;

        input   [31:0]   SRC1,SRC2;      // Source , Destination, data is stable during operation

        input                   CY_IN;  // comes from PSR

        input                   SUBP;   // SUBP = 1 : SUBP , 0 : ADDP

        output  reg     [31:0]   BCD_Q;

        output  reg             CY_OUT; // went to PSR if DONE is valid

        output                  BCD_DONE;

        reg                             run_bcd;

        reg              [1:0]   byte_cou;

        reg             [15:0]   datain;

        wire     [7:0]   result;

        wire                    carry,carry_lsd,carry_msd;

        // START :     _/---\________________

        // byte_cou :  xxxxxx 0 x 1 x 2 x 3 x

        // BCD_DONE :  _____/---\____________  if BWD = Byte

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) run_bcd <= 1'b0;

                  else

                        run_bcd <= (START & DO_BCD) | (run_bcd & (BWD != byte_cou));

        always @(posedge BCLK) byte_cou <= START ? 2'd0 : byte_cou + {1'b0,run_bcd};

        always @(*)

                casex ({START,byte_cou})

                  3'b1_xx : datain = {SRC1[7:0],  SRC2[7:0]};

                  3'b0_00 : datain = {SRC1[15:8], SRC2[15:8]};

                  3'b0_01 : datain = {SRC1[23:16],SRC2[23:16]};

                  3'b0_1x : datain = {SRC1[31:24],SRC2[31:24]};

                endcase

        assign carry = START ? CY_IN : CY_OUT;

        BCDADDER        lsd_inst ( .A_IN(datain[3:0]), .B_IN(datain[11:8]), .CY_IN(carry), .SUBP(SUBP),

                                                   .OUT(result[3:0]), .CY_OUT(carry_lsd) );

        BCDADDER        msd_inst ( .A_IN(datain[7:4]), .B_IN(datain[15:12]), .CY_IN(carry_lsd), .SUBP(SUBP),

                                                   .OUT(result[7:4]), .CY_OUT(carry_msd) );

        always @(posedge BCLK) CY_OUT <= carry_msd;

        always @(posedge BCLK) if (START)                        BCD_Q[7:0]   <= result;

        always @(posedge BCLK) if (byte_cou == 2'd0) BCD_Q[15:8]  <= result;

        always @(posedge BCLK) if (byte_cou == 2'd1) BCD_Q[23:16] <= result;

        always @(posedge BCLK) if (byte_cou[1])          BCD_Q[31:24] <= result;

        assign BCD_DONE = run_bcd & (BWD == byte_cou);

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      4. DFPU_ADDSUB  Double precision floating point adder and subtractor

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module DFPU_ADDSUB ( BCLK, START, SRC1, SRC2, MAN1, MAN2, SRCFLAGS, BWD, SELECT, OUT, IOUT, CMPRES );

        input                   BCLK;

        input    [1:0]   START;

        input   [31:0]   SRC1,SRC2;      // The input data

        input   [20:0]   MAN1,MAN2;

        input    [5:0]   SRCFLAGS;       // NAN, ZERO and SIGN of operands

        input    [1:0]   BWD;            // size of integer

        input    [3:0]   SELECT;         // upper 2 bits : R.T.F. code

        output  [69:0]   OUT;

        output  [31:0]   IOUT;           // result of ROUNDLi/TRUNCLi/FLOORLi = R.T.F.

        output  [1:0]    CMPRES;

        reg             [69:0]   outreg;

        reg             [31:0]   IOUT;

        // MOViL   : 2 cycles

        // ROUNDLi : 3 cycles (+TRUNC & FLOOR)

        // ADD/SUB : 4 cycles

        // CMP     : 2 cycles

        // ++++++++++++++++++++++++++++++++++

        // MOViL : 1. Pipeline stage : needs 3 cycles

        reg  [31:8]     movdat;

        reg      [31:0]  movif;

        reg                     sign_movif;

        always @(BWD or SRC1)

                casex({BWD,SRC1[15],SRC1[7]})

                  4'b00x0 : movdat =  24'h0000_00;                              // Byte

                  4'b00x1 : movdat =  24'hFFFF_FF;

                  4'b010x : movdat = {16'h0000,SRC1[15:8]};             // Word

                  4'b011x : movdat = {16'hFFFF,SRC1[15:8]};

                default   : movdat = SRC1[31:8];                                // Double

                endcase

        // This  pipeline stage for better timing 

        always @(posedge BCLK) movif <= movdat[31] ? (32'h0 - {movdat,SRC1[7:0]}) : {movdat,SRC1[7:0]};   // -2^31 is kept !

        always @(posedge BCLK) sign_movif <= movdat[31];

        // ROUNDLi/TRUNCLi/FLOORLi : 1. pipeline stage : can Opcode-Decoder deliver direct the 64 bit operand ? From register "yes"

        reg                     ovflag,ovflag2;

        reg                     rovfl;

        reg                     minint;

        wire [11:0]      rexdiff,rexo;

        wire            ganzklein;      // Flag for 0

        assign rexdiff = 12'h41D - {1'b0,SRC1[30:20]};  // 4..0 is the right shift value : like Single FP same value space

        // ovflag2 at the end of rounding : Check for Overflow

        always @(posedge BCLK) rovfl <= (ovflag | ovflag2) & (SELECT[1:0] == 2'b11) & ~minint;

        // a large positiv difference is a very small number :

        assign ganzklein = (~rexdiff[11] & (rexdiff[10:5] != 6'b0));    // 0 is implicit via SRC1[30:20]=0

        // Detection of Overflow

        assign rexo = ({1'b0,SRC1[30:20]} - {11'h1FF,~BWD[1]}); // subtract B/W = 3FF , D = 3FE

        always @(BWD or rexo)   // 0 ist in implicitly

                casex (BWD)

                  2'b00 : ovflag = (~rexo[11] & (rexo[10:3] != 8'h0));  // Exponent 0..7 because -128.4 => -128

                  2'b01 : ovflag = (~rexo[11] & (rexo[10:4] != 7'h0));  // Exponent 0..15 look above

                default : ovflag = (~rexo[11] & (rexo[10:5] != 6'h0));  // but Exponent only 0..30

                endcase

        always @(posedge BCLK)

                if (START[1]) minint <= (SRC1 == 32'hC1E0_0000) & (SRC2 == 32'h0) & BWD[1];     // detection of -2^31

        // ++++++++++++++++++++++++++++++++++++

        // ADD/SUB : 1. Pipeline Stage : which operand ist bigger ? Exchange if neccessary

        // SUB/CMP : SRC2 - SRC1

        reg                             ex_null,ma_null,ex_msb,ma_msb;

        reg             [10:0]   expo1,expo2;

        wire    [11:0]   exdiff,exdiff12;

        wire    [20:0]   madiff;

        wire                    switch,nan,sign,sign1,sign2;

        reg              [5:0]   shift1,shift2;

                // Pipeline register :

        reg             [63:0]   muxsrc2;

        reg             [55:3]  pipe1;  // Nummbers for right shifter

        reg      [5:0]   shift;

        reg                             vorz,addflag;

        wire    [52:0]   muxsrc1;

        wire    [32:0]   lowdiff;

        assign nan = (SELECT[1:0] == 2'b11) ? SRCFLAGS[1] : (~SELECT[1] & (SRCFLAGS[3] | SRCFLAGS[1]));  // used at the end

        assign exdiff   = {1'b0,SRC2[30:20]} - {1'b0,SRC1[30:20]};      // Difference of Exponents

        assign madiff   = {1'b0,SRC2[19:0]}  - {1'b0,SRC1[19:0]}; // Difference of Mantissa 

        assign exdiff12 = {1'b0,SRC1[30:20]} - {1'b0,SRC2[30:20]};      // Diff. Exponents exchanged

        always @(posedge BCLK)

                if (START[0])

                  begin

                        ex_null <= (exdiff[10:0] == 11'h0);

                        ma_null <= (madiff[19:0] == 20'h0);

                        ex_msb  <= exdiff[11];

                        ma_msb  <= madiff[20];

                        shift1  <= (exdiff[10:6]   != 5'h0) ? 6'h3F : exdiff[5:0];

                        shift2  <= (exdiff12[10:6] != 5'h0) ? 6'h3F : exdiff12[5:0];

                        expo1   <= SRC1[30:20];

                        expo2   <= SRC2[30:20];

                  end

        assign lowdiff = {1'b0,SRC2} - {1'b0,SRC1};     // LSD compare

        assign switch = ex_msb | (ex_null & (ma_msb | (ma_null & lowdiff[32])));        // exchange ?

        assign muxsrc1 = switch ? {MAN2,SRC2} : {MAN1,SRC1};

        always @(posedge BCLK)  // Pipeline Reg

          begin

                muxsrc2 <= switch  ? {expo1,MAN1,SRC1}   : {expo2,MAN2,SRC2};   // Incl. Exponent & "1" of mantissa

                pipe1 <= SELECT[1] ? (ganzklein ? 53'd0  : {1'b1,SRC1[19:0],SRC2}) : muxsrc1;    // Feeding of R.T.F.

                shift <= SELECT[1] ? {1'b0,rexdiff[4:0]} : (switch ? shift2 : shift1);

          end

        //      SRC2   SRC1     : switch = 0            SRC2   SRC1 : switch = 1

        //        5  +   3  : +(5 + 3) =  8               3  +   5  : +(5 + 3) =  8             SELECT[0] = 0

        //        5  + (-3) : +(5 - 3) =  2               3  + (-5) : -(5 - 3) = -2

        //      (-5) +   3  : -(5 - 3) = -2             (-3) +   5  : +(5 - 3) =  2

        //      (-5) + (-3) : -(5 + 3) = -8             (-3) + (-5) : -(5 + 3) = -8

        //        5  -   3  : +(5 - 3) =  2               3  -   5  : -(5 - 3) = -2             SELECT[0] = 1

        //        5  - (-3) : +(5 + 3) =  8               3  - (-5) : +(5 + 3) =  8

        //      (-5) -   3  : -(5 + 3) = -8             (-3) -   5  : -(5 + 3) = -8

        //      (-5) - (-3) : -(5 - 3) = -2             (-3) - (-5) : +(5 - 3) =  2

        assign sign1 = SRCFLAGS[4];

        assign sign2 = SRCFLAGS[5];

        always @(posedge BCLK)  // Pipeline Reg

          begin

                vorz    <= switch ? (SELECT[0] ^ sign1) : sign2;

                addflag <= ~(SELECT[0] ^ (sign1 ^ sign2));

          end

        // CMPF : 1. Pipeline Stage : first result : is stored one level higer in Reg

        assign CMPRES[1] = ~CMPRES[0] & (switch ? ~sign1 : sign2);       // look table above

        assign CMPRES[0] = (ex_null & ma_null & (sign1 == sign2) & (lowdiff == 33'h0)) | (SRCFLAGS[2] & SRCFLAGS[0]);

        // ++++++++++++++++++++++++++++++++++

        // ADD/SUB + ROUND/TRUNC : 2. Step : Barrelshifter to the right -->

        wire [55:0] brshifta,brshiftb,brshiftc,brshiftd,brshifte,brshiftf;

        // 5..33322222222221111111111   is this picture still correct ? Took over from Single FP

        // 5..2109876543210987654321098765432-10

        // 1..VVVVVVVVVVVVVVVVVVVVVVVV0000000-00        // last 2 bit for rounding

        assign brshifta = shift[5] ? {32'h0,   pipe1[55:33],   (pipe1[32:3] != 30'h0)} : {pipe1,3'h0};

        assign brshiftb = shift[4] ? {16'h0,brshifta[55:17],(brshifta[16:0] != 17'h0)} : brshifta;

        assign brshiftc = shift[3] ? { 8'h0, brshiftb[55:9], (brshiftb[8:0] !=  9'h0)} : brshiftb;

        assign brshiftd = shift[2] ? { 4'h0, brshiftc[55:5], (brshiftc[4:0] !=  5'h0)} : brshiftc;

        assign brshifte = shift[1] ? { 2'h0, brshiftd[55:3], (brshiftd[2:0] !=  3'h0)} : brshiftd;

        assign brshiftf = shift[0] ? { 1'b0, brshifte[55:2], (brshifte[1:0] !=  2'h0)} : brshifte;

        // ++++++++++++++++++++++++++++++++++

        // ROUNDLi/TRUNCLi/FLOORLi : 3. Step : round to Integer

        reg                     car_ry;

        wire  [1:0] inex;

        wire [30:0] compl;

        wire [31:0] iadder;

        wire            restbits;

        assign restbits = (brshiftf[23:0] != 24'h0);

        assign inex     = {brshiftf[24],restbits};              // Inexact-Flag-Data transfered to multiplexer at the end

        always @(SELECT or sign1 or brshiftf or restbits or inex or ganzklein)

                casex (SELECT[3:2])

                    2'b00 : car_ry = sign1 ^ (((brshiftf[25:24] == 2'b11) & ~restbits) | (inex == 2'b11));      // ROUNDLi

                    2'b1x : car_ry = sign1 ? (~ganzklein & (inex == 2'b00)) : 1'b0;     // +numbers like TRUNCLi, -numbers to "-infinity" round

                  default : car_ry = sign1;     // TRUNCLi , simple cut off

                endcase

        assign compl  = sign1 ? ~brshiftf[55:25] : brshiftf[55:25];

        assign iadder = {sign1,compl} + {31'h0,car_ry};

        always @(posedge BCLK) IOUT <= minint ? 32'h8000_0000 : iadder;

        always @(iadder or BWD or sign1)        // special overflow detection i.e. -129 to -255 at Byte

                casex (BWD)                                             // or 127.9 -> 128 = error !

                  2'b00 : ovflag2 = (iadder[8]  != iadder[7]);  // Byte

                  2'b01 : ovflag2 = (iadder[16] != iadder[15]); // Word

                default : ovflag2 = 1'b0;

                endcase

        // ++++++++++++++++++++++++++++++++++

        // ADD/SUB : 3. Step : Addition or Subtraction

        wire    [67:0]   result;

        wire    [55:0]   blshifti;

        wire    [12:0]   shiftl;

        wire                    shift_32;

        wire    [65:0]   add_q;

        // The central adder : the subtraction needs 3 Guard-Bits after LSB for correct rounding

        assign result = {1'b0,muxsrc2,3'b000} + (addflag ? {12'h0,brshiftf} : {12'hFFF,~brshiftf}) + {67'd0,~addflag};

        assign blshifti = SELECT[1] ? {movif,24'h0} : result[55:0];      // Feeding of MOViL, comes from Register

        assign shiftl = SELECT[1] ? 13'h041E : {1'b0,result[67:56]};    // MOViL

        assign shift_32 = (blshifti[55:24] == 32'h0);

        // In case of ADD the result bypasses the barrelshifter : LSB of exponent has changed

        assign add_q = (muxsrc2[53] != result[56]) ? {result[67:3],(result[2:0] != 3'b000)}

                                                                                           : {result[67:56],result[54:2],(result[1:0] != 2'b00)} ;

        // ++++++++++++++++++++++++++++++++++

        // ADD/SUB : 4. Step : Barrelshifter left for SUB and MOViF :

        wire            shift_16,shift_8,shift_4,shift_2,shift_1,zero;

        wire  [1:0] lsb_bl;

        wire [55:0]      blshifta,blshiftb,blshiftc,blshiftd,blshifte,blshiftf;

        wire [12:0]      expol;

        assign blshifta = shift_32 ? {blshifti[23:0],32'h0} : blshifti;

        assign shift_16 = (blshifta[55:40] == 16'h0);

        assign blshiftb = shift_16 ? {blshifta[39:0],16'h0}      : blshifta;

        assign shift_8  = (blshiftb[55:48] == 8'h00);

        assign blshiftc = shift_8  ? {blshiftb[47:0],8'h0}       : blshiftb;

        assign shift_4  = (blshiftc[55:52] == 4'h0);

        assign blshiftd = shift_4  ? {blshiftc[51:0],4'h0}       : blshiftc;

        assign shift_2  = (blshiftd[55:54] == 2'b00);

        assign blshifte = shift_2  ? {blshiftd[53:0],2'b0}       : blshiftd;

        assign shift_1  = ~blshifte[55];

        assign blshiftf = shift_1  ? {blshifte[54:0],1'b0}       : blshifte;

        // Overflow at ROUNDLi/TRUNCLi/FLOORLi is shown in overflow of exponent , SELECT[1] is then 1

        assign expol = shiftl - {7'h00,shift_32,shift_16,shift_8,shift_4,shift_2,shift_1};

        // Inexact at ROUNDLi/TRUNCLi/FLOORLi : evaluation for all one level higher

        assign lsb_bl = (SELECT == 2'b11) ? inex : {blshiftf[2],(blshiftf[1:0] != 2'b0)};

        assign zero =  (~SELECT[1] & SRCFLAGS[2] & SRCFLAGS[0])

                                 | ((blshifti == 56'h0) & ((~addflag & ~SELECT[1]) | (SELECT[1:0] == 2'b10)));

        assign sign = SELECT[1] ? sign_movif : (vorz & ~zero);  // sign for MOViL

        // 2. Pipeline register for ADD , SUB and MOViL 

        always @(posedge BCLK)

                outreg <= (addflag & ~SELECT[1]) ? {nan,zero,sign,1'b0,add_q}

                                                                                 : {nan,zero,sign,expol,blshiftf[54:3],lsb_bl};

        // ++++++++++++++++++++++++++++++++++

        assign OUT = {outreg[69:67],(rovfl ? 2'b01 : outreg[66:65]),outreg[64:0]};

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      5. DFPU_MISC    Double precision floating point miscellaneous operations 

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module DFPU_MISC ( BCLK, START, SRC1, SRC2, SRCFLAG, MIMUX, MODE, OUT );

        input                   BCLK;

        input                   START;

        input   [31:0]   SRC1,SRC2;

        input                   SRCFLAG;

        input                   MIMUX;

        input    [3:0]   MODE;

        output  [69:0]   OUT;

        reg             [69:0]   OUT;

        reg             [63:0]   daten;

        wire    [10:0]   scalb_l;

        wire                    nan,zero,sign;

        wire    [12:0]   lexpo,sexpo;

        wire    [69:0]   scalb_res,logb_res,fl_lf;

        always @(posedge BCLK) if (START) daten <= {(MIMUX ? {daten[31],scalb_l,daten[19:0]}: SRC1),SRC2};

        assign nan  = MODE[0] ? (daten[62:55] == 8'hFF) : (daten[62:52] == 11'h7FF);

        assign zero = MODE[0] ? (daten[62:55] == 8'h00) : (daten[62:52] == 11'h000);

        assign sign = daten[63] & ~zero;

        assign lexpo = {5'b0,daten[62:55]} + 13'h0380;  // -7F + 3FF

        assign sexpo = (daten[62:52] > 11'h47E) ? 13'h0FFF

                                                                                        : ((daten[62:52] < 11'h381) ? 13'h0 : {2'b0,{4{daten[62]}},daten[58:52]});

        assign fl_lf = MODE[0] ? {nan,zero,sign,lexpo,daten[54:32],31'h0}                                                                                // MOVFL

                                                   : {nan,zero,sign,sexpo,daten[51:29],28'h0,daten[29:28],(daten[27:0] != 28'h0)};       // MOVLF

        // +++++++++++++++++++++++++++  LOGBf  +++++++++++++++++++++++++++++++++++

        wire                    logb_null;

        wire     [9:0]   sel_data,unbiased,shift_l8,shift_l4,shift_l2;