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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
//      Filename:       ICACHE.v
//      Version:        3.0 Cache Interface reworked
//      History:        2.0 50 MHz release of 14 August 2016
//                              1.0 first release of 30 Mai 2015
//      Date:           2 December 2018
//
// Copyright (C) 2018 Udo Moeller
// 
// This source file may be used and distributed without 
// restriction provided that this copyright statement is not 
// removed from the file and that any derivative work contains 
// the original copyright notice and the associated disclaimer.
// 
// This source file is free software; you can redistribute it 
// and/or modify it under the terms of the GNU Lesser General 
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any 
// later version. 
// 
// This source is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied 
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
// PURPOSE. See the GNU Lesser General Public License for more 
// details. 
// 
// You should have received a copy of the GNU Lesser General 
// Public License along with this source; if not, download it 
// from http://www.opencores.org/lgpl.shtml 
// 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//      Modules contained in this file:
//      ICACHE          the instruction cache of M32632
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
module ICACHE( BCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
                           KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR,
                           INHIBIT, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
                           DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
 
input                   BCLK;
input    [2:0]   DRAMSZ;
input                   MDONE;
input                   BRESET;
input                   READ_I;
input                   IO_READY;
input                   PSR_USER;
input                   DATA_HOLD;
input                   PTB_WR;
input                   PTB_SEL;
input                   DRAM_WR;
input                   KDET;
input                   HOLD;
input    [1:0]   CFG;
input  [127:0]   DRAM_Q;
input    [1:0]   CINVAL;
input    [1:0]   IC_SIGS;
input   [31:0]   IO_Q;
input    [1:0]   IVAR;
input   [28:4]  KOLLI_A;
input    [3:0]   MCR_FLAGS;
input   [23:0]   MMU_DIN;
input   [31:0]   VADR;
input                   INHIBIT;
input                   ENA_HK;
input                   ENDRAM;
 
output                  IO_RD;
output                  DRAM_ACC;
output                  INIT_RUN;
output                  PROT_ERROR;
output                  ACC_OK;
output                  IC_PREQ;
output                  KOLLISION;
output                  STOP_CINV;
output  [31:0]   IC_DQ;
output [31:12]  IC_VA;
output   [3:0]   ICTODC;
output reg      [28:0]   DRAM_A;
output reg      [31:0]   IO_A;
 
reg             [31:0]   VADR_R;
reg             [31:0]   CAPDAT;
reg             [31:0]   DFFE_IOR;
reg                             HOLD_ON;
reg                             DFF_HDFF1;
reg                             DFF_IRD_REG;
 
wire    [4:0]    A_CV;
wire                    ACOK;
wire    [4:0]    ACV;
wire                    AUX_DAT;
wire                    CA_HIT;
wire                    CA_SET;
wire                    CUPDATE;
wire    [23:0]   D_CV;
wire                    HIT_ALL;
wire                    INIT_CA_RUN;
wire                    IO_ACC;
wire                    KILL;
wire                    NEW_PTB;
wire                    PTB_ONE;
wire   [31:12]  RADR;
wire                    READ;
wire                    RUN_ICRD;
wire                    STOP_ICRD;
wire    [23:0]   UPCD;
wire    [23:0]   UPDATE_C;
wire    [31:0]   UPDATE_M;
wire                    USE_CA;
wire                    USER;
wire    [11:7]  V_ADR;
wire                    WE_CV;
wire                    WEMV;
wire                    WRCRAM0;
wire                    WRCRAM1;
wire                    WRSET0;
wire                    WRSET1;
wire                    WRITE;
wire    [11:7]  KILLADR;
wire                    AUX_ALT;
wire                    VIRT_A;
wire                    CI;
wire                    MMU_HIT;
wire                    LD_DRAM_A;
wire                    IO_SPACE;
wire                    LAST_MUX;
wire                    VIRTUELL;
wire                    NEW_PTB_RUN;
wire    [31:0]   SET_DAT;
wire    [31:0]   ALT_DAT;
wire    [31:0]   DAT_MV;
wire     [3:0]   RADR_MV;
wire     [3:0]   WADR_MV;
wire    [23:0]   NEWCVAL;
wire                    KILL_C,KILL_K;
wire                    RMW;
wire    [31:0]   CAP_Q;
wire   [28:12]  TAGDAT;
 
// +++++++++++++++++++ Memories ++++++++++++++++++++
 
reg        [127:0]       DATA0 [0:255];           // Data Set 0 : 4 kBytes
reg        [127:0]       RDDATA0;
reg             [31:0]   SET_DAT0;
 
reg        [127:0]       DATA1 [0:255];           // Data Set 1 : 4 kBytes
reg        [127:0]       RDDATA1;
reg             [31:0]   SET_DAT1;
 
reg             [16:0]   TAGSET_0 [0:255];        // Tag Set for Data Set 0 : 256 entries of 17 bits
reg             [16:0]   TAG0;
 
reg             [16:0]   TAGSET_1 [0:255];        // Tag Set for Data Set 1 : 256 entries of 17 bits
reg             [16:0]   TAG1;
 
wire    [23:0]   CVALID;
 
reg             [35:0]   MMU_TAGS [0:255];        // Tag Set for MMU : 256 entries of 36 bits
reg             [35:0]   MMU_Q;
 
reg             [31:0]   MMU_VALID [0:15];        // Valid bits for MMU Tag Set : 16 entries of 32 bits
reg             [31:0]   MVALID;
 
reg             [16:0]   KTAGSET_0 [0:255];       // Kollision Tag Set for Data Set 0 : 256 entries of 17 bits
reg             [16:0]   KTAG0;
 
reg             [16:0]   KTAGSET_1 [0:255];       // Kollision Tag Set for Data Set 1 : 256 entries of 17 bits
reg             [16:0]   KTAG1;
 
wire    [23:0]   KCVALID;
 
assign  READ    = READ_I & ~HOLD_ON & RUN_ICRD;
assign  WRITE   = 1'b0;
assign  RMW             = 1'b0;
 
assign  ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
 
assign  RADR    = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
 
assign  V_ADR   = STOP_ICRD ? KILLADR : VADR[11:7] ;
assign  ACV             = STOP_ICRD ? KILLADR : A_CV ;
assign  UPCD    = STOP_ICRD ? NEWCVAL : UPDATE_C ;
 
assign  IC_DQ   = LAST_MUX ? ALT_DAT : SET_DAT ;
 
assign  SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
 
assign  KILL    = KILL_C | KILL_K;
 
assign  IC_VA   = VADR_R[31:12];
 
assign  VIRT_A  = ~CINVAL[0] & VIRTUELL;
 
assign  ACC_OK  = HOLD_ON | ACOK;
 
assign  USER    = ~MCR_FLAGS[3] & PSR_USER;
 
assign  AUX_ALT = HOLD_ON | DFF_IRD_REG;
 
assign  LAST_MUX = AUX_ALT | AUX_DAT;
 
assign  INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
 
assign  LD_DRAM_A = ~DRAM_ACC | MDONE;
 
assign  ICTODC[3] = USER;
 
always @(posedge BCLK) VADR_R <= VADR;
 
always @(posedge BCLK) DFF_IRD_REG <= IO_RD;
 
always @(posedge BCLK) DFF_HDFF1 <= IO_READY;
 
always @(posedge BCLK) if (LD_DRAM_A) DRAM_A <= {RADR[28:12],VADR_R[11:2],USE_CA,CA_SET};
 
always @(posedge BCLK) if (IO_ACC) IO_A <= {RADR[31:12],VADR_R[11:0]};
 
always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
 
always @(posedge BCLK or negedge BRESET)
        if (!BRESET) HOLD_ON <= 1'b0;
                else HOLD_ON <= (DATA_HOLD & DFF_HDFF1) | (HOLD_ON & DATA_HOLD);
 
DMUX  DMUX_4TO1 (
        .DRAM_Q(DRAM_Q),
        .ADDR(VADR_R[3:2]),
        .CAP_Q(CAP_Q) );
 
always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q;
 
FILTCMP  FILT_CMP(
        .RADR({RADR[28:12],VADR_R[11:4]}),
        .DRAMSZ(DRAMSZ),
        .DRAM_A(25'd0),
        .TAGDAT(TAGDAT),
        .ADR_EQU());
 
// +++++++++++++++++++++++++  Cache Valid  +++++++++++++++++++
 
NEU_VALID       VALID_RAM(
        .BCLK(BCLK),
        .VALIN(D_CV),
        .WADR(ACV),
        .WREN(WE_CV),
        .RADR(V_ADR[11:7]),
        .VALOUT(CVALID) );
 
// +++++++++++++++++++++++++  Tag Set 0  +++++++++++++++++++++
 
always @(posedge BCLK) TAG0 <= TAGSET_0[VADR[11:4]];
 
always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= TAGDAT;
 
// +++++++++++++++++++++++++  Tag Set 1  +++++++++++++++++++++
 
always @(posedge BCLK) TAG1 <= TAGSET_1[VADR[11:4]];
 
always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= TAGDAT;
 
// +++++++++++++++++++++++++  Data Set 0  ++++++++++++++++++++
 
always @(posedge BCLK) RDDATA0 <= DATA0[VADR[11:4]];
 
always @(RDDATA0 or VADR_R)
        case (VADR_R[3:2])
          2'b00 : SET_DAT0 <= RDDATA0[31:0];
          2'b01 : SET_DAT0 <= RDDATA0[63:32];
          2'b10 : SET_DAT0 <= RDDATA0[95:64];
          2'b11 : SET_DAT0 <= RDDATA0[127:96];
        endcase
 
always @(posedge BCLK) if (WRSET0) DATA0[VADR_R[11:4]] <= DRAM_Q;
 
// +++++++++++++++++++++++++  Data Set 1  ++++++++++++++++++++
 
always @(posedge BCLK) RDDATA1 <= DATA1[VADR[11:4]];
 
always @(RDDATA1 or VADR_R)
        case (VADR_R[3:2])
          2'b00 : SET_DAT1 <= RDDATA1[31:0];
          2'b01 : SET_DAT1 <= RDDATA1[63:32];
          2'b10 : SET_DAT1 <= RDDATA1[95:64];
          2'b11 : SET_DAT1 <= RDDATA1[127:96];
        endcase
 
always @(posedge BCLK) if (WRSET1) DATA1[VADR_R[11:4]] <= DRAM_Q;
 
CA_MATCH        DCA_COMPARE(
        .INVAL_L(CINVAL[0]),
        .CI(CI),
        .MMU_HIT(MMU_HIT),
        .WRITE(WRITE),
        .KDET(1'b0),
        .ADDR({RADR[31:12],VADR_R[11:4]}),
        .CFG(CFG),
        .ENDRAM(ENDRAM),
        .CVALID(CVALID),
        .TAG0(TAG0),
        .TAG1(TAG1),
        .CA_HIT(CA_HIT),
        .CA_SET(CA_SET),
        .WB_ACC(),
        .USE_CA(USE_CA),
        .DRAMSZ(DRAMSZ),
        .IO_SPACE(IO_SPACE),
        .DC_ILO(1'b0),
        .KILL(KILL_C),
        .UPDATE(UPDATE_C));
 
DCA_CONTROL     DCA_CTRL(
        .BCLK(BCLK),
        .BRESET(BRESET),
        .CA_SET(CA_SET),
        .HIT_ALL(HIT_ALL),
        .UPDATE(UPCD),
        .VADR_R(VADR_R[11:7]),
        .DRAM_ACC(DRAM_ACC),
        .CUPDATE(CUPDATE),
        .KILL(KILL),
        .WRITE(WRITE),
        .USE_CA(DRAM_A[1]),
        .INHIBIT(INHIBIT),
        .INVAL_A(CINVAL[1]),
        .MDONE(MDONE),
        .DAT_CV(D_CV),
        .WADR_CV(A_CV),
        .WE_CV(WE_CV),
        .INIT_CA_RUN(INIT_CA_RUN),
        .WRCRAM0(WRCRAM0),
        .WRCRAM1(WRCRAM1),
        .WRSET0(WRSET0),
        .WRSET1(WRSET1));
 
ICACHE_SM       IC_SM(
        .BCLK(BCLK),
        .BRESET(BRESET),
        .IO_SPACE(IO_SPACE),
        .READ(READ),
        .MDONE(MDONE),
        .IO_READY(IO_READY),
        .MMU_HIT(MMU_HIT),
        .CA_HIT(CA_HIT),
        .USE_CA(USE_CA),
        .PTB_WR(PTB_WR),
        .PTB_SEL(PTB_SEL),
        .USER(USER),
        .PROT_ERROR(PROT_ERROR),
        .PTE_ACC(IC_SIGS[1]),
        .ACC_OK(ACOK),
        .PTB_ONE(PTB_ONE),
        .NEW_PTB(NEW_PTB),
        .AUX_DAT(AUX_DAT),
        .CUPDATE(CUPDATE),
        .IO_RD(IO_RD),
        .IO_ACC(IO_ACC),
        .DRAM_ACC(DRAM_ACC),
        .IC_PREQ(IC_PREQ),
        .HIT_ALL(HIT_ALL));
 
// +++++++++++++++++++++++++  Kollision Valid  +++++++++++++++
 
NEU_VALID       KOL_VAL(
        .BCLK(BCLK),
        .VALIN(D_CV),
        .WADR(ACV),
        .WREN(WE_CV),
        .RADR(KOLLI_A[11:7]),
        .VALOUT(KCVALID) );
 
// +++++++++++++++++++++++++  Kollision Tag Set 0  +++++++++++
 
always @(posedge BCLK) KTAG0 <= KTAGSET_0[KOLLI_A[11:4]];
 
always @(negedge BCLK) if (WRCRAM0) KTAGSET_0[VADR_R[11:4]] <= TAGDAT;
 
// +++++++++++++++++++++++++  Kollision Tag Set 1  +++++++++++
 
always @(posedge BCLK) KTAG1 <= KTAGSET_1[KOLLI_A[11:4]];
 
always @(negedge BCLK) if (WRCRAM1) KTAGSET_1[VADR_R[11:4]] <= TAGDAT;
 
KOLDETECT       KOLLOGIK(
        .DRAM_WR(DRAM_WR),
        .BCLK(BCLK),
        .READ_I(READ_I),
        .ACC_OK(ACC_OK),
        .BRESET(BRESET),
        .INVAL_A(CINVAL[1]),
        .KDET(KDET),
        .HOLD(HOLD),
        .ENA_HK(ENA_HK),
        .STOP_CINV(STOP_CINV),
        .ADDR(KOLLI_A),
        .C_VALID(KCVALID),
        .CFG(CFG),
        .CVALID(CVALID),
        .TAG0(KTAG0),
        .TAG1(KTAG1),
        .KOLLISION(KOLLISION),
        .STOP_ICRD(STOP_ICRD),
        .RUN_ICRD(RUN_ICRD),
        .KILL(KILL_K),
        .ICTODC(ICTODC[2:0]),
        .KILLADR(KILLADR),
        .NEWCVAL(NEWCVAL));
 
MMU_MATCH       MMU_COMPARE(
        .USER(USER),
        .READ(READ),
        .WRITE(WRITE),
        .RMW(RMW),
        .IVAR(IVAR),
        .MCR_FLAGS(MCR_FLAGS[2:0]),
        .MMU_VA(MMU_Q[35:20]),
        .MVALID(MVALID),
        .VADR_R(VADR_R[31:12]),
        .MMU_HIT(MMU_HIT),
        .PROT_ERROR(PROT_ERROR),
        .VIRTUELL(VIRTUELL),
        .CI(CI),
        .SEL_PTB1(),
        .UPDATE(UPDATE_M));
 
MMU_UP  MMU_CTRL(
        .NEW_PTB(NEW_PTB),
        .IVAR(IVAR[1]),
        .BRESET(BRESET),
        .PTB1(PTB_ONE),
        .BCLK(BCLK),
        .WR_MRAM(IC_SIGS[0]),
        .MVALID(MVALID),
        .UPDATE(UPDATE_M),
        .VADR(VADR[19:16]),
        .VADR_R(VADR_R[19:16]),
        .WE_MV(WEMV),
        .NEW_PTB_RUN(NEW_PTB_RUN),
        .DAT_MV(DAT_MV),
        .RADR_MV(RADR_MV),
        .WADR_MV(WADR_MV));
 
// +++++++++++++++++++++++++  MMU Valid  +++++++++++++++++++++
 
always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];
 
always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;
 
// +++++++++++++++++++++++++  MMU Tags  ++++++++++++++++++++++
 
always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];
 
always @(negedge BCLK) if (IC_SIGS[0]) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};
 
endmodule

Line No.	Rev	Author	Line
1	29	ns32kum	`// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++`
2	9	ns32kum	`//`
3			`// This file is part of the M32632 project`
4			`// http://opencores.org/project,m32632`
5			`//`
6	23	ns32kum	`// Filename: ICACHE.v`
7	29	ns32kum	`// Version: 3.0 Cache Interface reworked`
8			`// History: 2.0 50 MHz release of 14 August 2016`
9			`// 1.0 first release of 30 Mai 2015`
10			`// Date: 2 December 2018`
11	9	ns32kum	`//`
12	29	ns32kum	`// Copyright (C) 2018 Udo Moeller`
13	9	ns32kum	`//`
14			`// This source file may be used and distributed without`
15			`// restriction provided that this copyright statement is not`
16			`// removed from the file and that any derivative work contains`
17			`// the original copyright notice and the associated disclaimer.`
18			`//`
19			`// This source file is free software; you can redistribute it`
20			`// and/or modify it under the terms of the GNU Lesser General`
21			`// Public License as published by the Free Software Foundation;`
22			`// either version 2.1 of the License, or (at your option) any`
23			`// later version.`
24			`//`
25			`// This source is distributed in the hope that it will be`
26			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
27			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
28			`// PURPOSE. See the GNU Lesser General Public License for more`
29			`// details.`
30			`//`
31			`// You should have received a copy of the GNU Lesser General`
32			`// Public License along with this source; if not, download it`
33			`// from http://www.opencores.org/lgpl.shtml`
34			`//`
35	29	ns32kum	`// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++`
36	9	ns32kum	`//`
37			`// Modules contained in this file:`
38			`// ICACHE the instruction cache of M32632`
39			`//`
40	11	ns32kum	`// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++`
41	9	ns32kum
42	29	ns32kum	`module ICACHE( BCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,`
43			`KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR,`
44			`INHIBIT, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,`
45	9	ns32kum	`DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );`
46
47			`input BCLK;`
48	23	ns32kum	`input [2:0] DRAMSZ;`
49	9	ns32kum	`input MDONE;`
50			`input BRESET;`
51			`input READ_I;`
52			`input IO_READY;`
53			`input PSR_USER;`
54			`input DATA_HOLD;`
55			`input PTB_WR;`
56			`input PTB_SEL;`
57			`input DRAM_WR;`
58			`input KDET;`
59			`input HOLD;`
60			`input [1:0] CFG;`
61	29	ns32kum	`input [127:0] DRAM_Q;`
62	9	ns32kum	`input [1:0] CINVAL;`
63			`input [1:0] IC_SIGS;`
64			`input [31:0] IO_Q;`
65			`input [1:0] IVAR;`
66	29	ns32kum	`input [28:4] KOLLI_A;`
67	9	ns32kum	`input [3:0] MCR_FLAGS;`
68			`input [23:0] MMU_DIN;`
69			`input [31:0] VADR;`
70	29	ns32kum	`input INHIBIT;`
71	9	ns32kum	`input ENA_HK;`
72			`input ENDRAM;`
73
74			`output IO_RD;`
75			`output DRAM_ACC;`
76			`output INIT_RUN;`
77			`output PROT_ERROR;`
78			`output ACC_OK;`
79			`output IC_PREQ;`
80			`output KOLLISION;`
81			`output STOP_CINV;`
82			`output [31:0] IC_DQ;`
83			`output [31:12] IC_VA;`
84			`output [3:0] ICTODC;`
85	29	ns32kum	`output reg [28:0] DRAM_A;`
86	9	ns32kum	`output reg [31:0] IO_A;`
87
88			`reg [31:0] VADR_R;`
89			`reg [31:0] CAPDAT;`
90			`reg [31:0] DFFE_IOR;`
91			`reg HOLD_ON;`
92			`reg DFF_HDFF1;`
93			`reg DFF_IRD_REG;`
94
95			`wire [4:0] A_CV;`
96			`wire ACOK;`
97			`wire [4:0] ACV;`
98			`wire AUX_DAT;`
99			`wire CA_HIT;`
100			`wire CA_SET;`
101			`wire CUPDATE;`
102			`wire [23:0] D_CV;`
103			`wire HIT_ALL;`
104			`wire INIT_CA_RUN;`
105			`wire IO_ACC;`
106			`wire KILL;`
107			`wire NEW_PTB;`
108			`wire PTB_ONE;`
109			`wire [31:12] RADR;`
110			`wire READ;`
111			`wire RUN_ICRD;`
112			`wire STOP_ICRD;`
113			`wire [23:0] UPCD;`
114			`wire [23:0] UPDATE_C;`
115			`wire [31:0] UPDATE_M;`
116			`wire USE_CA;`
117			`wire USER;`
118			`wire [11:7] V_ADR;`
119			`wire WE_CV;`
120			`wire WEMV;`
121			`wire WRCRAM0;`
122			`wire WRCRAM1;`
123			`wire WRSET0;`
124			`wire WRSET1;`
125			`wire WRITE;`
126			`wire [11:7] KILLADR;`
127			`wire AUX_ALT;`
128			`wire VIRT_A;`
129			`wire CI;`
130			`wire MMU_HIT;`
131			`wire LD_DRAM_A;`
132			`wire IO_SPACE;`
133			`wire LAST_MUX;`
134			`wire VIRTUELL;`
135			`wire NEW_PTB_RUN;`
136			`wire [31:0] SET_DAT;`
137			`wire [31:0] ALT_DAT;`
138			`wire [31:0] DAT_MV;`
139			`wire [3:0] RADR_MV;`
140			`wire [3:0] WADR_MV;`
141			`wire [23:0] NEWCVAL;`
142			`wire KILL_C,KILL_K;`
143			`wire RMW;`
144	29	ns32kum	`wire [31:0] CAP_Q;`
145			`wire [28:12] TAGDAT;`
146	9	ns32kum
147			`// +++++++++++++++++++ Memories ++++++++++++++++++++`
148
149	29	ns32kum	`reg [127:0] DATA0 [0:255]; // Data Set 0 : 4 kBytes`
150			`reg [127:0] RDDATA0;`
151	9	ns32kum	`reg [31:0] SET_DAT0;`
152
153	29	ns32kum	`reg [127:0] DATA1 [0:255]; // Data Set 1 : 4 kBytes`
154			`reg [127:0] RDDATA1;`
155	9	ns32kum	`reg [31:0] SET_DAT1;`
156
157	29	ns32kum	`reg [16:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 17 bits`
158			`reg [16:0] TAG0;`
159	9	ns32kum
160	29	ns32kum	`reg [16:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 17 bits`
161			`reg [16:0] TAG1;`
162	9	ns32kum
163	23	ns32kum	`wire [23:0] CVALID;`
164	9	ns32kum
165			`reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits`
166			`reg [35:0] MMU_Q;`
167
168			`reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits`
169			`reg [31:0] MVALID;`
170
171	29	ns32kum	`reg [16:0] KTAGSET_0 [0:255]; // Kollision Tag Set for Data Set 0 : 256 entries of 17 bits`
172			`reg [16:0] KTAG0;`
173	9	ns32kum
174	29	ns32kum	`reg [16:0] KTAGSET_1 [0:255]; // Kollision Tag Set for Data Set 1 : 256 entries of 17 bits`
175			`reg [16:0] KTAG1;`
176	9	ns32kum
177	23	ns32kum	`wire [23:0] KCVALID;`
178	9	ns32kum
179			`assign READ = READ_I & ~HOLD_ON & RUN_ICRD;`
180			`assign WRITE = 1'b0;`
181			`assign RMW = 1'b0;`
182
183			`assign ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;`
184
185			`assign RADR = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;`
186
187			`assign V_ADR = STOP_ICRD ? KILLADR : VADR[11:7] ;`
188			`assign ACV = STOP_ICRD ? KILLADR : A_CV ;`
189			`assign UPCD = STOP_ICRD ? NEWCVAL : UPDATE_C ;`
190
191			`assign IC_DQ = LAST_MUX ? ALT_DAT : SET_DAT ;`
192
193			`assign SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;`
194
195			`assign KILL = KILL_C \| KILL_K;`
196
197			`assign IC_VA = VADR_R[31:12];`
198
199			`assign VIRT_A = ~CINVAL[0] & VIRTUELL;`
200
201			`assign ACC_OK = HOLD_ON \| ACOK;`
202
203			`assign USER = ~MCR_FLAGS[3] & PSR_USER;`
204
205			`assign AUX_ALT = HOLD_ON \| DFF_IRD_REG;`
206
207			`assign LAST_MUX = AUX_ALT \| AUX_DAT;`
208
209			`assign INIT_RUN = NEW_PTB_RUN \| INIT_CA_RUN;`
210
211			`assign LD_DRAM_A = ~DRAM_ACC \| MDONE;`
212
213			`assign ICTODC[3] = USER;`
214
215			`always @(posedge BCLK) VADR_R <= VADR;`
216
217			`always @(posedge BCLK) DFF_IRD_REG <= IO_RD;`
218
219			`always @(posedge BCLK) DFF_HDFF1 <= IO_READY;`
220
221	29	ns32kum	`always @(posedge BCLK) if (LD_DRAM_A) DRAM_A <= {RADR[28:12],VADR_R[11:2],USE_CA,CA_SET};`
222	9	ns32kum
223			`always @(posedge BCLK) if (IO_ACC) IO_A <= {RADR[31:12],VADR_R[11:0]};`
224
225			`always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;`
226
227			`always @(posedge BCLK or negedge BRESET)`
228			`if (!BRESET) HOLD_ON <= 1'b0;`
229			`else HOLD_ON <= (DATA_HOLD & DFF_HDFF1) \| (HOLD_ON & DATA_HOLD);`
230
231	29	ns32kum	`DMUX DMUX_4TO1 (`
232			`.DRAM_Q(DRAM_Q),`
233			`.ADDR(VADR_R[3:2]),`
234			`.CAP_Q(CAP_Q) );`
235
236			`always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q;`
237	9	ns32kum
238	29	ns32kum	`FILTCMP FILT_CMP(`
239			`.RADR({RADR[28:12],VADR_R[11:4]}),`
240			`.DRAMSZ(DRAMSZ),`
241			`.DRAM_A(25'd0),`
242			`.TAGDAT(TAGDAT),`
243			`.ADR_EQU());`
244
245	9	ns32kum	`// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++`
246
247	23	ns32kum	`NEU_VALID VALID_RAM(`
248			`.BCLK(BCLK),`
249			`.VALIN(D_CV),`
250			`.WADR(ACV),`
251			`.WREN(WE_CV),`
252			`.RADR(V_ADR[11:7]),`
253			`.VALOUT(CVALID) );`
254	9	ns32kum
255			`// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++`
256
257			`always @(posedge BCLK) TAG0 <= TAGSET_0[VADR[11:4]];`
258
259	29	ns32kum	`always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= TAGDAT;`
260	9	ns32kum
261			`// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++`
262
263			`always @(posedge BCLK) TAG1 <= TAGSET_1[VADR[11:4]];`
264
265	29	ns32kum	`always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= TAGDAT;`
266	9	ns32kum
267			`// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++`
268
269	29	ns32kum	`always @(posedge BCLK) RDDATA0 <= DATA0[VADR[11:4]];`
270	9	ns32kum
271	29	ns32kum	`always @(RDDATA0 or VADR_R)`
272			`case (VADR_R[3:2])`
273			`2'b00 : SET_DAT0 <= RDDATA0[31:0];`
274			`2'b01 : SET_DAT0 <= RDDATA0[63:32];`
275			`2'b10 : SET_DAT0 <= RDDATA0[95:64];`
276			`2'b11 : SET_DAT0 <= RDDATA0[127:96];`
277			`endcase`
278
279			`always @(posedge BCLK) if (WRSET0) DATA0[VADR_R[11:4]] <= DRAM_Q;`
280
281	9	ns32kum	`// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++`
282
283	29	ns32kum	`always @(posedge BCLK) RDDATA1 <= DATA1[VADR[11:4]];`
284	9	ns32kum
285	29	ns32kum	`always @(RDDATA1 or VADR_R)`
286			`case (VADR_R[3:2])`
287			`2'b00 : SET_DAT1 <= RDDATA1[31:0];`
288			`2'b01 : SET_DAT1 <= RDDATA1[63:32];`
289			`2'b10 : SET_DAT1 <= RDDATA1[95:64];`
290			`2'b11 : SET_DAT1 <= RDDATA1[127:96];`
291			`endcase`
292
293			`always @(posedge BCLK) if (WRSET1) DATA1[VADR_R[11:4]] <= DRAM_Q;`
294
295	9	ns32kum	`CA_MATCH DCA_COMPARE(`
296			`.INVAL_L(CINVAL[0]),`
297			`.CI(CI),`
298			`.MMU_HIT(MMU_HIT),`
299			`.WRITE(WRITE),`
300			`.KDET(1'b0),`
301	23	ns32kum	`.ADDR({RADR[31:12],VADR_R[11:4]}),`
302	9	ns32kum	`.CFG(CFG),`
303			`.ENDRAM(ENDRAM),`
304			`.CVALID(CVALID),`
305			`.TAG0(TAG0),`
306			`.TAG1(TAG1),`
307			`.CA_HIT(CA_HIT),`
308			`.CA_SET(CA_SET),`
309			`.WB_ACC(),`
310			`.USE_CA(USE_CA),`
311	23	ns32kum	`.DRAMSZ(DRAMSZ),`
312	9	ns32kum	`.IO_SPACE(IO_SPACE),`
313			`.DC_ILO(1'b0),`
314			`.KILL(KILL_C),`
315			`.UPDATE(UPDATE_C));`
316
317			`DCA_CONTROL DCA_CTRL(`
318			`.BCLK(BCLK),`
319			`.BRESET(BRESET),`
320			`.CA_SET(CA_SET),`
321			`.HIT_ALL(HIT_ALL),`
322			`.UPDATE(UPCD),`
323			`.VADR_R(VADR_R[11:7]),`
324			`.DRAM_ACC(DRAM_ACC),`
325			`.CUPDATE(CUPDATE),`
326			`.KILL(KILL),`
327			`.WRITE(WRITE),`
328	29	ns32kum	`.USE_CA(DRAM_A[1]),`
329			`.INHIBIT(INHIBIT),`
330	9	ns32kum	`.INVAL_A(CINVAL[1]),`
331	29	ns32kum	`.MDONE(MDONE),`
332	9	ns32kum	`.DAT_CV(D_CV),`
333			`.WADR_CV(A_CV),`
334			`.WE_CV(WE_CV),`
335			`.INIT_CA_RUN(INIT_CA_RUN),`
336			`.WRCRAM0(WRCRAM0),`
337			`.WRCRAM1(WRCRAM1),`
338			`.WRSET0(WRSET0),`
339			`.WRSET1(WRSET1));`
340
341			`ICACHE_SM IC_SM(`
342			`.BCLK(BCLK),`
343			`.BRESET(BRESET),`
344			`.IO_SPACE(IO_SPACE),`
345			`.READ(READ),`
346			`.MDONE(MDONE),`
347			`.IO_READY(IO_READY),`
348			`.MMU_HIT(MMU_HIT),`
349			`.CA_HIT(CA_HIT),`
350			`.USE_CA(USE_CA),`
351			`.PTB_WR(PTB_WR),`
352			`.PTB_SEL(PTB_SEL),`
353			`.USER(USER),`
354			`.PROT_ERROR(PROT_ERROR),`
355			`.PTE_ACC(IC_SIGS[1]),`
356			`.ACC_OK(ACOK),`
357			`.PTB_ONE(PTB_ONE),`
358			`.NEW_PTB(NEW_PTB),`
359			`.AUX_DAT(AUX_DAT),`
360			`.CUPDATE(CUPDATE),`
361			`.IO_RD(IO_RD),`
362			`.IO_ACC(IO_ACC),`
363			`.DRAM_ACC(DRAM_ACC),`
364			`.IC_PREQ(IC_PREQ),`
365			`.HIT_ALL(HIT_ALL));`
366
367			`// +++++++++++++++++++++++++ Kollision Valid +++++++++++++++`
368
369	23	ns32kum	`NEU_VALID KOL_VAL(`
370			`.BCLK(BCLK),`
371			`.VALIN(D_CV),`
372			`.WADR(ACV),`
373			`.WREN(WE_CV),`
374			`.RADR(KOLLI_A[11:7]),`
375			`.VALOUT(KCVALID) );`
376	9	ns32kum
377			`// +++++++++++++++++++++++++ Kollision Tag Set 0 +++++++++++`
378
379			`always @(posedge BCLK) KTAG0 <= KTAGSET_0[KOLLI_A[11:4]];`
380
381	29	ns32kum	`always @(negedge BCLK) if (WRCRAM0) KTAGSET_0[VADR_R[11:4]] <= TAGDAT;`
382	9	ns32kum
383			`// +++++++++++++++++++++++++ Kollision Tag Set 1 +++++++++++`
384
385			`always @(posedge BCLK) KTAG1 <= KTAGSET_1[KOLLI_A[11:4]];`
386
387	29	ns32kum	`always @(negedge BCLK) if (WRCRAM1) KTAGSET_1[VADR_R[11:4]] <= TAGDAT;`
388	9	ns32kum
389			`KOLDETECT KOLLOGIK(`
390			`.DRAM_WR(DRAM_WR),`
391			`.BCLK(BCLK),`
392			`.READ_I(READ_I),`
393			`.ACC_OK(ACC_OK),`
394			`.BRESET(BRESET),`
395			`.INVAL_A(CINVAL[1]),`
396			`.KDET(KDET),`
397			`.HOLD(HOLD),`
398			`.ENA_HK(ENA_HK),`
399			`.STOP_CINV(STOP_CINV),`
400			`.ADDR(KOLLI_A),`
401			`.C_VALID(KCVALID),`
402			`.CFG(CFG),`
403			`.CVALID(CVALID),`
404			`.TAG0(KTAG0),`
405			`.TAG1(KTAG1),`
406			`.KOLLISION(KOLLISION),`
407			`.STOP_ICRD(STOP_ICRD),`
408			`.RUN_ICRD(RUN_ICRD),`
409			`.KILL(KILL_K),`
410			`.ICTODC(ICTODC[2:0]),`
411			`.KILLADR(KILLADR),`
412			`.NEWCVAL(NEWCVAL));`
413
414			`MMU_MATCH MMU_COMPARE(`
415			`.USER(USER),`
416			`.READ(READ),`
417			`.WRITE(WRITE),`
418			`.RMW(RMW),`
419			`.IVAR(IVAR),`
420			`.MCR_FLAGS(MCR_FLAGS[2:0]),`
421			`.MMU_VA(MMU_Q[35:20]),`
422			`.MVALID(MVALID),`
423			`.VADR_R(VADR_R[31:12]),`
424			`.MMU_HIT(MMU_HIT),`
425			`.PROT_ERROR(PROT_ERROR),`
426			`.VIRTUELL(VIRTUELL),`
427			`.CI(CI),`
428			`.SEL_PTB1(),`
429			`.UPDATE(UPDATE_M));`
430
431			`MMU_UP MMU_CTRL(`
432			`.NEW_PTB(NEW_PTB),`
433			`.IVAR(IVAR[1]),`
434			`.BRESET(BRESET),`
435			`.PTB1(PTB_ONE),`
436			`.BCLK(BCLK),`
437			`.WR_MRAM(IC_SIGS[0]),`
438			`.MVALID(MVALID),`
439			`.UPDATE(UPDATE_M),`
440			`.VADR(VADR[19:16]),`
441			`.VADR_R(VADR_R[19:16]),`
442			`.WE_MV(WEMV),`
443			`.NEW_PTB_RUN(NEW_PTB_RUN),`
444			`.DAT_MV(DAT_MV),`
445			`.RADR_MV(RADR_MV),`
446			`.WADR_MV(WADR_MV));`
447
448			`// +++++++++++++++++++++++++ MMU Valid +++++++++++++++++++++`
449
450			`always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];`
451
452			`always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;`
453
454			`// +++++++++++++++++++++++++ MMU Tags ++++++++++++++++++++++`
455
456			`always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];`
457
458			`always @(negedge BCLK) if (IC_SIGS[0]) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};`
459
460			`endmodule`

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