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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

// This file is part of the M32632 project

// http://opencores.org/project,m32632

//

// Filename: I_PFAD.v

// Version:  1.2 bug fix

// Version:  1.1 bug fix release of 7 November 2015

// History:  1.0 first release of 30 Mai 2015

// Date:     4 February 2016

//

// Copyright (C) 2016 Udo Moeller

// 

// This source file may be used and distributed without 

// restriction provided that this copyright statement is not 

// removed from the file and that any derivative work contains 

// the original copyright notice and the associated disclaimer.

// 

// This source file is free software; you can redistribute it 

// and/or modify it under the terms of the GNU Lesser General 

// Public License as published by the Free Software Foundation;

// either version 2.1 of the License, or (at your option) any 

// later version. 

// 

// This source is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied 

// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 

// PURPOSE. See the GNU Lesser General Public License for more 

// details. 

// 

// You should have received a copy of the GNU Lesser General 

// Public License along with this source; if not, download it 

// from http://www.opencores.org/lgpl.shtml 

// 

// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      Modules contained in this file:

//      1. BITMASK      Mask Generator , was a ROM on falling edge in early days

//      2. MULFILTER    Filter for Multiplier Input Data

//      3. SIGNMUL              Signed Multiplier for Integer Multiplication

//      4. SHIFTER              Barrel Shifter for all Shift Opcodes

//      5. FFS_LOGIK    Logic for FFS opcode 

//      6. SCHALE               Enclosure for Adder/Subtractor

//      7. I_PFAD               The Integer Datapath

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      1. BITMASK      Mask Generator , was a ROM on falling edge in early days

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module BITMASK (AA, DOUT);

//      0    :   FFFFFFFF;      Masktype 1 , Zero from right

//      1    :   FFFFFFFE;

//      2    :   FFFFFFFC;

//      3    :   FFFFFFF8;

//      .    :   ...

//      32   :   00000001;      Masktype 2 , Decoder

//      33   :   00000002;

//      34   :   00000004;

//      35   :   00000008;

//      ..   :   ...

//      64   :   00000001;      Masktyte 3 , One from right

//      65   :   00000003;

//      66   :   00000007;

//      67   :   0000000F;

//      ..   :   ...

//      96   :   FFFFFFFF;      Masktype 4 , like Masktype 3 but AA-1

//      97   :   00000001;

//      98   :   00000003;

//      99   :   00000007;

//      ..   :   ...

        input           [6:0]    AA;

        output  reg     [31:0]   DOUT;

        reg             [7:0]    dec_bit;

        wire     [4:0]   code;

        wire                    high,low;

        assign code = AA[4:0] - {4'd0,&AA[6:5]};

        assign high = (AA[6:5] == 2'd0);

        assign low  =  AA[6];

        always @(code or high or low)

                case (code[2:0])

                  3'b000 : dec_bit = {{7{high}},1'b1         };

                  3'b001 : dec_bit = {{6{high}},1'b1,   low  };

                  3'b010 : dec_bit = {{5{high}},1'b1,{2{low}}};

                  3'b011 : dec_bit = {{4{high}},1'b1,{3{low}}};

                  3'b100 : dec_bit = {{3{high}},1'b1,{4{low}}};

                  3'b101 : dec_bit = {{2{high}},1'b1,{5{low}}};

                  3'b110 : dec_bit = {   high  ,1'b1,{6{low}}};

                  3'b111 : dec_bit = {          1'b1,{7{low}}};

                endcase

        always @(code or high or low or dec_bit)

                case (code[4:3])

                  2'b00 : DOUT = {{24{high}},dec_bit              };

                  2'b01 : DOUT = {{16{high}},dec_bit,{ 8{low}}};

                  2'b10 : DOUT = {{ 8{high}},dec_bit,{16{low}}};

                  2'b11 : DOUT = {           dec_bit,{24{low}}};

                endcase

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      2. MULFILTER    Filter for Multiplier Input Data

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module MULFILTER (BWD, FLOAT, SRC1, SRC2, DEST1, DEST2);

        input    [1:0]   BWD;

        input                   FLOAT;

        input   [31:0]   SRC1,SRC2;

        output  [31:0]   DEST1,DEST2;

        wire                    sign1,sign2;

        reg             [31:0]   DEST1,DEST2;

        assign sign1 = BWD[0] ? SRC1[15] : SRC1[7];

        always @(FLOAT or BWD or SRC1 or sign1)

                casex ({FLOAT,BWD,sign1})

                  4'b0_00_0 : DEST1 = {24'h000000, SRC1[7:0]};

                  4'b0_00_1 : DEST1 = {24'hFFFFFF, SRC1[7:0]};

                  4'b0_01_0 : DEST1 = {  16'h0000,SRC1[15:0]};

                  4'b0_01_1 : DEST1 = {  16'hFFFF,SRC1[15:0]};

                  4'b1_xx_x : DEST1 = {    9'h001,SRC1[22:0]};

                  default       : DEST1 = SRC1;

                endcase

        assign sign2 = BWD[0] ? SRC2[15] : SRC2[7];

        always @(FLOAT or BWD or SRC2 or sign2)

                casex ({FLOAT,BWD,sign2})

                  4'b0_00_0 : DEST2 = {24'h000000, SRC2[7:0]};

                  4'b0_00_1 : DEST2 = {24'hFFFFFF, SRC2[7:0]};

                  4'b0_01_0 : DEST2 = {  16'h0000,SRC2[15:0]};

                  4'b0_01_1 : DEST2 = {  16'hFFFF,SRC2[15:0]};

                  4'b1_xx_x : DEST2 = {    9'h001,SRC2[22:0]};

                  default       : DEST2 = SRC2;

                endcase

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      3. SIGNMUL              Signed Multiplier for Integer Multiplication

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module SIGNMUL (dataa, datab, result);

        input   signed  [31:0]   dataa,datab;

        output  signed  [63:0]   result;

        assign result = dataa * datab;

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      4. SHIFTER              Barrel Shifter for all Shift Opcodes

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module SHIFTER ( MASKE,ROT,LSH,ASH,SIZE,SH_VAL,SH_DAT,SH_OUT,MASK_SEL);

        input  [31:0] MASKE;

        input         ROT,LSH,ASH;

        input   [1:0] SIZE;

        input   [7:0] SH_VAL;

        input  [31:0] SH_DAT;

        output [31:0] SH_OUT;

        output  [4:0] MASK_SEL;

        reg  [31:0] sh_dat_in;

        wire [31:0] sh_dat_0,sh_dat_1,sh_dat_2,sh_dat_3,sh_dat_4;

        wire  [4:0] shift;

        reg                 msb;

        wire  [1:0] mask_code;

        reg  [31:0] SH_OUT;

        reg   [4:0] MASK_SEL;

        // Inputstage : prepare for ROT opcode :

        always @(ROT or SIZE or SH_DAT)

          casex ({ROT,SIZE})

                3'b100  : sh_dat_in = {SH_DAT[31:16],SH_DAT[7:0],SH_DAT[7:0]};    // Byte copy to left

                3'b101  : sh_dat_in = {SH_DAT[15:0],SH_DAT[15:0]};        // Word copy to left

                default : sh_dat_in = SH_DAT;

          endcase

        // Special case for ROT and BYTE : this way less logic

        assign shift = (ROT & (SIZE == 2'b00)) ? {2'b11,SH_VAL[2:0]} : SH_VAL[4:0];

        // Rotation logic

        assign sh_dat_0 = shift[0] ? {sh_dat_in[30:0],sh_dat_in[31]} : sh_dat_in; // Rotation of 1 bit position

        assign sh_dat_1 = shift[1] ? {sh_dat_0[29:0],sh_dat_0[31:30]} : sh_dat_0;        // 2

        assign sh_dat_2 = shift[2] ? {sh_dat_1[27:0],sh_dat_1[31:28]} : sh_dat_1;        // 4

        assign sh_dat_3 = shift[3] ? {sh_dat_2[23:0],sh_dat_2[31:24]} : sh_dat_2;        // 8

        assign sh_dat_4 = shift[4] ? {sh_dat_3[15:0],sh_dat_3[31:16]} : sh_dat_3;        // 16

        // Detection of negativ data    

        always @(SIZE or SH_DAT)

          casex (SIZE)

                2'b00   : msb = SH_DAT[7];      // Byte

                2'b01   : msb = SH_DAT[15];     // Word

                default : msb = SH_DAT[31];     // Double = 11

          endcase

        // needs mask for output data : SH_VAL[7] says negativ number and "right" shift

        assign mask_code[1] = ROT | (SH_VAL[7] &   ASH &  msb);

        assign mask_code[0] = ROT | (SH_VAL[7] & ((ASH & ~msb) | LSH));

        always @(SH_VAL or SIZE)

          casex ({SH_VAL[7],SIZE})

                3'b100  : MASK_SEL = {2'b00,SH_VAL[2:0]};        // special mask for Byte at right-shift

                3'b101  : MASK_SEL = {1'b0,SH_VAL[3:0]}; // special mask for Word at right-shift

                default : MASK_SEL = SH_VAL[4:0];

          endcase

        always @(mask_code or sh_dat_4 or MASKE)        // top bits of MASKE are "1", lower bits are "0"

          casex (mask_code)

                  2'b00 : SH_OUT = sh_dat_4 &  MASKE;   // LSH and ASH with positiv shift count

                  2'b01 : SH_OUT = sh_dat_4 & ~MASKE;   // Negativ shift count : LSH or ASH with positiv data

                  2'b10 : SH_OUT = sh_dat_4 |  MASKE;   // ASH with negativ shift count and negativ input data

                default : SH_OUT = sh_dat_4;                    // ROT

          endcase

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      5. FFS_LOGIK    Logic for FFS opcode 

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module FFS_LOGIK  (SRC1, SRC2, BWD, FLAG, DOUT);

        input   [31:0]   SRC1;

        input    [4:0]   SRC2;

        input    [1:0]   BWD;

        output  reg             FLAG;

        output   [4:0]   DOUT;

        reg              [6:0]   maske;

        reg              [7:0]   byte_1,byte_2;

        wire     [7:0]   byte_0,byte_3;

        wire    [15:0]   mdat_0;

        wire     [7:0]   mdat_1;

        wire     [3:0]   mdat_2;

        wire     [1:0]   mdat_3;

        wire     [4:0]   obits;

        always @(*)

                case (SRC2[2:0])

                  3'd0 : maske = 7'h7F;

                  3'd1 : maske = 7'h7E;

                  3'd2 : maske = 7'h7C;

                  3'd3 : maske = 7'h78;

                  3'd4 : maske = 7'h70;

                  3'd5 : maske = 7'h60;

                  3'd6 : maske = 7'h40;

                  3'd7 : maske = 7'h00;

                endcase

        assign byte_0 = (SRC2[4:3] == 2'b00) ? {SRC1[7],(SRC1[6:0] & maske)} : 8'h00;

        always @(*)

                casex (SRC2[4:3])

                  2'b00 : byte_1 = SRC1[15:8];

                  2'b01 : byte_1 = {SRC1[15],(SRC1[14:8] & maske)};

                  2'b1x : byte_1 = 8'h00;

                endcase

        always @(*)

                casex (SRC2[4:3])

                  2'b0x : byte_2 = SRC1[23:16];

                  2'b10 : byte_2 = {SRC1[23],(SRC1[22:16] & maske)};

                  2'b11 : byte_2 = 8'h00;

                endcase

        assign byte_3 = (SRC2[4:3] == 2'b11) ? {SRC1[31],(SRC1[30:24] & maske)} : SRC1[31:24];

        assign obits[4] = ({byte_1,byte_0} == 16'h0);

        assign mdat_0   = obits[4] ? {byte_3,byte_2} : {byte_1,byte_0}; // 16 Bit

        assign obits[3] = (mdat_0[7:0] == 8'h0);

        assign mdat_1   = obits[3] ? mdat_0[15:8] : mdat_0[7:0];

        assign obits[2] = (mdat_1[3:0] == 4'h0);

        assign mdat_2   = obits[2] ? mdat_1[7:4] : mdat_1[3:0];

        assign obits[1] = (mdat_2[1:0] == 2'b0);

        assign mdat_3   = obits[1] ? mdat_2[3:2] : mdat_2[1:0];

        assign obits[0] = ~mdat_3[0];

        always @(BWD or obits or mdat_3)

                casex ({BWD,obits[4:3]})

                  4'b00_x1 : FLAG = 1;  // Byte Overflow => nothing found

                  4'b00_10 : FLAG = 1;  // Byte Overflow => nothing found

                  4'b01_1x : FLAG = 1;  // Word Overflow => nothing found

                  default  : FLAG = (mdat_3 == 2'b00);

                endcase

        assign DOUT = FLAG ? 5'h0 : obits;

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      6. SCHALE               Enclosure for Adder/Subtractor

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module SCHALE (dataa, datab, cin, add_sub, bwd, result, cout, overflow);

        input   [31:0]   dataa,datab;

        input                   cin;

        input                   add_sub;        // 1 = Addition , 0 = Subtraction

        input    [1:0]   bwd;

        output  [31:0]   result;

        output                  cout,overflow;

        reg              [2:0]   seldat;

        reg                             overflow;

        wire    [32:0]   summe;

        assign summe = {1'b0,dataa} + {1'b0,(add_sub ? datab : ~datab)} + {32'd0,cin};

        always @(bwd or dataa or datab or summe)

                case (bwd)

                  2'b00   : seldat = {summe[7], dataa[7], datab[7]};

                  2'b01   : seldat = {summe[15],dataa[15],datab[15]};

                  default : seldat = {summe[31],dataa[31],datab[31]};

                endcase

        always @(seldat or add_sub)

                case (seldat[1:0])

                  2'b00 : overflow = add_sub ?  seldat[2] : 1'b0;

                  2'b01 : overflow = add_sub ? 1'b0 :  seldat[2];

                  2'b10 : overflow = add_sub ? 1'b0 : ~seldat[2];

                  2'b11 : overflow = add_sub ? ~seldat[2] : 1'b0;

                endcase

        assign cout = add_sub ? summe[32] : ~summe[32];

        assign result = summe[31:0];

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//      7. I_PFAD               The Integer Datapath

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module I_PFAD ( BCLK, BRESET, SFP_DAT, FSR, DP_OUT, SRC1, SRC2, BMASKE, ADDR, MRESULT, OPCODE, BWD, FL, SP_CMP, DP_CMP, LD_OUT,

                                WREN, WRADR, RDAA, DETOIP, BITSEL, OVF_BCD, DISP, RWVFLAG, DSR, I_OUT, PSR, BMCODE, OV_FLAG, ACB_ZERO, STRING);

        input                   BCLK,BRESET;

        input   [31:0]   SFP_DAT,FSR,DP_OUT;

        input   [31:0]   SRC1,SRC2;

        input   [31:0]   BMASKE;

        input   [31:0]   ADDR;

        input   [63:0]   MRESULT;

        input    [7:0]   OPCODE;

        input    [1:0]   BWD;

        input                   FL;

        input    [2:0]   SP_CMP;

        input    [2:0]   DP_CMP;

        input                   LD_OUT;

        input                   WREN;

        input    [5:0]   WRADR;

        input    [7:0]   RDAA;

        input   [11:0]   DETOIP;

        input    [2:0]   BITSEL;

        input    [3:0]   OVF_BCD;

        input    [4:0]   DISP;

        input                   RWVFLAG;

        input    [3:0]   DSR;

        output  [31:0]   I_OUT;

        output  [11:0]   PSR;

        output   [6:0]   BMCODE; // ROM Address for BITMASK

        output  reg             OV_FLAG;

        output                  ACB_ZERO;

        output   [4:0]   STRING;

        reg             [31:0]   I_OUT;

        reg             [31:0]   pfad_7,pfad_6,pfad_8,pfad_4a;

        wire    [31:0]   pfad_4,pfad_5,pfad_11;

        reg             [31:0]   bwd_daten1,bwd_daten2;

        wire    [31:0]   addsub_q;

        // +++++++++++++  Global Output Multiplexer  ++++++++++++++++++++++++++++

        always @(OPCODE or pfad_4 or pfad_5 or pfad_6 or pfad_7 or pfad_8 or DP_OUT or FL or SFP_DAT or FSR or pfad_11)

                casex (OPCODE[7:3])

                  5'b0100_x : I_OUT = pfad_4;

                  5'b0101_x : I_OUT = pfad_5;   // String opcodes

                  5'b0110_x : I_OUT = pfad_6;

                  5'b0111_x : I_OUT = pfad_7;

                  5'b1000_x : I_OUT = pfad_8;

                  5'b1001_0 : I_OUT = DP_OUT;   // SP_FPU has higher priority ! LFSR has no output

                  // SFSR : ROUND,TRUNC,FLOOR Integer Data : SP or DP Block

                  5'b1001_1 : I_OUT = (OPCODE[2:1] == 2'b10) ? FSR : (FL ? SFP_DAT : DP_OUT);

                  5'b1011_x : I_OUT = pfad_11;

                  5'b1101_x : I_OUT = DP_OUT;   // Coprocessor

                  default       : I_OUT = 32'hxxxx_xxxx;        // don't care

                endcase

        // ++++++++++++++ PSR Register :         I  P S U / N Z F V - L T C

        //                                                                      11 10 9 8   7 6 5 4 3 2 1 0

        reg              [3:0]   psr_high;

        reg              [7:0]   psr_low,psr_new;

        reg             [11:0]   push_psr;       // true Register

        reg             [11:0]   calc_psr;       // only verilog case

        reg              [1:0]   nl_int;

        wire                    ld_psr_l,ld_psr_h,up_psr;

        wire                    cmp_op,bit_op,ari_op,neg_op,ffs_op,str_op,chk_op,abs_op,rwv_op;

        wire     [1:0]   fp_nz;

        wire                    f_flag,z_flag;

        wire     [1:0]   nl_flags;

        wire                    over_flow,cy_out;

        wire                    ffs_flag;       // FLAG result of FFS

        wire                    chk_flag;       // FLAG result of CHECK

        wire                    save_psr,pop_psr;

        wire     [4:0]   selbits;

        // Bits from DETOIP;

        wire                    cmps_op,ph_match,until,kill_opt,inss_op,exin_cmd,extract,bit_reg,kurz_st,dw_info,acb_reg,t2p;

        wire                    bcd_op,bcd_carry;

        assign cmps_op  = DETOIP[11];   // for CMPS

        assign ph_match = DETOIP[10];   // MATCH phase

        assign until    = DETOIP[9];    // UNITL Flag for String

        assign kill_opt = DETOIP[8];    // optimized execution of MOVS/MOVM

        assign inss_op  = DETOIP[7];    // 1=INSS

        assign exin_cmd = DETOIP[6];    // for EXT/INS

        assign extract  = DETOIP[5] & exin_cmd; // 1=EXT

        assign bit_reg  = DETOIP[4];    // for Bit opcodes

        assign kurz_st  = DETOIP[3];    // for MOVM/CMPM

        assign dw_info  = DETOIP[2];    // at ADJSPi is SP=SRC2 always 32 Bit

        assign acb_reg  = DETOIP[1];    // suppresses Carry-Set at ACB

        assign t2p          = DETOIP[0]; // Pulse to Load Trace-Bit to Pending-Trace-Bit

        assign bcd_op    = OVF_BCD[1];  // ADDPi,SUBPi - from DP_FPU

        assign bcd_carry = OVF_BCD[0];

        assign ld_psr_l = ((WRADR == 6'h1D) | (WRADR == 6'h10)) & WREN; // Register PSR & UPSR

        assign ld_psr_h =  (WRADR == 6'h1D) & (BWD != 2'b00) & WREN;    // Register PSR

        // LD_OUT[1] is coming out of DECODER for this purpose

        assign up_psr = bcd_op | ((cmp_op | bit_op | ari_op | neg_op | ffs_op | chk_op) & LD_OUT);

        assign cmp_op = (OPCODE == 8'h41) | ((OPCODE == 8'hB2) & (FL ? ~SP_CMP[2] : ~DP_CMP[2]));       // CMPi or (CMPf & ~NAN)

        assign bit_op =   ((OPCODE[7:4] == 4'h6) & ((~OPCODE[3] & OPCODE[1]) | OPCODE[3:0] == 4'hE))     // the last term is for IBIT

                                        | (OPCODE == 8'h4D) | str_op | rwv_op;  // TBIT or CMPS or RDVAL/WRVAL

        assign ari_op = (OPCODE[7:4] == 4'h4) & (OPCODE[1:0] == 2'b0) & ~dw_info;        // ADDi,ADDCi,SUBi,SUBCi - special case ADJSPi no flags

        assign neg_op = (OPCODE[7:4] == 4'h6) & (OPCODE[3] & (OPCODE[1:0] == 2'b0));     // ABSi,NEGi  

        assign ffs_op = (OPCODE          == 8'h85);     // FFS

        assign chk_op = (OPCODE          == 8'h83);     // CHECK

        assign str_op = (OPCODE[7:4] == 4'h5) & (OPCODE[3:2] == 2'b0) & ~kurz_st;       // String-"S" opcodes : F-Flag to 0, at start always

        assign abs_op = (OPCODE          == 8'h6C);     // ABSi : Carry is not affected !

        assign rwv_op = (OPCODE[7:4] == 4'hE) & (OPCODE[3:1] == 3'b0);  // RDVAL + WRVAL

        always @(bwd_daten1 or bwd_daten2 or addsub_q)  // SRC1 > SRC2 ?

                case ({bwd_daten2[31],bwd_daten1[31]})

                  2'b00 : nl_int = {addsub_q[31],addsub_q[31]}; // MSB = N , LSB = L

                  2'b01 : nl_int = {   1'b0     ,    1'b1    };

                  2'b10 : nl_int = {   1'b1     ,    1'b0    };

                  2'b11 : nl_int = {addsub_q[31],addsub_q[31]};

                endcase

        assign ACB_ZERO = (addsub_q == 32'h0);  // is used for ACBi opcode too

        assign f_flag = str_op ? 1'b0 : (rwv_op ? RWVFLAG : (bit_op ? SRC2[selbits] : (acb_reg ? PSR[5] : over_flow)));

        assign fp_nz  = FL ? SP_CMP[1:0] : DP_CMP[1:0];

        assign z_flag =   OPCODE[1] ?  fp_nz[0] : ACB_ZERO;

        assign nl_flags = OPCODE[1] ? {fp_nz[1],1'b0} : nl_int;

        always @(*)     // Bits : N Z F V - L T C

                casex ({cmp_op,bcd_op,bit_op,(ffs_op | chk_op)})

                  4'b0000 : psr_new = {PSR[7:6],          f_flag,PSR[4:1],((acb_reg | abs_op) ? PSR[0] : cy_out)};       // arithmetic Op : CY and F

                  4'b0001 : psr_new = {PSR[7:6],(ffs_op ? ffs_flag : chk_flag),PSR[4:0]};                // FFS or CHECK

                  4'b001x : psr_new = (cmps_op & str_op) ?

                                                          {2'b01,             f_flag,PSR[4:3],1'b0,PSR[1:0]}             // Init CMPS

                                                        : {PSR[7:6],          f_flag,PSR[4:0]};                                          // Bit opcode

                  4'b01xx : psr_new = {PSR[7:6],          1'b0,  PSR[4:1],bcd_carry};                   // BCD opcode