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[/] [m32632/] [trunk/] [rtl/] [REGISTERS.v] - Blame information for rev 11

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1 9 ns32kum
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2
//
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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//
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// Filename: REGISTERS.v
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// Version:  1.0
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// Date:     30 May 2015
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//
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// Copyright (C) 2015 Udo Moeller
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// 
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// This source file may be used and distributed without 
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// restriction provided that this copyright statement is not 
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// removed from the file and that any derivative work contains 
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// the original copyright notice and the associated disclaimer.
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// 
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// This source file is free software; you can redistribute it 
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// and/or modify it under the terms of the GNU Lesser General 
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any 
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// later version. 
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// 
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// This source is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied 
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
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// PURPOSE. See the GNU Lesser General Public License for more 
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// details. 
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// 
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// You should have received a copy of the GNU Lesser General 
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// Public License along with this source; if not, download it 
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// from http://www.opencores.org/lgpl.shtml 
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// 
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//      Modules contained in this file:
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//      1. CONFIG_REGS  Configuration and Debug Registers
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//      2. FP_STAT_REG  Floating Point Status Register
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//      3. REGISTER             General Purpose Registers
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//
40 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
41 9 ns32kum
 
42 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//      1. CONFIG_REGS  Configuration and Debug Registers
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//
46 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ,
48 9 ns32kum
                                         CFG, MCR, PTB_WR, PTB_SEL, IVAR, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
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50
        input                   BCLK,BRESET;
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        input                   WREN,LD_OUT;
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        input    [7:0]   OPCODE;
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        input   [31:0]   SRC1;
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        input    [5:0]   WRADR;
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        input   [31:0]   PC_ARCHI;
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        input                   USER;
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        input                   PCMATCH;
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        input                   DBG_HIT;
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        input                   READ;
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61
        output  [12:0]   CFG;
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        output   [3:0]   MCR;
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        output                  PTB_WR;
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        output                  PTB_SEL;
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        output   [1:0]   IVAR;
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        output   [3:0]   CINV;
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        output                  Y_INIT;
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        output   [3:0]   DSR;
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        output   [2:0]   DBG_TRAPS;
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        output  [40:2]  DBG_IN;
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72
        reg              [3:0]   MCR;
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        reg             [12:0]   CFG;
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        reg              [1:0]   old_cfg;
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        reg                             PTB_WR,PTB_SEL;
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        reg                             ivarreg;
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        reg              [1:0]   ci_all,ci_line;
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        reg                             check_y;
79
 
80
        wire                    ld_cfg,ld_mcr,do_cinv;
81
        wire                    init_ic,init_dc;
82
        wire                    op_ok;
83
 
84
        assign op_ok = (OPCODE == 8'h6A);       // Special Opcode - for security reason
85
 
86
        assign ld_cfg  = op_ok & (WRADR == 6'h1C)          & WREN;
87
        assign ld_mcr  = op_ok & (WRADR == 6'd9)           & WREN;
88
        assign do_cinv = op_ok & (WRADR[5:4] == 2'b11) & WREN;
89
 
90
        // PF is not implemented
91
        always @(posedge BCLK or negedge BRESET)
92
                if (!BRESET) CFG <= 13'h0;
93
                        else if (ld_cfg) CFG <= SRC1[12:0];
94
 
95
        always @(posedge BCLK or negedge BRESET)
96
                if (!BRESET) MCR <= 4'h0;
97
                        else if (ld_mcr) MCR <= SRC1[3:0];
98
 
99
        always @(posedge BCLK) ivarreg <= op_ok & (WRADR[5:1] == 5'd7) & WREN;  // IVAR0/1 = Reg. Nr. 14/15
100
        assign IVAR = {ivarreg,PTB_SEL};
101
 
102
        always @(posedge BCLK) PTB_WR  <= op_ok & (WRADR[5:1] == 5'd6) & WREN;  // PTB0/1 = Reg. Nr. 12/13
103
        always @(posedge BCLK) PTB_SEL <= WRADR[0];
104
 
105
        // The Cache content will be invalid if the Enable-Bit is set to 0
106
        always @(posedge BCLK) old_cfg <= {CFG[11],CFG[9]};
107
 
108 11 ns32kum
        // Cache Invalidate : the Flags are coming out of the Short-field which is otherwise used for Register selection
109 9 ns32kum
        always @(posedge BCLK) ci_all  <= do_cinv &  WRADR[2] ? WRADR[1:0] : 2'b0;       // clear all
110
        always @(posedge BCLK) ci_line <= do_cinv & ~WRADR[2] ? WRADR[1:0] : 2'b0;       // clear cache line
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112
        assign init_ic = old_cfg[1] & (~CFG[11] | ci_all[1]);
113
        assign init_dc = old_cfg[0] & (~CFG[9]  | ci_all[0]);
114
 
115
        assign CINV = {init_ic,ci_line[1],init_dc,ci_line[0]};
116
 
117
        // Y_INIT is neccessary if nothing has changed and therefore no DC/IC_INIT is generated
118
        always @(posedge BCLK) check_y <= ld_cfg | do_cinv;
119
        assign Y_INIT = check_y & ~init_ic & ~init_dc;  // goes to register "old_init"
120
 
121
        // +++++++++++++  DEBUG Unit  +++++++++++++++
122
 
123
        reg              [3:0]   DSR;
124
        reg             [12:0]   dcr;
125
        reg             [31:0]   bpc;
126
        reg             [31:2]  car;
127
 
128
        wire                    op_dbg,ld_dcr,ld_bpc,ld_dsr,ld_car;
129
        wire                    enable;
130
 
131
        assign op_dbg = (OPCODE == 8'h76);
132
 
133
        assign ld_dcr = op_dbg & (WRADR == 6'h11) & WREN;
134
        assign ld_bpc = op_dbg & (WRADR == 6'h12) & WREN;
135
        assign ld_dsr = op_dbg & (WRADR == 6'h13) & WREN;
136
        assign ld_car = op_dbg & (WRADR == 6'h14) & WREN;
137
 
138
        assign enable = dcr[12] & (USER ? dcr[10] : dcr[11]);   // DEN & (USER ? UD : SD)
139
 
140
        always @(posedge BCLK or negedge BRESET)
141
                if (!BRESET) dcr <= 13'd0;
142
                        else if (ld_dcr) dcr <= {SRC1[23:19],SRC1[7:0]};
143
 
144
        always @(posedge BCLK) if (ld_bpc) bpc <= SRC1;
145
        always @(posedge BCLK) if (ld_car) car <= SRC1[31:2];
146
 
147
        //                                      DEN               SD        DEN       UD       CAE      CRD      CAE      CWR    VNP/CBE  CAR
148 11 ns32kum
        assign DBG_IN = {(dcr[12] & dcr[11]),(dcr[12] & dcr[10]),(dcr[7] & dcr[6]),(dcr[7] & dcr[5]),dcr[4:0],car};
149 9 ns32kum
 
150
        always @(posedge BCLK or negedge BRESET)
151
                if (!BRESET) DSR <= 4'd0;
152
                  else
153
                        if (ld_dsr) DSR <= SRC1[31:28];
154
                          else
155
                                begin
156
                                  DSR[3] <= DBG_HIT ? READ : DSR[3];
157
                                  DSR[2] <= DSR[2] | PCMATCH;
158
                                  DSR[1] <= DSR[1];
159
                                  DSR[0] <= DSR[0] | DBG_HIT;
160
                                end
161
 
162
        assign DBG_TRAPS[0] = enable & dcr[9] & (PC_ARCHI == bpc);       // dcr[9]=PCE
163
        assign DBG_TRAPS[1] = DBG_HIT;  // Compare Adress Hit
164
        assign DBG_TRAPS[2] = dcr[8];   // TR, Trap enable
165
 
166
endmodule
167
 
168 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
170
//      2. FP_STAT_REG  Floating Point Status Register
171
//
172 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module FP_STAT_REG ( BCLK, BRESET, LFSR, UP_SP, UP_DP, TT_SP, TT_DP, WREN, WRADR, DIN, FSR, TWREN, FPU_TRAP, SAVE_PC);
174 9 ns32kum
 
175
        input                   BCLK;
176
        input                   BRESET;
177
        input                   LFSR;   // Load by LFSR opcode
178
        input                   UP_SP,UP_DP;    // update if calculation operation
179
        input    [4:0]   TT_SP,TT_DP;
180
        input                   WREN;   // for RMB and LFSR
181
        input    [5:4]  WRADR;
182
        input   [16:0]   DIN;    // Data for LFSR opcode
183
 
184
        output  [31:0]   FSR;
185
        output                  TWREN;
186
        output  reg             FPU_TRAP;
187
        output                  SAVE_PC;
188
 
189
        reg              [4:3]  trap_d;
190
        reg                             update_d;
191
        reg                             set_rm_d;
192
        reg             [10:0]   set_bits;
193
        reg              [4:0]   flags;
194
        reg                             rm_bit;
195
 
196
        wire                    load_fsr;
197
        wire                    update,update_i;
198
        wire     [4:0]   trap;
199
        wire                    uflag,iflag,rmflag;
200
 
201
        assign load_fsr = LFSR & WREN;
202
 
203
        assign trap = UP_SP ? TT_SP : TT_DP;
204
 
205
        // This signal suppresses write into registers if FPU Trap, timing critical signal !
206
        assign TWREN = ~((UP_SP & (TT_SP[2:0] != 3'b0)) | (UP_DP & (TT_DP[2:0] != 3'b0)));
207
 
208
        always @(posedge BCLK or negedge BRESET)
209
                if (!BRESET) FPU_TRAP <= 1'b0;
210
                  else FPU_TRAP <= ~FPU_TRAP & ~TWREN;  // one pulse of one cycle informs the Opcode Decoder
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212
        assign update_i = (UP_SP | UP_DP) & ~FPU_TRAP;  // unfortunately one FPU opcode may follow !
213
        always @(posedge BCLK) update_d <= update_i;
214
        always @(posedge BCLK) trap_d   <= trap[4:3];
215
        always @(posedge BCLK) set_rm_d <= WREN & (WRADR == 2'b10);
216
        assign update = update_d & ~FPU_TRAP;
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218
        // The Flags are set and stay "1" 
219
        assign iflag  = (update & trap_d[4]) | flags[4];        // Inexact Result
220
        assign uflag  = (update & trap_d[3]) | flags[3];        // Underflow
221
        assign rmflag = (set_rm_d & ~FPU_TRAP) | rm_bit;        // Register Modify
222
 
223
        always @(posedge BCLK or negedge BRESET)
224
                if (!BRESET) flags[4:3] <= 2'b0;        // Inexact = Bit6, Underflow = Bit4
225
                  else
226
                  begin
227
                        if (load_fsr) flags[4:3] <= {DIN[6],DIN[4]};
228
                          else
229
                                if (update) flags[4:3] <= {iflag,uflag};
230
                  end
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232
        always @(posedge BCLK or negedge BRESET)
233
                if (!BRESET) flags[2:0] <= 3'b0; // TT Field = Bit2-0
234
                  else
235
                  begin
236
                        if (load_fsr) flags[2:0] <= DIN[2:0];
237
                          else
238
                                if (update_i) flags[2:0] <= trap[2:0];
239
                  end
240
 
241
        always @(posedge BCLK or negedge BRESET)
242
                if (!BRESET) rm_bit <= 1'b0;    // Register Modify Bit
243
                  else
244
                  begin
245
                        if (load_fsr) rm_bit <= DIN[16];
246
                          else
247
                                if (set_rm_d & ~FPU_TRAP) rm_bit <= 1'b1;       // in case of TRAP there is no writing to Register
248
                  end
249
 
250
        always @(posedge BCLK or negedge BRESET)
251
                if (!BRESET) set_bits <= 11'b0; // all other Bits
252
                  else
253
                        if (load_fsr) set_bits <= {DIN[15:7],DIN[5],DIN[3]};
254
 
255
        assign FSR = {15'h0,rmflag,set_bits[10:2],iflag,set_bits[1],uflag,set_bits[0],flags[2:0]};
256
 
257
        assign SAVE_PC = (UP_SP | UP_DP) & ~FPU_TRAP;   // Store the correct PC for FPU Trap
258
 
259
endmodule
260
 
261 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
262 9 ns32kum
//
263
//      3. REGISTER             General Purpose Registers
264
//
265 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
266 9 ns32kum
module REGISTER( BCLK, ENWR, DOWR, BYDIN, DIN, RADR, WADR, WMASKE, DOUT, SELI );
267
 
268
input                   BCLK;
269
input                   DOWR,ENWR;
270
input   [31:0]   BYDIN,DIN;
271
input    [7:0]   RADR;
272
input    [5:0]   WADR;
273
input    [1:0]   WMASKE;
274
 
275
output  [31:0]   DOUT;
276
output reg              SELI;
277
 
278
reg              [2:0]   MX;
279
 
280
wire     [3:0]   BE;
281
wire                    eq_rw;
282
 
283
// +++++++++++++++++++ Memories ++++++++++++++++++++
284
 
285
reg              [7:0]   REGFILE_D [0:63];
286
reg              [7:0]   REGFILE_C [0:63];
287
reg              [7:0]   REGFILE_B [0:63];
288
reg              [7:0]   REGFILE_A [0:63];
289
reg             [31:0]   RF;
290
 
291
assign  BE = {WMASKE[1],WMASKE[1],(WMASKE[1] | WMASKE[0]),1'b1};
292
 
293
assign  eq_rw = ENWR & (RADR[5:0] == WADR);
294
 
295
always @(posedge BCLK) if (RADR[7]) MX[2:0] <= BE[2:0] & {{3{eq_rw}}};
296
 
297
always @(posedge BCLK) if (RADR[7]) SELI <= RADR[6];
298
 
299
assign DOUT[31:16] = MX[2] ? BYDIN[31:16] : RF[31:16];
300
assign DOUT[15:8]  = MX[1] ? BYDIN[15:8]  : RF[15:8];
301
assign DOUT[7:0]   = MX[0] ? BYDIN[7:0]   : RF[7:0];
302
 
303
// ++++++++++++++++ Register File 64 * 32 Bits ++++++++++++
304
 
305
always @(posedge BCLK)
306
        if (RADR[7])
307
                begin
308
                        RF[31:24] <= REGFILE_D[RADR[5:0]];
309
                        RF[23:16] <= REGFILE_C[RADR[5:0]];
310
                        RF[15:8]  <= REGFILE_B[RADR[5:0]];
311
                        RF[7:0]   <= REGFILE_A[RADR[5:0]];
312
                end
313
 
314
always @(posedge BCLK)
315
        if (DOWR)
316
                begin
317
                        if (BE[3]) REGFILE_D[WADR] <= DIN[31:24];
318
                        if (BE[2]) REGFILE_C[WADR] <= DIN[23:16];
319
                        if (BE[1]) REGFILE_B[WADR] <= DIN[15:8];
320
                        if (BE[0]) REGFILE_A[WADR] <= DIN[7:0];
321
                end
322
 
323
endmodule
324
 

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