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[/] [m32632/] [trunk/] [rtl/] [REGISTERS.v] - Blame information for rev 29

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1 29 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 9 ns32kum
//
3
// This file is part of the M32632 project
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// http://opencores.org/project,m32632
5
//
6 23 ns32kum
//      Filename:       REGISTERS.v
7 29 ns32kum
//      Version:        3.0
8 23 ns32kum
//      History:        1.0 first release of 30 Mai 2015
9 29 ns32kum
//      Date:           2 December 2018
10 9 ns32kum
//
11 29 ns32kum
// Copyright (C) 2018 Udo Moeller
12 9 ns32kum
// 
13
// This source file may be used and distributed without 
14
// restriction provided that this copyright statement is not 
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// removed from the file and that any derivative work contains 
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// the original copyright notice and the associated disclaimer.
17
// 
18
// This source file is free software; you can redistribute it 
19
// and/or modify it under the terms of the GNU Lesser General 
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any 
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// later version. 
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// 
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// This source is distributed in the hope that it will be 
25
// useful, but WITHOUT ANY WARRANTY; without even the implied 
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
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// PURPOSE. See the GNU Lesser General Public License for more 
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// details. 
29
// 
30
// You should have received a copy of the GNU Lesser General 
31
// Public License along with this source; if not, download it 
32
// from http://www.opencores.org/lgpl.shtml 
33
// 
34 29 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
35 9 ns32kum
//
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//      Modules contained in this file:
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//      1. CONFIG_REGS  Configuration and Debug Registers
38
//      2. FP_STAT_REG  Floating Point Status Register
39
//      3. REGISTER             General Purpose Registers
40
//
41 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
42 9 ns32kum
 
43 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
44 9 ns32kum
//
45
//      1. CONFIG_REGS  Configuration and Debug Registers
46
//
47 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
48
module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ,
49 9 ns32kum
                                         CFG, MCR, PTB_WR, PTB_SEL, IVAR, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
50
 
51
        input                   BCLK,BRESET;
52
        input                   WREN,LD_OUT;
53
        input    [7:0]   OPCODE;
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        input   [31:0]   SRC1;
55
        input    [5:0]   WRADR;
56
        input   [31:0]   PC_ARCHI;
57
        input                   USER;
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        input                   PCMATCH;
59
        input                   DBG_HIT;
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        input                   READ;
61
 
62
        output  [12:0]   CFG;
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        output   [3:0]   MCR;
64
        output                  PTB_WR;
65
        output                  PTB_SEL;
66
        output   [1:0]   IVAR;
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        output   [3:0]   CINV;
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        output                  Y_INIT;
69
        output   [3:0]   DSR;
70
        output   [2:0]   DBG_TRAPS;
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        output  [40:2]  DBG_IN;
72
 
73
        reg              [3:0]   MCR;
74
        reg             [12:0]   CFG;
75
        reg              [1:0]   old_cfg;
76
        reg                             PTB_WR,PTB_SEL;
77
        reg                             ivarreg;
78
        reg              [1:0]   ci_all,ci_line;
79
        reg                             check_y;
80
 
81
        wire                    ld_cfg,ld_mcr,do_cinv;
82
        wire                    init_ic,init_dc;
83
        wire                    op_ok;
84
 
85
        assign op_ok = (OPCODE == 8'h6A);       // Special Opcode - for security reason
86
 
87
        assign ld_cfg  = op_ok & (WRADR == 6'h1C)          & WREN;
88
        assign ld_mcr  = op_ok & (WRADR == 6'd9)           & WREN;
89
        assign do_cinv = op_ok & (WRADR[5:4] == 2'b11) & WREN;
90
 
91
        // PF is not implemented
92
        always @(posedge BCLK or negedge BRESET)
93
                if (!BRESET) CFG <= 13'h0;
94
                        else if (ld_cfg) CFG <= SRC1[12:0];
95
 
96
        always @(posedge BCLK or negedge BRESET)
97
                if (!BRESET) MCR <= 4'h0;
98
                        else if (ld_mcr) MCR <= SRC1[3:0];
99
 
100
        always @(posedge BCLK) ivarreg <= op_ok & (WRADR[5:1] == 5'd7) & WREN;  // IVAR0/1 = Reg. Nr. 14/15
101
        assign IVAR = {ivarreg,PTB_SEL};
102
 
103
        always @(posedge BCLK) PTB_WR  <= op_ok & (WRADR[5:1] == 5'd6) & WREN;  // PTB0/1 = Reg. Nr. 12/13
104
        always @(posedge BCLK) PTB_SEL <= WRADR[0];
105
 
106
        // The Cache content will be invalid if the Enable-Bit is set to 0
107
        always @(posedge BCLK) old_cfg <= {CFG[11],CFG[9]};
108
 
109 11 ns32kum
        // Cache Invalidate : the Flags are coming out of the Short-field which is otherwise used for Register selection
110 9 ns32kum
        always @(posedge BCLK) ci_all  <= do_cinv &  WRADR[2] ? WRADR[1:0] : 2'b0;       // clear all
111
        always @(posedge BCLK) ci_line <= do_cinv & ~WRADR[2] ? WRADR[1:0] : 2'b0;       // clear cache line
112
 
113
        assign init_ic = old_cfg[1] & (~CFG[11] | ci_all[1]);
114
        assign init_dc = old_cfg[0] & (~CFG[9]  | ci_all[0]);
115
 
116
        assign CINV = {init_ic,ci_line[1],init_dc,ci_line[0]};
117
 
118
        // Y_INIT is neccessary if nothing has changed and therefore no DC/IC_INIT is generated
119
        always @(posedge BCLK) check_y <= ld_cfg | do_cinv;
120
        assign Y_INIT = check_y & ~init_ic & ~init_dc;  // goes to register "old_init"
121
 
122
        // +++++++++++++  DEBUG Unit  +++++++++++++++
123
 
124
        reg              [3:0]   DSR;
125
        reg             [12:0]   dcr;
126
        reg             [31:0]   bpc;
127
        reg             [31:2]  car;
128
 
129
        wire                    op_dbg,ld_dcr,ld_bpc,ld_dsr,ld_car;
130
        wire                    enable;
131
 
132
        assign op_dbg = (OPCODE == 8'h76);
133
 
134
        assign ld_dcr = op_dbg & (WRADR == 6'h11) & WREN;
135
        assign ld_bpc = op_dbg & (WRADR == 6'h12) & WREN;
136
        assign ld_dsr = op_dbg & (WRADR == 6'h13) & WREN;
137
        assign ld_car = op_dbg & (WRADR == 6'h14) & WREN;
138
 
139
        assign enable = dcr[12] & (USER ? dcr[10] : dcr[11]);   // DEN & (USER ? UD : SD)
140
 
141
        always @(posedge BCLK or negedge BRESET)
142
                if (!BRESET) dcr <= 13'd0;
143
                        else if (ld_dcr) dcr <= {SRC1[23:19],SRC1[7:0]};
144
 
145
        always @(posedge BCLK) if (ld_bpc) bpc <= SRC1;
146
        always @(posedge BCLK) if (ld_car) car <= SRC1[31:2];
147
 
148
        //                                      DEN               SD        DEN       UD       CAE      CRD      CAE      CWR    VNP/CBE  CAR
149 11 ns32kum
        assign DBG_IN = {(dcr[12] & dcr[11]),(dcr[12] & dcr[10]),(dcr[7] & dcr[6]),(dcr[7] & dcr[5]),dcr[4:0],car};
150 9 ns32kum
 
151
        always @(posedge BCLK or negedge BRESET)
152
                if (!BRESET) DSR <= 4'd0;
153
                  else
154
                        if (ld_dsr) DSR <= SRC1[31:28];
155
                          else
156
                                begin
157
                                  DSR[3] <= DBG_HIT ? READ : DSR[3];
158
                                  DSR[2] <= DSR[2] | PCMATCH;
159
                                  DSR[1] <= DSR[1];
160
                                  DSR[0] <= DSR[0] | DBG_HIT;
161
                                end
162
 
163
        assign DBG_TRAPS[0] = enable & dcr[9] & (PC_ARCHI == bpc);       // dcr[9]=PCE
164
        assign DBG_TRAPS[1] = DBG_HIT;  // Compare Adress Hit
165
        assign DBG_TRAPS[2] = dcr[8];   // TR, Trap enable
166
 
167
endmodule
168
 
169 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
170 9 ns32kum
//
171
//      2. FP_STAT_REG  Floating Point Status Register
172
//
173 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
174
module FP_STAT_REG ( BCLK, BRESET, LFSR, UP_SP, UP_DP, TT_SP, TT_DP, WREN, WRADR, DIN, FSR, TWREN, FPU_TRAP, SAVE_PC);
175 9 ns32kum
 
176
        input                   BCLK;
177
        input                   BRESET;
178
        input                   LFSR;   // Load by LFSR opcode
179
        input                   UP_SP,UP_DP;    // update if calculation operation
180
        input    [4:0]   TT_SP,TT_DP;
181
        input                   WREN;   // for RMB and LFSR
182
        input    [5:4]  WRADR;
183
        input   [16:0]   DIN;    // Data for LFSR opcode
184
 
185
        output  [31:0]   FSR;
186
        output                  TWREN;
187
        output  reg             FPU_TRAP;
188
        output                  SAVE_PC;
189
 
190
        reg              [4:3]  trap_d;
191
        reg                             update_d;
192
        reg                             set_rm_d;
193
        reg             [10:0]   set_bits;
194
        reg              [4:0]   flags;
195
        reg                             rm_bit;
196
 
197
        wire                    load_fsr;
198
        wire                    update,update_i;
199
        wire     [4:0]   trap;
200
        wire                    uflag,iflag,rmflag;
201
 
202
        assign load_fsr = LFSR & WREN;
203
 
204
        assign trap = UP_SP ? TT_SP : TT_DP;
205
 
206
        // This signal suppresses write into registers if FPU Trap, timing critical signal !
207
        assign TWREN = ~((UP_SP & (TT_SP[2:0] != 3'b0)) | (UP_DP & (TT_DP[2:0] != 3'b0)));
208
 
209
        always @(posedge BCLK or negedge BRESET)
210
                if (!BRESET) FPU_TRAP <= 1'b0;
211
                  else FPU_TRAP <= ~FPU_TRAP & ~TWREN;  // one pulse of one cycle informs the Opcode Decoder
212
 
213
        assign update_i = (UP_SP | UP_DP) & ~FPU_TRAP;  // unfortunately one FPU opcode may follow !
214
        always @(posedge BCLK) update_d <= update_i;
215
        always @(posedge BCLK) trap_d   <= trap[4:3];
216
        always @(posedge BCLK) set_rm_d <= WREN & (WRADR == 2'b10);
217
        assign update = update_d & ~FPU_TRAP;
218
 
219
        // The Flags are set and stay "1" 
220
        assign iflag  = (update & trap_d[4]) | flags[4];        // Inexact Result
221
        assign uflag  = (update & trap_d[3]) | flags[3];        // Underflow
222
        assign rmflag = (set_rm_d & ~FPU_TRAP) | rm_bit;        // Register Modify
223
 
224
        always @(posedge BCLK or negedge BRESET)
225
                if (!BRESET) flags[4:3] <= 2'b0;        // Inexact = Bit6, Underflow = Bit4
226
                  else
227
                  begin
228
                        if (load_fsr) flags[4:3] <= {DIN[6],DIN[4]};
229
                          else
230
                                if (update) flags[4:3] <= {iflag,uflag};
231
                  end
232
 
233
        always @(posedge BCLK or negedge BRESET)
234
                if (!BRESET) flags[2:0] <= 3'b0; // TT Field = Bit2-0
235
                  else
236
                  begin
237
                        if (load_fsr) flags[2:0] <= DIN[2:0];
238
                          else
239
                                if (update_i) flags[2:0] <= trap[2:0];
240
                  end
241
 
242
        always @(posedge BCLK or negedge BRESET)
243
                if (!BRESET) rm_bit <= 1'b0;    // Register Modify Bit
244
                  else
245
                  begin
246
                        if (load_fsr) rm_bit <= DIN[16];
247
                          else
248
                                if (set_rm_d & ~FPU_TRAP) rm_bit <= 1'b1;       // in case of TRAP there is no writing to Register
249
                  end
250
 
251
        always @(posedge BCLK or negedge BRESET)
252
                if (!BRESET) set_bits <= 11'b0; // all other Bits
253
                  else
254
                        if (load_fsr) set_bits <= {DIN[15:7],DIN[5],DIN[3]};
255
 
256
        assign FSR = {15'h0,rmflag,set_bits[10:2],iflag,set_bits[1],uflag,set_bits[0],flags[2:0]};
257
 
258
        assign SAVE_PC = (UP_SP | UP_DP) & ~FPU_TRAP;   // Store the correct PC for FPU Trap
259
 
260
endmodule
261
 
262 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
263 9 ns32kum
//
264
//      3. REGISTER             General Purpose Registers
265
//
266 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
267 9 ns32kum
module REGISTER( BCLK, ENWR, DOWR, BYDIN, DIN, RADR, WADR, WMASKE, DOUT, SELI );
268
 
269
input                   BCLK;
270
input                   DOWR,ENWR;
271
input   [31:0]   BYDIN,DIN;
272
input    [7:0]   RADR;
273
input    [5:0]   WADR;
274
input    [1:0]   WMASKE;
275
 
276
output  [31:0]   DOUT;
277
output reg              SELI;
278
 
279 23 ns32kum
reg              [2:0]   mx;
280 9 ns32kum
 
281 23 ns32kum
wire     [2:0]   be;
282 9 ns32kum
wire                    eq_rw;
283
 
284
// +++++++++++++++++++ Memories ++++++++++++++++++++
285
 
286 23 ns32kum
reg             [15:0]   REGFILE_C [0:63];        // Byte 3 and 2 , Verilog allows no "Byte Write" in wider memories !!!
287
reg              [7:0]   REGFILE_B [0:63];        // Byte 1
288
reg              [7:0]   REGFILE_A [0:63];        // Byte 0
289 9 ns32kum
reg             [31:0]   RF;
290
 
291 23 ns32kum
assign  be = {WMASKE[1],(WMASKE[1] | WMASKE[0]),1'b1};
292 9 ns32kum
 
293
assign  eq_rw = ENWR & (RADR[5:0] == WADR);
294
 
295 23 ns32kum
always @(posedge BCLK) if (RADR[7]) mx[2:0] <= be[2:0] & {{3{eq_rw}}};
296 9 ns32kum
 
297
always @(posedge BCLK) if (RADR[7]) SELI <= RADR[6];
298
 
299 23 ns32kum
assign DOUT[31:16] = mx[2] ? BYDIN[31:16] : RF[31:16];
300
assign DOUT[15:8]  = mx[1] ? BYDIN[15:8]  : RF[15:8];
301
assign DOUT[7:0]   = mx[0] ? BYDIN[7:0]   : RF[7:0];
302 9 ns32kum
 
303
// ++++++++++++++++ Register File 64 * 32 Bits ++++++++++++
304
 
305
always @(posedge BCLK)
306
        if (RADR[7])
307
                begin
308 23 ns32kum
                        RF[31:16] <= REGFILE_C[RADR[5:0]];
309 9 ns32kum
                        RF[15:8]  <= REGFILE_B[RADR[5:0]];
310
                        RF[7:0]   <= REGFILE_A[RADR[5:0]];
311
                end
312
 
313
always @(posedge BCLK)
314
        if (DOWR)
315
                begin
316 23 ns32kum
                        if (be[2]) REGFILE_C[WADR] <= DIN[31:16];
317
                        if (be[1]) REGFILE_B[WADR] <= DIN[15:8];
318
                        if (be[0]) REGFILE_A[WADR] <= DIN[7:0];
319 9 ns32kum
                end
320
 
321
endmodule
322
 

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