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1 9 ns32kum
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6
// Filename: SP_FPU.v
7
// Version:  1.0
8
// Date:     30 May 2015
9
//
10
// Copyright (C) 2015 Udo Moeller
11
// 
12
// This source file may be used and distributed without 
13
// restriction provided that this copyright statement is not 
14
// removed from the file and that any derivative work contains 
15
// the original copyright notice and the associated disclaimer.
16
// 
17
// This source file is free software; you can redistribute it 
18
// and/or modify it under the terms of the GNU Lesser General 
19
// Public License as published by the Free Software Foundation;
20
// either version 2.1 of the License, or (at your option) any 
21
// later version. 
22
// 
23
// This source is distributed in the hope that it will be 
24
// useful, but WITHOUT ANY WARRANTY; without even the implied 
25
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
26
// PURPOSE. See the GNU Lesser General Public License for more 
27
// details. 
28
// 
29
// You should have received a copy of the GNU Lesser General 
30
// Public License along with this source; if not, download it 
31
// from http://www.opencores.org/lgpl.shtml 
32
// 
33
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
34
//
35
//      Modules contained in this file:
36
//      1. ADDSUB               Adder and Subtractor for 36 bit
37
//      2. SFPU_ADDSUB  Single Precision Floating Point Adder/Subtractor and Converter
38
//      3. SFPU_MUL             Single Precision Floating Point Multiplier
39
//      4. SP_FPU               Top Level of Single Precision Floating Point Unit
40
//
41 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
42 9 ns32kum
 
43 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
44 9 ns32kum
//
45
//      1. ADDSUB               Adder and Subtractor for 36 bit
46
//
47 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
48 9 ns32kum
module ADDSUB (dataa, datab, add_sub, result);
49
 
50
        input   [35:0]   dataa,datab;
51
        input                   add_sub;        // 1 = Addition , 0 = Subtraction
52
        output  [35:0]   result;
53
 
54
        assign result = dataa + (add_sub ? datab : ~datab) + {35'd0,~add_sub};
55
 
56
endmodule
57
 
58 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
59 9 ns32kum
//
60
//      2. SFPU_ADDSUB  Single Precision Floating Point Adder/Subtractor and Converter
61
//
62 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
63 9 ns32kum
module SFPU_ADDSUB ( SRC1, SRC2, NZEXP, BWD, SELECT, OUT, IOUT, CMPRES );
64
 
65
        input   [31:0]   SRC1,SRC2;      // Input data
66
        input    [2:1]  NZEXP;
67
        input    [1:0]   BWD;            // size of integer
68
        input    [3:0]   SELECT;
69
 
70
        output  [36:0]   OUT;            // the result
71
        output  [31:0]   IOUT;           // result of ROUNDFi/TRUNCFi/FLOORFi
72
        output   [1:0]   CMPRES;
73
 
74
        // ++++++++++++++++++++++++++++++++++
75
        // MOViF : 1. step
76
 
77
        reg  [31:8]     movdat;
78
        wire [31:0]      movif;
79
 
80
        always @(BWD or SRC1)
81
                casex({BWD,SRC1[15],SRC1[7]})
82
                  4'b00x0 : movdat =  24'h0000_00;                              // Byte
83
                  4'b00x1 : movdat =  24'hFFFF_FF;
84
                  4'b010x : movdat = {16'h0000,SRC1[15:8]};             // Word
85
                  4'b011x : movdat = {16'hFFFF,SRC1[15:8]};
86
                default   : movdat = SRC1[31:8];                                // Double
87
                endcase
88
 
89
        assign movif = movdat[31] ? (32'h0 - {movdat,SRC1[7:0]}) : {movdat,SRC1[7:0]};
90
                                                                // -2^31 is kept
91
 
92
        // ROUNDFi/TRUNCFi/FLOORFi : 1. step
93
 
94
        reg                     ovflag,ovflag2;
95
        wire [8:0]       rexdiff,rexo;
96
        wire            rovfl,minint;
97
        wire            ganzklein;      // Flag for 0
98
 
99
        assign rexdiff = 9'h09D - {1'b0,SRC1[30:23]};   // 4..0 is the right shift value
100
        assign rovfl = (ovflag | ovflag2) & (SELECT[1:0] == 2'b11) & ~minint;
101
        assign ganzklein = (~rexdiff[8] & (rexdiff[7:5] != 3'b000));    // 0 is implicit via SRC1[30:23]=0
102
 
103
        // Detection of Overflow
104
        assign rexo = ({1'b0,SRC1[30:23]} - {8'h3F,~BWD[1]});   // subtract B/W = 7F , D = 7E
105
 
106
        always @(BWD or rexo)
107
                casex (BWD)
108
                  2'b00 : ovflag = (~rexo[8] & (rexo[7:3] != 5'h0));    // Exponent 0..7 because of -128.4 => -128
109
                  2'b01 : ovflag = (~rexo[8] & (rexo[7:4] != 4'h0));    // Exponent 0..15 because of -128.4 => -128
110
                default : ovflag = (~rexo[8] & (rexo[7:5] != 3'h0));    // Exponent only 0..30 
111
                endcase
112
 
113
        assign minint = (SRC1 == 32'hCF00_0000) & BWD[1];       // detection of -2^31
114
 
115
        // ++++++++++++++++++++++++++++++++++
116
        // ADD/SUB : 1. step : which operand ist bigger ? if required exchange
117
        // SUB/CMP : SRC2 - SRC1
118
 
119
        wire  [8:0]      exdiff;
120
        wire [23:0]      madiff;
121
        wire            switch,sign,sign1,sign2;
122
        wire            variante;
123
        wire            vorz,addflag;
124
        wire [35:0]      result_sw,result_nosw;
125
        wire [24:0] value1,value2;
126
 
127
        wire [35:0] result;
128
 
129
        assign exdiff = {1'b0,SRC2[30:23]} - {1'b0,SRC1[30:23]};        // Difference of Exponents
130
        assign madiff = {1'b0,SRC2[22:0]}  - {1'b0,SRC1[22:0]};           // Difference of Mantissas
131
 
132
        // if exdiff = 0 the shifter to the right is not needed ! 
133 11 ns32kum
        assign variante = (exdiff[8:1] == 8'h00) | (exdiff == 9'h1FF) | SELECT[1];      // MUX at the end, ROUND/TRUNC/MOViF uses case 1
134 9 ns32kum
 
135
// ++++++++++++++++++++++++++  1. case works on MOViF  +++++++++++++++++++++++++++++++++++++++
136
 
137
        assign switch = exdiff[8] | ((exdiff[7:0] == 8'h0) & madiff[23]);        // exchange ?
138
 
139
        assign value1 = exdiff[0] ? {1'b0,NZEXP[1],SRC1[22:0]} : {NZEXP[1],SRC1[22:0],1'b0};
140
        assign value2 = exdiff[0] ? {1'b0,NZEXP[2],SRC2[22:0]} : {NZEXP[2],SRC2[22:0],1'b0};
141
 
142
        // The Subtraction needs 3 Guard-Bits after LSB for rounding ! 36 Bit wide
143
        //                                                                                              1
144
        ADDSUB  addsub_nosw     (.dataa({1'b0,SRC2[30:23],NZEXP[2],SRC2[22:0],3'b000}),
145
                                                 .datab({9'h0,value1,2'b0}), .add_sub(addflag),
146
                                                 .result(result_nosw) );
147
 
148
        ADDSUB  addsub_sw       (.dataa({1'b0,SRC1[30:23],NZEXP[1],SRC1[22:0],3'b000}),
149
                                                 .datab({9'h0,value2,2'b0}), .add_sub(addflag),
150
                                                 .result(result_sw) );
151
 
152
        assign result = switch ? result_sw : result_nosw;
153
 
154
        //      SRC2   SRC1     : switch = 0            SRC2   SRC1 : switch = 1
155
        //        5  +   3  : +(5 + 3) =  8               3  +   5  : +(5 + 3) =  8             SELECT[0] = 0
156
        //        5  + (-3) : +(5 - 3) =  2               3  + (-5) : -(5 - 3) = -2
157
        //      (-5) +   3  : -(5 - 3) = -2             (-3) +   5  : +(5 - 3) =  2
158
        //      (-5) + (-3) : -(5 + 3) = -8             (-3) + (-5) : -(5 + 3) = -8
159
        //        5  -   3  : +(5 - 3) =  2               3  -   5  : -(5 - 3) = -2             SELECT[0] = 1
160
        //        5  - (-3) : +(5 + 3) =  8               3  - (-5) : +(5 + 3) =  8
161
        //      (-5) -   3  : -(5 + 3) = -8             (-3) -   5  : -(5 + 3) = -8
162
        //      (-5) - (-3) : -(5 - 3) = -2             (-3) - (-5) : +(5 - 3) =  2
163
 
164
        assign sign1 = SRC1[31];
165
        assign sign2 = SRC2[31];
166
 
167
        assign vorz    = switch ? (SELECT[0] ^ sign1) : sign2;
168
        assign addflag = ~(SELECT[0] ^ (sign1 ^ sign2));
169
 
170
        // CMPF : 1. step : what happend if Invalid Operand occurs - no Flag update !
171
 
172 11 ns32kum
        assign CMPRES[1] = ~CMPRES[0] & (switch ? ~sign1 : sign2);               // see table above : N-Bit=1 if SRC1 > SRC2
173 9 ns32kum
        assign CMPRES[0] = (SRC1 == SRC2) | (~NZEXP[2] & ~NZEXP[1]);     // Z-Bit : SRC1=SRC2, +0.0 = -0.0
174
 
175
        // ++++++++++++++++++++++++++++++++++
176
        // ADD/SUB : 3. step : prepare of Barrelshifter Left
177
 
178
        wire [31:0] blshift;
179
        wire  [9:0]      shiftl;
180
        wire            shift_16;
181
        wire [33:0] add_q;
182
        wire [31:0]      muxsrc2;
183
        wire  [1:0] inex;
184
 
185
        assign blshift = SELECT[1] ? movif : {result[26:0],5'h00};       // Feeding of MOViF
186
 
187
        assign shiftl = SELECT[1] ? 10'h09E : {1'b0,result[35:27]};      // MOViF
188
 
189
        assign shift_16 = (blshift[31:16] == 16'h0000);
190
 
191
        // In case of ADD the result bypasses the Barrelshifter left
192
        assign add_q = (muxsrc2[24] != result[27]) ? {result[35:3],(result[2:0] != 3'b000)}
193
                                                                                           : {result[35:27],result[25:2],(result[1:0] != 2'b00)} ;
194
 
195
        // ++++++++++++++++++++++++++++++++++
196
        // ADD/SUB : 4. step : Barrelshifter left for SUB and MOViF :
197
 
198
        wire            shift_8,shift_4,shift_2,shift_1,zero;
199
        wire  [1:0] lsb_bl;
200
        wire [31:0]      blshifta,blshiftb,blshiftc,blshiftd,blshifte;
201
        wire  [9:0]      expol;
202
        wire [36:0] out_v1;
203
 
204
        assign blshifta = shift_16 ? {blshift[15:0],16'h0000}    : blshift;
205
        assign shift_8 = (blshifta[31:24] == 8'h00);
206
        assign blshiftb = shift_8  ? {blshifta[23:0],8'h00}      : blshifta;
207
        assign shift_4 = (blshiftb[31:28] == 4'h0);
208
        assign blshiftc = shift_4  ? {blshiftb[27:0],4'h0}               : blshiftb;
209
        assign shift_2 = (blshiftc[31:30] == 2'b00);
210
        assign blshiftd = shift_2  ? {blshiftc[29:0],2'b00}      : blshiftc;
211
        assign shift_1 = ~blshiftd[31];
212
        assign blshifte = shift_1  ? {blshiftd[30:0],1'b0}               : blshiftd;
213
 
214
        // Overflow at ROUNDFi/TRUNCFi/FLOORFi via overflow in exponent shown, SELECT[1] is then 1 !
215
        assign expol = (shiftl - {5'h00,shift_16,shift_8,shift_4,shift_2,shift_1}) | {1'b0,rovfl,8'h00};
216
 
217
        // Inexact at ROUNDFi/TRUNCFi/FLOORFi : evaluation for all one level higher
218
        assign lsb_bl = (SELECT[1:0] == 2'b11) ? inex : {blshifte[7],(blshifte[6:0] != 7'h00)};
219
 
220
        assign zero =  (~SELECT[1] & ~NZEXP[2] & ~NZEXP[1])
221
                                 | ((blshift == 32'h0) & ((~addflag & ~SELECT[1]) | (SELECT[1:0] == 2'b10)));
222
 
223
        assign sign = SELECT[1] ? movdat[31] : vorz;
224
 
225
        assign out_v1 = (addflag & ~SELECT[1]) ? {zero,sign,1'b0,add_q}
226
                                                                                   : {zero,sign,expol,blshifte[30:8],lsb_bl};
227
 
228
// +++++++++++++++++++++++++  2. case works on ROUND/TRUNC/FLOOR  ++++++++++++++++++++++++++++++++++
229
 
230
        wire            vswitch;
231
        wire  [4:0]      shift1,shift2;
232
        wire  [8:0]      exdiff12;
233
        wire [23:0]      muxsrc1;
234
        wire [32:9]     pipe1;  // numbering special for Right Shifter
235
        wire  [4:0]      shift;
236
 
237 11 ns32kum
// the difference between SRC1 and SRC2 is bigger/equal 4:1 => no Barrelshifter after ADDSUB neccessary
238 9 ns32kum
 
239
        assign vswitch = exdiff[8];     // exchange ?
240
 
241
        assign shift1 = (exdiff[7:5] != 3'h0) ? 5'h1F : exdiff[4:0];
242
        assign exdiff12 = {1'b0,SRC1[30:23]} - {1'b0,SRC2[30:23]};      // caclulate already
243
        assign shift2 = (exdiff12[7:5] != 3'h0) ? 5'h1F : exdiff12[4:0];
244
 
245 11 ns32kum
        assign muxsrc2 = vswitch ? {SRC1[30:23],1'b1,SRC1[22:0]} : {SRC2[30:23],1'b1,SRC2[22:0]}; // Including exponent
246 9 ns32kum
        assign muxsrc1 = vswitch ? {NZEXP[2],SRC2[22:0]} : {NZEXP[1],SRC1[22:0]};
247
 
248 11 ns32kum
        assign pipe1 = SELECT[1] ? (ganzklein ? 24'h0 : {NZEXP[1],SRC1[22:0]}) : muxsrc1;        // Feeding in R.T.F.
249 9 ns32kum
 
250
        assign shift = SELECT[1] ? rexdiff[4:0] : (vswitch ? shift2 : shift1);
251
 
252
        // ++++++++++++++++++++++++++++++++++
253
        // ADD/SUB + ROUND/TRUNC/FLOOR : 2. step : Barrelshifter to right -->
254
 
255
        wire [32:0] brshifta,brshiftb,brshiftc,brshiftd;
256
        wire [32:0] brshifte;    // last stage
257
 
258
        // 33322222222221111111111
259
        // 2109876543210987654321098765432-10
260
        // 1VVVVVVVVVVVVVVVVVVVVVVV0000000-00   // last 2 Bit for rounding
261
 
262
        assign brshifta = shift[4] ? {16'h0,pipe1[32:17],  (pipe1[16:9]   != 8'h00)}  : {pipe1,9'h0};
263
        assign brshiftb = shift[3] ? { 8'h0,brshifta[32:9],(brshifta[8:0] != 9'h000)} : brshifta;
264
        assign brshiftc = shift[2] ? { 4'h0,brshiftb[32:5],(brshiftb[4:0] != 5'h00)}  : brshiftb;
265
        assign brshiftd = shift[1] ? { 2'h0,brshiftc[32:3],(brshiftc[2:0] != 3'h0)}   : brshiftc;
266
        assign brshifte = shift[0] ? { 1'b0,brshiftd[32:2],(brshiftd[1:0] != 2'h0)}   : brshiftd;
267
 
268
        // ++++++++++++++++++++++++++++++++++
269
        // ROUNDFi/TRUNCFi/FLOORFi : 3. step : round to integer
270
 
271
        reg                     car_ry;
272
        wire [30:0] compl;
273
        wire [31:0] iadder;
274
 
275
        assign inex = brshifte[1:0];             // Inexact-Flag-Data via multiplexer at the end
276
 
277
        always @(SELECT or sign1 or brshifte or inex or ganzklein)
278
                casex (SELECT[3:2])
279
                    2'b00 : car_ry = sign1 ^ ((brshifte[2:0] == 3'b110) | (inex == 2'b11));      // ROUNDLi
280 11 ns32kum
                    2'b1x : car_ry = sign1 ? (~ganzklein & (inex == 2'b00)) : 1'b0;     // +numbers like TRUNCLi, -numbers round to "-infinity"
281 9 ns32kum
                  default : car_ry = sign1;     // TRUNCLi , simple cut
282
                endcase
283
 
284
        assign compl  = sign1 ? ~brshifte[32:2] : brshifte[32:2];
285
 
286
        assign iadder = {sign1,compl} + {31'h0,car_ry};
287
 
288
        assign IOUT = minint ? 32'h8000_0000 : iadder;
289
 
290
        always @(iadder or BWD or sign1)        // special overflow detection i.e. -129 bis -255 bei Byte
291
                casex (BWD)                                             // or 127.9 -> 128 = Fehler !
292
                  2'b00 : ovflag2 = (iadder[8]  != iadder[7]);  // Byte
293
                  2'b01 : ovflag2 = (iadder[16] != iadder[15]); // Word
294
                default : ovflag2 = 1'b0;
295
                endcase
296
 
297
        // ++++++++++++++++++++++++++++++++++
298
        // only ADD/SUB : 3. step : Add or Subtract
299
        // the modul ADDSUB integrates the carry from the mantissa : 35 Bit
300
 
301
        wire            lsb;
302
        wire [35:0]      vresult;
303
        wire  [7:0]      eminus1;
304
        wire [33:0] vadd_q,vsub_q;
305
        wire            vzero;
306
        wire [36:0] out_v0;
307
 
308
        assign lsb = (brshifte[6:0] != 7'h00);
309
 
310
        // Adder-Definition : "0"(8 Bit Exponent)"1"(23 Bit Mantissa)"000"
311
 
312
        ADDSUB  addsub_v        (.dataa({1'b0,muxsrc2,3'b000}),
313
                                                 .datab({9'h0,brshifte[32:7],lsb}), .add_sub(addflag),
314
                                                 .result(vresult) );
315
 
316 11 ns32kum
        assign eminus1 = muxsrc2[31:24] - 8'h01;        // a greater Underflow can not exist, because minimal Exponent = 0..01
317 9 ns32kum
 
318
        // Case ADD : Bit 23 : LSB of exponent
319
        assign vadd_q = (muxsrc2[24] != vresult[27]) ? {vresult[35:3],(vresult[2:0] != 3'b000)}
320
                                                                                                 : {vresult[35:27],vresult[25:2],(vresult[1:0] != 2'b00)} ;
321
 
322
        // Case SUB : Bit 26 : "hidden" MSB of mantissa
323 11 ns32kum
        assign vsub_q = vresult[26] ? {vresult[35:27],     vresult[25:2],(vresult[1:0] != 2'b00)}        // like the vadd_q "0" case
324 9 ns32kum
                                                            : {vresult[35],eminus1,vresult[24:0]} ;
325
 
326
        // SELECT[1] has here no meaning
327
        assign vzero = (vresult[26:0] == 27'h0) & ~addflag;      // only if "-" can be the result 0
328
 
329
        assign out_v0 = addflag ? {vzero,vorz,1'b0,vadd_q}
330
                                                        : {vzero,vorz,1'b0,vsub_q} ;
331
 
332
        assign OUT = variante ? out_v1 : out_v0;        // Last multiplexer
333
 
334
endmodule
335
 
336 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
337 9 ns32kum
//
338
//      3. SFPU_MUL             Single Precision Floating Point Multiplier
339
//
340 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
341 9 ns32kum
module SFPU_MUL ( SRC1, SRC2, MRESULT, NZEXP, OUT);
342
 
343
        input   [31:0]   SRC1,SRC2;      // only exponent of input data used
344
        input   [47:0]   MRESULT;
345
        input    [2:1]  NZEXP;          // Flags of input data
346
 
347
        output  [36:0]   OUT;            // The result
348
 
349
        wire  [9:0] exponent,expoh,expol;
350
        wire  [1:0] restlow,resthigh;
351
        wire            zero,sign,orlow;
352
 
353
        assign zero =   ~NZEXP[2] | ~NZEXP[1];  // one of both NULL -> NULL is the result
354
        assign sign =   (SRC1[31] ^ SRC2[31]) & ~zero;
355
        assign orlow =  (MRESULT[21:0] != 22'b0);
356
 
357
        assign restlow  = {MRESULT[22],orlow};
358
        assign resthigh = {MRESULT[23],(MRESULT[22] | orlow)};
359
 
360
        assign exponent = {2'b00,SRC1[30:23]} + {2'b00,SRC2[30:23]};
361
        assign expoh    = exponent - 10'h07E;
362
        assign expol    = exponent - 10'h07F;    // for MSB if MRESULT=0
363
 
364
        assign OUT = MRESULT[47] ? {zero,sign,expoh,MRESULT[46:24],resthigh}
365
                                                         : {zero,sign,expol,MRESULT[45:23],restlow};
366
 
367
endmodule
368
 
369 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
370 9 ns32kum
//
371
//      4. SP_FPU               Top Level of Single Precision Floating Point Unit
372
//
373 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
374
module SP_FPU (BCLK, OPCODE, SRC1, SRC2, FSR, MRESULT, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX, LD_FSR, UP_SP);
375 9 ns32kum
 
376
        input                   BCLK;           // is not used !
377
        input    [7:0]   OPCODE;
378
        input   [31:0]   SRC1,SRC2;      // Input data
379
        input    [8:3]  FSR;            // Floating Point Status Register
380
        input   [47:0]   MRESULT;        // Multiplier result
381
        input    [1:0]   BWD;            // Size of integer
382
        input                   FL;
383
 
384
        output  [31:0]   FP_OUT,I_OUT;   // The results
385
        output   [4:0]   TT_SP;          // Trap-Type
386
        output   [2:0]   SP_CMP;         // CMPF result
387
        output                  SP_MUX,LD_FSR,UP_SP;
388
 
389
        reg              [2:0]   tt;
390
        reg              [3:0]   select;
391
        reg                             car_ry;
392
 
393
        wire    [36:0]   mulout,addout,fpout;
394
        wire     [2:1]  nzexp;
395
        wire    [34:2]  rund;           // Indexnumbers like xxxout
396
        wire                    overflow,underflow,inexact;
397
        wire                    op_cmp;
398
        wire                    nan,nan_1,nan_2;
399
 
400
        // Control of datapath 
401
 
402
        always @(OPCODE)
403
                casex (OPCODE)
404
                  8'b1011_0000 : select = 4'b1000;      // 0 0 0 :      ADDF    Shifter are reused
405
                  8'b1011_0100 : select = 4'b1001;      // 0 0 1 :      SUBF
406
                  8'b1001_000x : select = 4'b1010;      // 0 1 0 :      MOViF
407
                  8'b1001_100x : select = 4'b1011;      // 0 1 1 :      ROUNDFi
408
                  8'b1001_101x : select = 4'b1011;      // 0 1 1 :      TRUNCFi
409
                  8'b1001_111x : select = 4'b1011;      // 0 1 1 :      FLOORFi
410
                  8'b1011_0010 : select = 4'b1001;      // 0 0 1 :      CMPF
411
                  8'b1011_1100 : select = 4'b1100;      // 1 x x :      MULF
412
                  default      : select = 4'b0;
413
                endcase
414
 
415
        assign SP_MUX = select[3] & (select[1:0] != 2'b11) & FL; // Output multiplexer
416
 
417 11 ns32kum
        assign LD_FSR = (OPCODE[7:4] == 4'h9) & (OPCODE[3:1] == 3'b001);        // LFSR does only Double (according datasheet NS32016)
418 9 ns32kum
        assign UP_SP  = select[3] & FL;                         // All FPU opcodes of SP_FPU
419
        assign op_cmp = (OPCODE == 8'hB2) & FL;
420
 
421
        // SRCFLAGS
422
 
423
        assign nzexp[2] = (SRC2[30:23] != 8'd0);                // only exponent 0 ,denormalized Number => NAN !
424
        assign nzexp[1] = (SRC1[30:23] != 8'd0);                // only exponent 0 ,denormalized Number => NAN !
425
        assign nan_2    = (SRC2[30:23] == 8'hFF) | (~nzexp[2] & (SRC2[22:0] != 23'd0));  // NAN
426
        assign nan_1    = (SRC1[30:23] == 8'hFF) | (~nzexp[1] & (SRC1[22:0] != 23'd0));  // NAN
427
 
428
        assign nan = (select[1:0] == 2'b11) ? nan_1 : (~select[1] & (nan_2 | nan_1));
429
 
430
        // 001 : ADDF,... + 011 : CMPF
431
        SFPU_ADDSUB IADDSUB     ( .SRC1(SRC1), .SRC2(SRC2), .NZEXP(nzexp), .BWD(BWD),
432
                                                  .SELECT({OPCODE[2:1],select[1:0]}), .OUT(addout), .IOUT(I_OUT), .CMPRES(SP_CMP[1:0]) );
433
 
434
        // 100 : MULF
435
        SFPU_MUL IMUL ( .SRC1(SRC1), .SRC2(SRC2), .MRESULT(MRESULT), .OUT(mulout), .NZEXP(nzexp) );
436
 
437
        // FP - Pfad : selection of result and rounding :
438
 
439
        assign fpout = (OPCODE[5] & OPCODE[3]) ? mulout : addout;
440
 
441
        always @(FSR or fpout)  // calculate Carry according rounding mode, fpout[35] = sign bit
442
                casex (FSR[8:7])
443
                  2'b00 : car_ry = ((fpout[1:0] == 2'b10) & fpout[2]) | (fpout[1:0] == 2'b11);    // round to nearest
444
                  2'b10 : car_ry = ~fpout[35] & (fpout[1:0] != 2'b00);   // round to positiv infinity
445
                  2'b11 : car_ry =  fpout[35] & (fpout[1:0] != 2'b00);   // round to negativ infinity
446
                default : car_ry = 1'b0;                                                                // round to zero
447
                endcase
448
 
449
        assign rund = {fpout[34:2]} + {32'h0,car_ry};
450
 
451
        // Detection of Overflow, Underflow and Inexact : epxonent is [34:25] = 10 Bits
452
        assign overflow  = ~rund[34] & (rund[33] | (rund[32:25] == 8'hFF));
453
        assign underflow = (rund[34] | (rund[33:25] == 9'h0)) & ~fpout[36];     // Zero-Flag
454
        assign inexact   = (fpout[1:0] != 2'b00);
455
 
456
        // CMPF can have no other error except NAN 
457
        always @(nan or op_cmp or overflow or underflow or inexact or FSR)
458
                casex ({nan,op_cmp,overflow,FSR[3],underflow,FSR[5],inexact})
459
                        7'b1xxxxxx : tt = 3'b101;       // Invalid operation
460
                        7'b001xxxx : tt = 3'b010;       // Overflow
461
                        7'b00011xx : tt = 3'b001;       // Underflow
462
                        7'b0000011 : tt = 3'b110;       // Inexact Result
463
                        default    : tt = 3'b000;       // no error
464
                endcase
465
 
466
        assign TT_SP = {(inexact & ~op_cmp),(underflow & ~op_cmp),tt};
467
        assign SP_CMP[2] = nan;
468
 
469
        // Underflow Special case and force ZERO 
470
        assign FP_OUT = (underflow | fpout[36]) ? 32'd0 : {fpout[35],rund[32:2]};
471
 
472
endmodule

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