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[/] [m32632/] [trunk/] [rtl/] [STEUER_MISC.v] - Blame information for rev 14

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1 9 ns32kum
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6
// Filename: STEUER_MISC.v
7 14 ns32kum
// Version:  1.1 bug fix
8
// History:  1.0 first release of 30 Mai 2015
9
// Date:     21 January 2016
10 9 ns32kum
//
11 14 ns32kum
// Copyright (C) 2016 Udo Moeller
12 9 ns32kum
// 
13
// This source file may be used and distributed without 
14
// restriction provided that this copyright statement is not 
15
// removed from the file and that any derivative work contains 
16
// the original copyright notice and the associated disclaimer.
17
// 
18
// This source file is free software; you can redistribute it 
19
// and/or modify it under the terms of the GNU Lesser General 
20
// Public License as published by the Free Software Foundation;
21
// either version 2.1 of the License, or (at your option) any 
22
// later version. 
23
// 
24
// This source is distributed in the hope that it will be 
25
// useful, but WITHOUT ANY WARRANTY; without even the implied 
26
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
27
// PURPOSE. See the GNU Lesser General Public License for more 
28
// details. 
29
// 
30
// You should have received a copy of the GNU Lesser General 
31
// Public License along with this source; if not, download it 
32
// from http://www.opencores.org/lgpl.shtml 
33
// 
34
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
35
//
36
//      Modules contained in this file:
37
//      1. OPDEC_REG    Central Instruction Register
38
//      2. PROG_COUNTER Program Counters
39
//      3. REG_LIST             Register List Evaluation
40
//      4. ILL_UNDEF    Illegal and Undefined Opcodes Detection
41
//      5. GRUPPE_2             Decoder and State Machine for GRUPPE_2 Opcodes
42
//
43 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
44 9 ns32kum
 
45 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
46 9 ns32kum
//
47
//      1. OPDEC_REG    Central Instruction Register
48
//
49 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
50
module OPDEC_REG ( BCLK, BRESET, NEW, ACC_STAT, PROT_ERROR, ALSB, USED, IC_DIN, IC_INIT, DC_INIT, Y_INIT, RESTART, STOP_IC,
51 9 ns32kum
                                   OPREG, ANZ_VAL, IC_READ, NEW_PC, NEXT_ADR, DATA_HOLD, ABORT, IC_TEX, INIT_DONE);
52
 
53
        input                   BCLK,BRESET;
54
        input                   NEW;            // a program jump took place
55
        input    [3:0]   ACC_STAT;       // ICACHE signals data is available or Abort
56
        input                   PROT_ERROR;     // comes direct from ICACHE
57
        input    [1:0]   ALSB;           // lower addressbits of access address to ICACHE
58
        input    [2:0]   USED;           // Message from DECODER how many bytes were used
59
        input   [31:0]   IC_DIN;         // ICACHE Data
60
        input                   IC_INIT,DC_INIT,Y_INIT; // Initialising or new setting is running
61
        input                   RESTART;        // "Break" of Instruction Pipeline - set up new i.e. after load of PSR
62
        input                   STOP_IC;        // For LMR and CINV
63
 
64
        output  [55:0]   OPREG;          // this is the Central Opcode Decode Register, length = 7 bytes
65
        output   [2:0]   ANZ_VAL;
66
        output                  IC_READ;
67
        output                  NEW_PC;
68
        output                  NEXT_ADR;
69
        output                  DATA_HOLD;
70
        output                  ABORT;
71
        output   [2:0]   IC_TEX;
72
        output                  INIT_DONE;
73
 
74
        reg             [55:0]   OPREG;
75
        reg              [2:0]   ANZ_VAL;
76
        reg                             IC_READ;
77
        reg                             ABORT;
78
        reg                             abort_flag;
79
        reg              [2:0]   IC_TEX;
80
        reg             [55:0]   data_to_ri;
81
        reg                             old_init;
82
        reg                             pre_new;
83
        reg                             new_reg;
84
        reg                             nseq_flag;
85
        reg                             stop_init;
86
 
87
        wire     [2:0]   new_anz;
88
        wire                    new_restart;
89
        wire                    acc_err,acc_ok,acc_ende;
90
 
91
        // ++++++++++++++++++++  Evaluation of ACC_STAT from Instructioncache  ++++++++++++++++++++++++++++
92
 
93
        // ACC_STAT[3:0] : PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK
94
 
95
        assign acc_err = ACC_STAT[3] | ACC_STAT[1] | PROT_ERROR;
96
        assign acc_ok  = ACC_STAT[0];
97
 
98
        always @(posedge BCLK or negedge BRESET)        // is kept until DECODER really needs the data !
99
                if (!BRESET) ABORT <= 1'b0;
100
                  else ABORT <=  (acc_err & ~(new_restart | pre_new)) | (ABORT & ~NEW_PC);
101
 
102 11 ns32kum
        always @(posedge BCLK) if (acc_err) IC_TEX <= (ACC_STAT[3] | PROT_ERROR) ? {nseq_flag,2'b11} : {nseq_flag,~ACC_STAT[2],ACC_STAT[2]};
103 9 ns32kum
 
104
        always @(posedge BCLK) nseq_flag <= NEW_PC | (nseq_flag & ~acc_ok);     // for MMU Status Register
105
 
106
        always @(posedge BCLK) abort_flag <= acc_err;
107 11 ns32kum
        assign acc_ende = ~IC_READ | acc_ok | abort_flag;       // abort_flag one cycle later is ok ! If no ICache access always end
108 9 ns32kum
 
109
        assign new_restart = NEW | RESTART;     // They are pulses
110
 
111
        // Branch work out : NEW/RESTART notice if access still not ended
112
        always @(posedge BCLK) pre_new <= (new_restart & ~acc_ende) | (pre_new & ~acc_ende & BRESET);
113
 
114
        assign NEW_PC = (new_restart | pre_new) & acc_ende;     // At the end of access geenerate new address !
115
 
116 11 ns32kum
        // There are 2 "NEW/RESTART" : "new_restart" combinatorical out of DECODER, "pre_new" out of Register
117 9 ns32kum
        always @(posedge BCLK) new_reg <= new_restart | pre_new | (new_reg & ~acc_ende & BRESET);
118
 
119
        always @(USED or OPREG) // Data first shift to the right
120
                case (USED)
121
                  3'b000 : data_to_ri = OPREG;
122
                  3'b001 : data_to_ri =               { 8'hxx, OPREG[55:8]};
123
                  3'b010 : data_to_ri =             {16'hxxxx,OPREG[55:16]};
124
                  3'b011 : data_to_ri =          {24'hxx_xxxx,OPREG[55:24]};
125
                  3'b100 : data_to_ri =        {32'hxxxx_xxxx,OPREG[55:32]};
126
                  3'b101 : data_to_ri =     {40'hxx_xxxx_xxxx,OPREG[55:40]};
127
                  3'b110 : data_to_ri =   {48'hxxxx_xxxx_xxxx,OPREG[55:48]};
128
                  3'b111 : data_to_ri = 56'hxx_xxxx_xxxx_xxxx;
129
                endcase
130
 
131
        assign new_anz = ANZ_VAL - USED;
132
 
133
        always @(posedge BCLK)
134
                casex ({new_reg,acc_ok,ALSB,new_anz})
135
                  7'b1_100_xxx : OPREG <=        {24'hxx_xxxx,IC_DIN};
136
                  7'b1_101_xxx : OPREG <=      {32'hxxxx_xxxx,IC_DIN[31:8]};
137
                  7'b1_110_xxx : OPREG <=   {40'hxx_xxxx_xxxx,IC_DIN[31:16]};
138
                  7'b1_111_xxx : OPREG <= {48'hxxxx_xxxx_xxxx,IC_DIN[31:24]};
139
                  7'b0_0xx_xxx : OPREG <= data_to_ri;
140
                  7'b0_1xx_000 : OPREG <= {24'hxx_xxxx,IC_DIN};
141
                  7'b0_1xx_001 : OPREG <= {   16'hxxxx,IC_DIN, data_to_ri[7:0]};
142
                  7'b0_1xx_010 : OPREG <= {      8'hxx,IC_DIN,data_to_ri[15:0]};
143
                  7'b0_1xx_011 : OPREG <= {            IC_DIN,data_to_ri[23:0]};
144
                  7'b0_1xx_1xx : OPREG <= data_to_ri;
145
                endcase
146
 
147
        always @(posedge BCLK or negedge BRESET)
148
                if (!BRESET) ANZ_VAL <= 3'b000;
149
                  else
150
                        casex ({new_restart,new_reg,acc_ok,new_anz[2]})
151
                          4'b1x_x_x : ANZ_VAL <= 3'b000;        // hard setting to 0
152
                          4'b01_0_x : ANZ_VAL <= 3'b000;
153
                          4'b01_1_x : ANZ_VAL <= pre_new ? 3'b000 : 3'b100 - {1'b0,ALSB};
154
                          4'b00_0_x : ANZ_VAL <= new_anz;
155
                          4'b00_1_0 : ANZ_VAL <= new_anz + 3'b100;
156
                          4'b00_1_1 : ANZ_VAL <= new_anz;
157
                        endcase
158
 
159 11 ns32kum
        assign NEXT_ADR = new_reg ? (acc_ok & ~pre_new) : (acc_ok & ~new_anz[2]);       // switches MUX at PC resp. ICACHE
160 9 ns32kum
 
161
        // Instruction CACHE Control : READ is coming after all INITs are done
162
 
163
        always @(posedge BCLK) old_init <= IC_INIT | DC_INIT | Y_INIT;
164
 
165
        assign INIT_DONE = old_init & ~IC_INIT & ~DC_INIT;
166
 
167
        always @(posedge BCLK or negedge BRESET)
168
                if (!BRESET) stop_init <= 1'b0;
169
                        else stop_init <= stop_init | IC_READ;
170
 
171 11 ns32kum
        // The INIT_DONE should come after Reset. But it comes too at LMR PTB therefore extra enable after Reset !
172 9 ns32kum
        always @(posedge BCLK or negedge BRESET)
173
                if (!BRESET) IC_READ <= 1'b0;
174
                        else IC_READ <= (IC_READ & ~acc_err & ~(STOP_IC & acc_ok)) | NEW_PC | (INIT_DONE & ~stop_init);
175
 
176
        // The Opcode-Register can not store the data : keep them in ICACHE at IO-access
177
        assign DATA_HOLD = ~new_restart & ~new_reg & acc_ok & new_anz[2];
178
 
179
endmodule
180
 
181 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
182 9 ns32kum
//
183
//      2. PROG_COUNTER Program Counters
184
//
185 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
186
module PROG_COUNTER ( BCLK, BRESET, NEW, LOAD_PC, NEW_PC, NEXT_ADR, NEXT_PCA, DISP, PC_NEW, USED, USER, SAVE_PC, FPU_TRAP,
187 9 ns32kum
                                          ADIVAR, PC_ARCHI, PC_ICACHE, PC_SAVE, ALSB, IC_USER);
188
 
189
        input                   BCLK,BRESET;
190
        input                   NEW;
191
        input                   LOAD_PC;
192
        input                   NEW_PC;
193
        input                   NEXT_ADR;
194
        input                   NEXT_PCA;
195
        input   [31:0]   DISP;
196
        input   [31:0]   PC_NEW;
197
        input    [2:0]   USED;
198
        input                   USER;
199
        input                   SAVE_PC;
200
        input                   FPU_TRAP;
201
        input                   ADIVAR;
202
 
203
        output  [31:0]   PC_ARCHI;       // goes to Datapath
204
        output  [31:0]   PC_ICACHE;
205
        output  [31:0]   PC_SAVE;        // is the return address
206
        output   [1:0]   ALSB;
207
        output                  IC_USER;
208
 
209
        reg             [31:0]   PC_ARCHI;
210
        reg             [31:0]   pc_adduse;
211
        reg             [31:0]   pc_ic_reg;
212
        reg             [31:0]   fpu_trap_pc;
213
        reg                             IC_USER;
214
 
215
        wire    [31:0]   branch,pc_jump,next_pc,pc_icache_i;
216
 
217
        assign PC_SAVE = pc_adduse + {29'h0,USED};
218
        assign branch  = PC_ARCHI + DISP;
219
 
220
        assign pc_jump = LOAD_PC ? PC_NEW : branch;
221
 
222
        assign next_pc = NEW ? pc_jump : PC_SAVE;       // Only at NEW is the DISP correct !
223
 
224
        always @(posedge BCLK or negedge BRESET)
225
                if (!BRESET) pc_adduse <= 32'h0;
226
                  else
227
                        pc_adduse <= next_pc;
228
 
229
        // The Architectur - PC : Address mode "Programm Memory"-relativ
230
        // no BRESET because NEXT_PCA is immediately valid
231
        always @(posedge BCLK)
232
                if (FPU_TRAP) PC_ARCHI <= fpu_trap_pc;  // go back !
233
                  else
234
                        if (NEXT_PCA) PC_ARCHI <= pc_adduse;
235
 
236
        always @(posedge BCLK) if (SAVE_PC) fpu_trap_pc <= PC_ARCHI;    // Special storage for PC for FPU Trap
237
 
238
        always @(posedge BCLK or negedge BRESET)
239
                if (!BRESET) pc_ic_reg <= 32'h0;
240
                  else
241
                        pc_ic_reg <= pc_icache_i;
242
 
243 11 ns32kum
        // NEW is only one cycle long - but in pc_adduse is the PC stored when ACC_OK is not there and therefore NEW_PC
244 9 ns32kum
        // is used to initiate a new access in ICACHE
245 11 ns32kum
        assign pc_icache_i = NEW_PC ? (NEW ? pc_jump : pc_adduse) : (NEXT_ADR ? ({pc_ic_reg[31:2],2'b00} + 32'h0000_0004) : pc_ic_reg);
246 9 ns32kum
 
247
        // This MUX is extra for LMR IVAR,... and CINV build in
248
        assign PC_ICACHE = {(ADIVAR ? PC_NEW[31:4] : pc_icache_i[31:4]),pc_icache_i[3:0]};
249
 
250
        assign ALSB = pc_ic_reg[1:0];    // for OPDEC_REG
251
 
252
        // The IC_USER flag is allowed to switch synchronously with one cycle delay to PC_ICACHE
253
        always @(posedge BCLK or negedge BRESET)
254
                if (!BRESET) IC_USER <= 1'b0;
255
                  else
256
                        if (NEW_PC) IC_USER <= USER;
257
 
258
endmodule
259
 
260 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
261 9 ns32kum
//
262
//      3. REG_LIST             Register List Evaluation
263
//
264 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
265 9 ns32kum
module REG_LIST ( DIN, IPOS, INIT, OPOS, VALID);
266
 
267
        // Detects set bits in register list for SAVE/RESTORE & ENTER/EXIT
268
 
269
        input    [7:0]   DIN;
270
        input    [2:0]   IPOS;
271
        input                   INIT;
272
        output   [2:0]   OPOS;
273
        output                  VALID;
274
 
275
        reg              [7:1]  filter;
276
        wire     [7:0]   mdat_0;
277
        wire     [3:0]   mdat_1;
278
        wire     [1:0]   mdat_2;
279
 
280
        always @(IPOS or DIN)
281
                case (IPOS)
282
                  3'd0 : filter =  DIN[7:1];
283
                  3'd1 : filter = {DIN[7:2],1'b0};
284
                  3'd2 : filter = {DIN[7:3],2'b0};
285
                  3'd3 : filter = {DIN[7:4],3'b0};
286
                  3'd4 : filter = {DIN[7:5],4'b0};
287
                  3'd5 : filter = {DIN[7:6],5'b0};
288
                  3'd6 : filter = {DIN[7]  ,6'b0};
289
                  3'd7 : filter =           7'b0;
290
                endcase
291
 
292
        assign mdat_0  = INIT ? DIN : {filter,1'b0};
293
        assign OPOS[2] = (mdat_0[3:0] == 4'h0);
294
        assign mdat_1  = OPOS[2] ? mdat_0[7:4] : mdat_0[3:0];
295
        assign OPOS[1] = (mdat_1[1:0] == 2'b00);
296
        assign mdat_2  = OPOS[1] ? mdat_1[3:2] : mdat_1[1:0];
297
        assign OPOS[0] = ~mdat_2[0];
298
        assign VALID   = (mdat_2 != 2'b00);
299
 
300
endmodule
301
 
302 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
303 9 ns32kum
//
304
//      4. ILL_UNDEF    Illegal and Undefined Opcodes Detection
305
//
306 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
307 9 ns32kum
module ILL_UNDEF (OPREG, ANZ_VAL, USER, CFG, ILL, UNDEF );
308
 
309
        input   [23:0]   OPREG;
310
        input    [2:0]   ANZ_VAL;
311
        input    [3:1]  CFG;            // 3=CUSTOM,2=MMU,1=FPU
312
        input                   USER;
313
 
314
        output  reg             ILL;
315
        output                  UNDEF;
316
 
317
        reg                             undef_opc;
318
        reg                             undef_am;
319
        reg                             undef_im;
320
 
321
        wire     [2:0]   valid;
322
        wire                    gen12,gen22,gen13,gen23;
323
        wire                    igen12,igen22,igen13,igen23;
324
        wire                    lsbes;
325
 
326
        parameter udef_amode = 5'b10011;        // Undefined Addressing Mode
327
        parameter imode          = 5'b10100;    // Immediate Addressing Mode 
328
 
329
        // [2]= minimum 3, [1]= minimum 2, [0]=minimum 1
330 11 ns32kum
        assign valid = {(ANZ_VAL[2] | (ANZ_VAL[1:0] == 2'b11)),(ANZ_VAL[2:1] != 2'b00),(ANZ_VAL != 3'b000)};
331 9 ns32kum
        assign lsbes = (OPREG[1:0] == 2'b10);    // Tag of all 3 Byte opcodes
332
 
333
        // +++++++++++++++++++++++++  Detect illegale opcodes  +++++++++++++++++++
334
 
335
        always @(OPREG or lsbes or valid or USER)
336
                casex ({valid[2:1],OPREG[13:2],lsbes})
337
                  15'bx1_xx_x000_1x10_11_0 : ILL = USER;        // SPRi/LPRi DCR
338
                  15'bx1_xx_x001_xx10_11_0 : ILL = USER;        // SPRi/LPRi BPC/DSR
339
                  15'bx1_xx_xx10_xx10_11_0 : ILL = USER;        // SPRi/LPRi CAR/CFG/PSR
340
                  15'bx1_xx_x101_1x10_11_0 : ILL = USER;        // SPRi/LPRi USP
341
                  15'bx1_xx_x111_0x10_11_0 : ILL = USER;        // SPRi/LPRi INTBASE
342
                  15'bx1_xx_x0x1_0111_11_x : ILL = USER & OPREG[0];      // BICPSRW,BISPSRW
343
                  15'bx1_00_10xx_0000_11_1 : ILL = USER;        // SETCFG - Achtung : is coded as 2 Byte Opcode 
344
                  15'b1x_00_xxxx_0001_11_1 : ILL = USER;        // LMR/SMR/RDVAL/WRVAL
345
                  15'b1x_10_01xx_0001_11_1 : ILL = USER;        // CINV
346
                  default                                  : ILL = 1'b0;
347
                endcase
348
 
349
        // ++++++++++++++++++++++++ Detect Undefined opcodes  +++++++++++++++
350
 
351
        always @(OPREG or lsbes or valid or CFG)
352
                casex ({valid,OPREG[13:2],lsbes})
353
                  16'bx1x_xx_xxxx_1111_110 : undef_opc = 1'b1;          // Format 3 : xxx1
354
                  16'bx1x_xx_x100_0111_110 : undef_opc = 1'b1;          // Format 3 : 1000
355
                  16'b1xx_1x_xxxx_0000_111 : undef_opc = 1'b1;          // Format 5 : 1xxx
356
                  16'b1xx_01_xxxx_0000_111 : undef_opc = 1'b1;          // Format 5 : 01xx
357
                  16'b1xx_01_00xx_0100_111 : undef_opc = 1'b1;          // Format 6 : 0100
358
                  16'b1xx_10_10xx_x100_111 : undef_opc = 1'b1;          // Format 6/7 : 1010
359 11 ns32kum
                  16'b1xx_xx_xxxx_x011_111 : undef_opc = ~CFG[1];       // Format 9/11 : FPU Befehle wie MOVif etc. und ADDf etc.
360 9 ns32kum
                  16'b1xx_xx_xxxx_1111_111 : undef_opc = ~CFG[1];       // Format 12 : FPU Befehle wie POLYf etc.
361
                  16'b1xx_x1_xxxx_0001_111 : undef_opc = 1'b1;          // Format 14 : x1xx 
362
                  16'b1xx_10_00xx_0001_111 : undef_opc = 1'b1;          // Format 14 : 1000
363
                  16'b1xx_10_1xxx_0001_111 : undef_opc = 1'b1;          // Format 14 : 101x
364
                  16'b1xx_00_1xxx_0001_111 : undef_opc = ~CFG[2] | ~OPREG[18];  // Format 14 : LMR/SMR
365
                  16'b1xx_xx_xxxx_x011_011 : undef_opc = ~CFG[3];       // Format 15.1/15.5 : CUSTOM CCV0, CCAL0 etc.
366
                  16'b1xx_xx_xxxx_0001_011 : undef_opc = 1'b1;          // Format 15.0 - not yet in, requires HW change
367
                  16'b1xx_xx_xxxx_x1x1_011 : undef_opc = 1'b1;          // Format 15 : rest
368
                  16'b1xx_xx_xxxx_1001_011 : undef_opc = 1'b1;          // Format 15.4
369
                // completely undefined :
370
                  16'bxx1_xx_xxxx_0111_111 : undef_opc = 1'b1;          // Format 10
371
                  16'bxx1_xx_xxxx_100x_111 : undef_opc = 1'b1;          // Format 13/18
372
                  16'bxx1_xx_xxxx_x101_111 : undef_opc = 1'b1;          // Format 16/17
373
                  16'bxx1_xx_xxxx_xxx0_011 : undef_opc = 1'b1;          // Format 19
374
                  default                                  : undef_opc = 1'b0;
375
                endcase
376
 
377
        // 2. Undefined Addressing mode 5'b10011
378
 
379
        assign gen12 = (OPREG[15:11] == udef_amode);
380
        assign gen22 = (OPREG[10:6]  == udef_amode);
381
        assign gen13 = (OPREG[23:19] == udef_amode);
382
        assign gen23 = (OPREG[18:14] == udef_amode);
383
 
384
        always @(OPREG or valid or gen12 or gen22 or gen13 or gen23)
385 11 ns32kum
                if (valid[2] && (OPREG[7:5] != 3'b000) && (OPREG[3:0] == 4'b1110)) undef_am = gen13 | gen23;     // nearly all 3 Byte opcodes
386 9 ns32kum
                  else
387 11 ns32kum
                    undef_am = valid[1] & gen12 & (OPREG[1:0] != 2'b10) & ((OPREG[3:2] != 2'b11) & gen22);       // all 2 Byte opcodes
388 9 ns32kum
 
389
        // 3. When is Immediate not allowed ?
390
 
391
        assign igen12 = (OPREG[15:11] == imode);
392
        assign igen22 = (OPREG[10:6]  == imode);
393
        assign igen13 = (OPREG[23:19] == imode);
394
        assign igen23 = (OPREG[18:14] == imode);
395
 
396
        always @(*)
397
                casex ({valid[2:1],OPREG[13:2],lsbes})
398 11 ns32kum
                  15'bx1_xxxxxx_x0xx11_0 : undef_im =  igen12 & (OPREG[5:4] != 2'b01);  // Format 2 : ADDQD,SPR,Scond
399 9 ns32kum
                  15'bx1_xxxxxx_x10111_0 : undef_im =  igen12;          // Format 2 : ACB,MOVQ
400
                  15'bx1_xxxxx0_011111_0 : undef_im =  igen12;          // Format 3 : CXPD,JUMP,JSR
401
                  15'bx1_xxxxxx_xxxxx0_0 : undef_im =  igen22;          // Format 4
402 11 ns32kum
                  15'bx1_xxxxxx_xxxx01_0 : undef_im = (igen12 & (OPREG[5:4] == 2'b10))  // Format 4 : SRC1 - not ADDR
403 9 ns32kum
                                                                                         |(igen22 & (OPREG[5:4] != 2'b00)); // Format 4 : SRC2 - CMP
404
                  15'b1x_xxxxxx_x10011_1 : undef_im =  igen23;          // Format 6+7
405
                  15'b1x_xxx0xx_0x1011_1 : undef_im =  igen13 | igen23; // Format 8 EXT,CVTP
406
                  15'b1x_xxx0xx_101011_1 : undef_im =  igen23;          // Format 8 : INS
407
                  15'b1x_xxx0xx_111011_1 : undef_im =  igen13;          // Format 8 : CHECK
408
                  15'b1x_xxx1xx_101011_1 : undef_im =  igen13 | igen23; // Format 8 MOVUS,MOVSU
409
                  15'b1x_xxx1xx_011011_1 : undef_im =  igen23;          // Format 8 : FFS
410
                  15'b1x_xxxxxx_001111_1 : undef_im =  igen23;          // Format 9
411
                  15'b1x_xxxxxx_101111_1 : undef_im =  igen23 & (OPREG[13:10] != 4'h2); // Format 10 without CMPf
412
                  15'b1x_010xxx_111111_1 : undef_im =  igen23;          // Format 12 SCALB+LOGB
413
                  15'b1x_000xxx_000111_1 : undef_im =  igen13;          // Format 14 RDVAL+WRVAL
414
                  15'b1x_0011xx_000111_1 : undef_im =  igen13;          // Format 14 SMR
415
                  default                                : undef_im = 1'b0;
416
                endcase
417
 
418
        // Final Message :
419
 
420
        assign UNDEF = undef_opc | undef_am | undef_im;
421
 
422
endmodule
423
 
424 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
425 9 ns32kum
//
426
//      5. GRUPPE_2             Decoder and State Machine for GRUPPE_2 Opcodes
427
//
428 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
429
module GRUPPE_2 ( BCLK, PHASE_0, OPREG, PHASE, SRC_1, SRC_2, REGA1, REGA2, IRRW1, IRRW2, ADRD1, ADRD2, EXR12, EXR22,
430 9 ns32kum
                                  PHRD1, PHRD2, NXRD1, NXRW2, ACCA, OPERA,
431
                                  STATE_0, STATE_GROUP_50, STATE_GROUP_60 );
432
 
433
 
434
        input                   BCLK,PHASE_0;
435 14 ns32kum
        input   [18:0]   OPREG;
436 9 ns32kum
        input    [3:0]   PHASE;  // nur die 4 LSBs
437
        // Source 1 & 2 Inputs
438
        input    [6:0]   SRC_1,SRC_2,REGA1,REGA2,IRRW1,IRRW2;
439
        input   [18:0]   ADRD1,ADRD2,EXR12,EXR22;
440
        input    [3:0]   PHRD1,PHRD2;
441
        input    [3:0]   NXRD1,NXRW2;
442
        input    [3:0]   ACCA;   // ACCA = Access type : 0x Register
443
                                                        //      [3:2] or [1:0]          10 Memory
444
                                                        //                                              11 Memory + Index
445
        input   [10:0]   OPERA;
446
 
447
        output  [66:0]   STATE_0;
448
        output  [66:0]   STATE_GROUP_50,STATE_GROUP_60;
449
 
450
        reg             [66:0]   STATE_GROUP_50,STATE_GROUP_60;
451
        reg             [66:0]   STATE_0,state_50,state_53,state_54,state_55,state_58,state_59,state_5A;
452
        reg              [4:0]   op_code,op_reg_reg;
453
        reg              [7:0]   phsrc1,phsrc2;
454
        reg              [5:0]   chkreg;
455
        reg              [1:0]   bwdreg;
456
        reg                             tbit_flag,size_dw;
457
        reg                             inss_flag;
458 14 ns32kum
        reg                             ext_tos;
459 9 ns32kum
 
460 14 ns32kum
        wire    [18:0]   exoffset,re_wr,rexwr;
461 9 ns32kum
        wire    [10:0]   op_kust,op_bwd;
462
        wire     [7:0]   phchk;
463
        wire     [4:0]   op_reg;
464
        wire     [6:0]   src_1l,src_2l;
465
        wire     [5:0]   dest_2;
466
        wire     [3:0]   get8b_s,get8b_d;
467
        wire     [6:0]   rd_reg;
468
        wire    [10:0]   op_zext;
469
        wire     [3:0]   imdi;
470
 
471
        parameter dont_care     = 67'hx_xxxx_xxxx_xxxx_xxxx;
472
        // Address-Field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
473
        parameter addr_nop      = 19'h0;        // alle Parameter auf 0
474
        parameter disp2ea       = 19'bxx_0010_0000_0_0000_0010; // pass DISP
475
        parameter case_op       = 19'bxx_0010_1000_0_0000_0001; // SRC1 add to PC_ARCHI
476
        parameter read_byb      = 19'b00_1011_11xx_0_0000_0011; // read of SRC2 for Bit opcodes
477 11 ns32kum
        parameter exr11         = {2'b10  ,4'b1011,4'h0 ,9'h080};       // 2. access External with Mem.-Pointer + 4* Disp
478 9 ns32kum
        parameter adrcvtp       = 19'bxx_0010_0111_0_0000_0000; // for CVTP
479 11 ns32kum
        parameter addone        = 19'bxx_0010_0100_0_0000_0000; // for INDEX : SRC1 + SRC2 , simple Add without Flags
480 9 ns32kum
        parameter addind        = 19'bxx_0010_0100_0_0000_0011; // for INDEX : SRC1 + EA
481
        parameter src_x         = 7'hxx;
482
        parameter dest_x        = 6'hxx;
483
        parameter imme          = {1'b1,6'hxx};
484
        parameter F0            = 7'h20;
485
        parameter F0_h          = 7'h21;
486
        parameter w_F0          = 6'h20;
487
        parameter w_F0_h        = 6'h21;
488
        parameter temp_l        = 6'h3C;
489
        parameter temp_h        = 6'h3D;        // Second last place for 8B TEMP Register
490
        parameter temp_1        = 6'h3E;
491
        parameter rtmpl         = 7'h3C;
492
        parameter rtmph         = 7'h3D;
493
        parameter rtmp1         = 7'h3E;
494 14 ns32kum
        parameter op_mov        = {3'bx1x,8'h45};
495
        parameter op_adr        = {3'bx1x,8'h49};
496
        parameter op_addl       = {3'b01x,8'hB0};
497
        parameter op_addf       = {3'b11x,8'hB0};
498
        parameter op_mull       = {3'b01x,8'hBC};
499
        parameter op_mulf       = {3'b11x,8'hBC};
500 9 ns32kum
        parameter op_truf       = {3'b101,8'h9A};       // TRUNCFW for SCALBF
501
        parameter op_trul       = {3'b001,8'h9A};       // TRUNCLW for SCALBL
502 14 ns32kum
        parameter op_stpr       = {3'b11x,8'h54};       // Special-Op for String opcodes
503 9 ns32kum
        parameter op_lsh        = {3'b011,8'h65};       // EXT : shift to right : DOUBLE !
504
        parameter op_msk        = {3'b011,8'h80};       // reuse of EXT Opcode at INS !
505
        parameter op_mul        = {3'b011,8'h78};       // INDEX
506 14 ns32kum
        parameter op_rwv        = {3'bx1x,8'hE0};       // RDVAL+WRVAL
507 9 ns32kum
 
508
        always @(OPREG) // whether the Opcode is valid is decided in DECODER !
509 14 ns32kum
          casex (OPREG[13:0])
510 9 ns32kum
                14'bxx_xxxx_1111_1110 : op_code = {2'b01,OPREG[11:10],OPREG[8]};        // DOT/POLY/SCALB
511
                14'b00_0xxx_0000_1110 : op_code = 5'b1_0000;    // MOVS/CMPS
512
                14'b00_11xx_0000_1110 : op_code = 5'b1_0000;    // SKPS
513
                14'b00_0xxx_1100_1110 : op_code = 5'b1_0001;    // MOVM/CMPM
514
                14'bxx_xx10_0111_11xx : op_code = 5'b1_0010;    // JUMP/JSR
515
                14'bxx_x111_0111_11xx : op_code = 5'b1_0011;    // CASE
516
                14'bxx_xxxx_xx11_010x : op_code = 5'b1_0100;    // TBIT
517
                14'bxx_xxxx_xx11_0111 : op_code = 5'b1_0100;    // TBIT
518
                14'b0x_1xxx_0100_1110 : op_code = 5'b1_0100;    // CBIT/SBIT
519
                14'b11_10xx_0100_1110 : op_code = 5'b1_0100;    // IBIT
520
                14'b00_11xx_1100_1110 : op_code = 5'b1_0101;    // EXTS
521
                14'b10_x1xx_1100_1110 : op_code = 5'b1_0111;    // DEI/MEI
522
                14'bxx_x0xx_1110_1110 : op_code = 5'b1_1000;    // CHECK
523
                14'bxx_x0xx_0010_1110 : op_code = 5'b1_1010;    // EXT
524
                14'bxx_x0xx_1010_1110 : op_code = 5'b1_1011;    // INS
525
                14'b00_10xx_1100_1110 : op_code = 5'b1_1011;    // INSS, the same like INS !
526
                14'bxx_x0xx_0110_1110 : op_code = 5'b1_1100;    // CVTP
527
                14'bxx_x1xx_0010_1110 : op_code = 5'b1_1101;    // INDEX
528
                14'bxx_x000_0111_11xx : op_code = 5'b1_1110;    // CXPD
529
                14'b00_0xxx_0001_1110 : op_code = 5'b1_1111;    // RDVAL+WRVAL
530
                default                           : op_code = 5'b00_xxx;
531
          endcase
532
 
533
        always @(posedge BCLK) if (PHASE_0) op_reg_reg <= op_code;
534
        assign op_reg = PHASE_0 ? op_code : op_reg_reg;
535
 
536
        always @(PHRD1) // recode of States
537
          casex (PHRD1)
538
                 4'h5 : phsrc1 = 8'h51;
539
                 4'h6 : phsrc1 = 8'h52;
540
                 4'hB : phsrc1 = 8'h53; // ok, is in default ...
541
          default : phsrc1 = 8'h53;
542
          endcase
543
 
544
        assign get8b_s = (PHRD1 == 4'hB) ? 4'hC : 4'h0; // Special case 8B Immeadiate, is used in State 53
545
 
546
        always @(PHRD2) // recode of States
547
          casex (PHRD2)
548
                 4'h5 : phsrc2 = 8'h56;
549
                 4'h6 : phsrc2 = 8'h57;
550
                 4'hB : phsrc2 = 8'h58; // ok, is in default ...
551
          default : phsrc2 = 8'h58;
552
          endcase
553
 
554
        assign get8b_d = (PHRD2 == 4'hB) ? 4'hC : 4'h0; // Special case 8B Immeadiate, is used in State 58
555
 
556
        assign src_1l = {SRC_1[6:1],1'b0};
557 14 ns32kum
        assign src_2l = {SRC_2[6:1],~SRC_2[0]};  // needed only for DEI/MEI
558 9 ns32kum
        assign dest_2 =  SRC_2[5:0];
559
 
560
        assign phchk = {7'b0101_010,size_dw};   // Phase 54 or 55
561
 
562
        assign op_kust = {1'bx,OPERA[9:8],8'h7A};       // Special-Opcode for MOVM/CMPM
563
        assign op_bwd  = {1'bx,OPERA[9:8],8'h45};       // for CASE and Bit opcodes
564
 
565 11 ns32kum
        assign re_wr   = {EXR22[18:17],4'b0101,4'h0, 9'h003};   // REUSE Address : Write of rmw , top 2 Bits contain size
566 9 ns32kum
 
567 14 ns32kum
        always @(posedge BCLK) if (PHASE_0) ext_tos <= (OPREG[18:14] == 5'h17); // if TOS
568
        assign rexwr   = {EXR22[18:17],4'b0101,4'h0, ext_tos, 8'h03};   // REUSE Addresse : Write von rmw , only for EXT and EXTS !
569
 
570 9 ns32kum
        always @(posedge BCLK) tbit_flag <= ~OPERA[1];  // due to Timing ...
571
        always @(posedge BCLK) size_dw   <=  OPERA[9];
572
 
573
        always @(posedge BCLK) if (PHASE_0) chkreg <= {3'b000,OPREG[13:11]};    // for CHECK
574
        assign rd_reg = (PHASE_0) ? {4'b0,OPREG[13:11]} : {1'b0,chkreg};        // for read operation at EXT/INS
575
 
576
        always @(posedge BCLK) if (PHASE_0) bwdreg <= OPREG[9:8];               // only for INS/INSS !
577
        assign op_zext = {1'bx,(PHASE_0 ? OPREG[9:8] : bwdreg),8'h76};
578
 
579
        always @(posedge BCLK) if (PHASE_0) inss_flag <= OPREG[6];      // Difference INSS to INS
580
        assign imdi = inss_flag ? 4'h8 : 4'hE;  // read Immediate or Displacement
581
        assign exoffset = inss_flag ? 19'b10_1011_0000_0_0000_0011      // Read of SRC2 at INSS
582
                                                                : 19'b10_1011_1100_0_0000_0011; // Read of SRC1+Offset at EXT, SRC2+Offset at INS 
583
 
584
        always @(*)
585
          casex (op_reg)
586 11 ns32kum
                5'b1_0000 :     // MOVS Phase 0 : Entry 1. Pointer "in Page"-test prepare, 2. test for R0=0 , then jump to x'C0
587 9 ns32kum
                        begin
588 11 ns32kum
                          STATE_0  = {   addr_nop,8'h67, 7'h01, 7'h02, 1'b0,dest_x,op_stpr,     2'b00,2'b00,4'h0  };    // String-Pointer prepare
589 9 ns32kum
                          state_50 = dont_care;
590
                          state_53 = dont_care;
591
                          state_54 = dont_care;
592
                          state_55 = dont_care;
593
                          state_58 = dont_care;
594
                          state_59 = dont_care;
595
                          state_5A = dont_care;
596
                        end
597
                5'b1_0001 :     // MOVM Phase 0 : Entry with test for R0=0 , then jump to x'C0
598
                        begin
599
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
600
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
601
                          state_53 = {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b1,temp_h,op_adr,  2'b00,2'b00,NXRW2 };
602
                          state_54 = dont_care;
603
                          state_55 = dont_care;
604 11 ns32kum
                          state_58 = {   disp2ea, 8'h65, src_x, src_x, 1'b1,temp_1,op_adr,  2'b00,2'b00,4'b1110 };      // Read of DISP for count
605
                          state_59 = {   addr_nop,8'h67, rtmph, rtmp1, 1'b0,dest_x,op_stpr,     2'b00,2'b00,4'h0  };    // String-Pointer prepare
606 9 ns32kum
                          state_5A = dont_care;
607
                        end
608
                5'b1_0010 :     // JUMP/JSR
609
                        begin
610
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
611
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
612
                          state_53 = {   addr_nop,8'h66, src_x, src_x, 1'b1,temp_h,op_adr,  2'b00,2'b00,4'h0  };
613
                          state_54 = dont_care;
614
                          state_55 = dont_care;
615
                          state_58 = dont_care;
616
                          state_59 = dont_care;
617
                          state_5A = dont_care;
618
                        end
619
                5'b1_1110 :     // CXPD
620
                        begin
621
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
622
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
623
                          state_53 = {   addr_nop,8'h6B, imme,  src_x, 1'b1,temp_h,op_mov,  2'b00,2'b00,4'h0  };
624
                          state_54 = dont_care;
625
                          state_55 = dont_care;
626
                          state_58 = dont_care;
627
                          state_59 = dont_care;
628
                          state_5A = dont_care;
629
                        end
630
                5'b1_1111 :     // RDVAL+WRVAL
631
                        begin
632
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
633
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
634 11 ns32kum
                          state_53 = {   addr_nop,8'h00, src_x, src_x, 1'b0,dest_x,op_rwv,  2'b00,2'b10,4'h0  };        // LD_OUT set because of "F"
635 9 ns32kum
                          state_54 = dont_care;
636
                          state_55 = dont_care;
637
                          state_58 = dont_care;
638
                          state_59 = dont_care;
639
                          state_5A = dont_care;
640
                        end
641
                5'b1_0011 :     // CASE
642
                        begin
643
                          STATE_0  = ACCA[3] ?          // _M...
644
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
645
                                           : {   case_op, 8'h54, SRC_1, src_x, 1'b0,dest_x,op_bwd,      2'b00,2'b00,4'h0  };
646 11 ns32kum
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };        // only one operand in mem.
647 9 ns32kum
                          state_53 = {   case_op, 8'h54, imme,  src_x, 1'b0,dest_x,op_bwd,      2'b00,2'b00,4'h0  };
648
                          state_54 = {   addr_nop,8'h66, src_x, src_x, 1'b1,temp_h,op_adr,  2'b00,2'b00,4'h0  };
649
                          state_55 = dont_care;
650
                          state_58 = dont_care;
651
                          state_59 = dont_care;
652
                          state_5A = dont_care;
653
                        end
654 11 ns32kum
                5'b1_0100 : // all Bit opcodes with Bit in memory. RMW Test in Phase x'59 = Special case, otherwise x'58
655 9 ns32kum
                        begin
656
                          STATE_0  = ACCA[3] ?          // _M...
657
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
658
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
659
                          state_50 = ACCA[3] ?          // _M...
660
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
661
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
662
                          state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
663 11 ns32kum
                          state_54 = {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };        // here SRC1 => TEMP_H
664 9 ns32kum
                          state_55 = dont_care;
665 11 ns32kum
                          state_58 = {   read_byb,8'h59, rtmph, src_x, 1'b0,dest_x,op_bwd,      2'b00,2'b00,4'h1  };    // next read of Byte
666 9 ns32kum
                          state_59 = tbit_flag ?
667
                                                 {       addr_nop,8'h00, src_x, imme,  1'b0,dest_x,OPERA,       2'b00,2'b10,4'h0  }             // TBIT end
668 11 ns32kum
                                           : {   re_wr,   8'h27, src_x, imme,  1'b0,dest_x,OPERA,       2'b00,2'b10,4'h1  };    // CBIT/SBIT/IBIT end
669 9 ns32kum
                          state_5A = dont_care;
670
                        end
671
                5'b1_0101 : // EXTS : BASE Operand => TEMP, calculate address of Destination
672
                        begin
673
                          STATE_0  = ACCA[3] ?          // _M...
674
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
675
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
676
                          state_50 = ACCA[3] ?          // _M...
677
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
678
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
679
                          state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
680
                          state_54 = ACCA[1] ?
681 11 ns32kum
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }         // here Adr(DEST) => EA
682
                                           : {   addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h8  };    // 1 Byte Immediate read
683 9 ns32kum
                          state_55 = dont_care;
684 11 ns32kum
                          state_58 = {   addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h8  };    // 1 Byte Immediate read
685 9 ns32kum
                          state_59 = ACCA[1] ?          // _..M.
686 14 ns32kum
                                                 {       rexwr,   8'h27, imme,  rtmph, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h1  }             // result in memory
687 11 ns32kum
                                           : {   addr_nop,8'h00, imme,  rtmph, 1'b1,dest_2,OPERA,       2'b00,2'b00,4'h0  };    // result in Register
688 9 ns32kum
                          state_5A = dont_care;
689
                        end
690
                5'b1_1010 : // EXT : BASE Operand => TEMP, calculate address of Destination
691
                        begin
692
                          STATE_0  = ACCA[3] ?          // _M...
693
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
694
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
695
                          state_50 = ACCA[3] ?          // _M...
696
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
697
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
698 11 ns32kum
                          state_53 = {   addr_nop,8'h55, src_x, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h0  };    // Addr => EA Reg
699 9 ns32kum
                          state_54 = ACCA[1] ?
700
                                                  ( ACCA[3] ?
701
                                                    {addr_nop,8'h5A, imme,  src_x, 1'b1,temp_h,op_mov,  2'b00,2'b00,4'h0  }
702 11 ns32kum
                                                   :{ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }     )       // here Adr(DEST) => EA
703 9 ns32kum
                                           : {   addr_nop,8'h59, rd_reg,(ACCA[3] ? imme : rtmph),
704
                                                                                                                   1'b1,temp_h,op_lsh,  2'b00,2'b00,4'hE  };    // Displacement read
705 11 ns32kum
                          state_55 = {   exoffset,8'h54, rd_reg,src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h1  };    // Read Source, EA reuse
706
                          state_58 = {   addr_nop,8'h59, rd_reg,rtmph, 1'b1,temp_h,op_lsh,      2'b00,2'b00,4'hE  };    // Displacement read
707 9 ns32kum
                          state_59 = ACCA[1] ?          // _..M.
708 14 ns32kum
                                                 {       rexwr,   8'h27, src_x, rtmph, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h1  }             // result in memory
709 11 ns32kum
                                           : {   addr_nop,8'h00, src_x, rtmph, 1'b1,dest_2,OPERA,       2'b00,2'b00,4'h0  };    // result in Register
710
                          state_5A = {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,      2'b00,2'b00,NXRW2 };    // special case Mem-Mem
711 9 ns32kum
                        end
712 11 ns32kum
                5'b1_1011 : // INS/INSS : BASE Operand => TEMP, SRC2 read as Double ! RMW not tested (Phase x'6A) but uncritical
713 9 ns32kum
                        begin
714
                          STATE_0  = ACCA[3] ?          // _M...
715
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
716
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };
717
                          state_50 = ACCA[3] ?          // _M...
718
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
719
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };
720 11 ns32kum
                          state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };        // zext(SRC1) => TEMP
721 9 ns32kum
                          state_54 = ACCA[1] ?
722 11 ns32kum
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,      2'b00,2'b00,NXRW2 }             // here Adr(DEST) => EA
723
                                           : {   addr_nop,8'h5A, SRC_2, src_x, 1'b1,temp_l,op_mov,      2'b00,2'b00,imdi  };    // Imme./Disp. read
724
                          state_55 = {   exoffset,8'h6A, rd_reg,src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h1  };    // Read Source, EA reuse
725 9 ns32kum
                          state_58 = {   addr_nop,8'h55, src_x, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h0  };    // 
726
                          state_59 = ACCA[1] ?          // _..M.
727
                                                 {       re_wr,   8'h27, rtmph, rtmpl, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h1  }             // result in memory
728 11 ns32kum
                                           : {   addr_nop,8'h00, rtmph, rtmpl, 1'b1,dest_2,OPERA,       2'b00,2'b00,4'h0  };    // result in Register
729
                          state_5A = {   addr_nop,8'h68, imme,  src_x, 1'b1,temp_1,op_msk,      2'b00,2'b00,4'h0  };    // Mask generate
730 9 ns32kum
                        end
731
                5'b1_1101 : // INDEX : 
732
                        begin
733
                          STATE_0  = ACCA[3] ?          // _M...
734
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
735
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };
736
                          state_50 = ACCA[3] ?          // _M...
737
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
738
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };
739 11 ns32kum
                          state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };        // zext(SRC1) => TEMP_H
740 9 ns32kum
                          state_54 = ACCA[1] ?
741 11 ns32kum
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,      2'b00,2'b00,NXRW2 }             // zext(SRC2) => TEMP_L
742 9 ns32kum
                                           : {   addr_nop,8'h55, SRC_2, src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0  };
743 11 ns32kum
                          state_55 = {   addr_nop,8'h5A, rd_reg,rtmph, 1'b1,temp_h,op_mul,      2'b00,2'b00,4'h0  };    // Multiplication
744 9 ns32kum
                          state_58 = {   addr_nop,8'h55, imme,  src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0  };        // 
745 11 ns32kum
                          state_59 = {   addind,  8'h60, rtmpl, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h0  };    // Add of Index in EA
746
                          state_5A = {   addone,  8'h59, rd_reg,rtmph, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h0  };    // Add of EA (=+1)
747 9 ns32kum
                        end
748
                5'b1_0111 :     // DEI + MEI , both read 8B from DEST ! RMW critical !
749
                        begin
750
                          STATE_0  = ACCA[3] ?          // _M...
751
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
752
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
753
                          state_50 = ACCA[3] ?          // _M...
754
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
755
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
756
                          state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
757
                          state_54 = ACCA[1] ?
758 11 ns32kum
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }         // here SRC1 => TEMP_H
759
                                           : {   addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_x,OPERA,       2'b01,2'b00,4'h0  };    // 1. part of Register
760 9 ns32kum
                          state_55 = dont_care;
761
                          state_58 = size_dw ?
762 11 ns32kum
                                                 {       addr_nop,8'h59, rtmph, imme,  1'b0,dest_x,OPERA,       2'b01,2'b00,4'h0  }             // D needs 2 accesses
763
                                           : {   addr_nop,8'h1F, rtmph, imme,  1'b0,dest_x,OPERA,       2'b11,2'b00,4'h0  };    // B+W start at once
764 9 ns32kum
                          state_59 = {   addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l),                                                      // SRC2 = memory or Reg
765
                                                                                                           ~ACCA[1],dest_2,OPERA,       2'b10,2'b00,4'h0  };
766
                          state_5A = dont_care;
767
                        end
768
                5'b1_1000 :     // CHECK
769
                        begin
770 11 ns32kum
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };        // No Register !
771 9 ns32kum
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
772 11 ns32kum
                          state_53 = {   addr_nop,phchk, imme,  src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };    // No Immediate !
773 9 ns32kum
                          state_54 = ACCA[1] ?
774
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }
775
                                           : (  size_dw ?
776 11 ns32kum
                                                        {addr_nop,8'h5A, SRC_2, rtmpl, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h0  }             // Upper Bound - pointer
777 9 ns32kum
                                                  : {addr_nop,8'h00, rtmph, SRC_2, 1'b1,chkreg,OPERA,   2'b00,2'b10,4'h0  } );
778
                          state_55 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_l,op_mov,      2'b00,2'b00,4'h0  };
779
                          state_58 = size_dw ?
780 11 ns32kum
                                                 {       addr_nop,8'h59, imme,  src_x, 1'b1,temp_1,op_mov,      2'b00,2'b00,4'h0  }             // here SRC2 => TEMP_1
781 9 ns32kum
                                           : {   addr_nop,8'h00, rtmph, imme,  1'b1,chkreg,OPERA,       2'b00,2'b10,4'h0  };
782 11 ns32kum
                          state_59 = {   addr_nop,8'h5A, rtmp1, rtmpl, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h0  };    // Upper Bound - pointer
783 9 ns32kum
                          state_5A = {   addr_nop,8'h00, rtmph, (ACCA[1] ? rtmp1 : SRC_2),
784
                                                                                                                   1'b1,chkreg,OPERA,   2'b00,2'b10,4'h0  };    // pointer - Lower Bound
785
                        end
786
                5'b1_1100 :     // CVTP
787
                        begin
788 11 ns32kum
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };        // Address
789 9 ns32kum
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
790
                          state_53 = {   addr_nop,8'h54, src_x, src_x, 1'b1,temp_h,op_adr,      2'b00,2'b00,4'h0  };
791 11 ns32kum
                          state_54 = {   adrcvtp, 8'h73, rtmph, rd_reg,1'b0,dest_x,op_mov,  2'b00,2'b00,4'h0  };        // 8*TEMP+Offset
792 9 ns32kum
                          state_55 = dont_care;
793
                          state_58 = dont_care;
794
                          state_59 = dont_care;
795
                          state_5A = dont_care;
796
                        end
797
                5'b01_000 :     // SCALBL : RMW critical !
798
                        begin
799
                          STATE_0  = ACCA[3] ?          // _M...
800
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
801
                                           : {   addr_nop,8'h54, SRC_1, src_1l,1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0  };
802
                          state_50 = ACCA[3] ?          // _M...
803
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
804
                                           : {   addr_nop,8'h54, SRC_1, src_1l,1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0  };
805
                          state_53 = {   addr_nop,8'h55, imme,  src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,get8b_s };
806
                          state_54 = ACCA[1] ?
807
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_trul, 2'b00,2'b00,NXRW2 }
808
                                           : {   addr_nop,8'h5A, src_x, src_x, 1'b0,temp_h,op_trul,     2'b00,2'b00,4'h0  };
809 11 ns32kum
                          state_55 = {   addr_nop,8'h54, rtmph, imme,  1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0  };        // 2. half of external SRC1
810 9 ns32kum
                          state_58 = {   addr_nop,8'h59, rtmph, imme,  1'b0,dest_2,OPERA,       2'b01,2'b00,4'h0  };
811
                          state_59 = {   addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l),
812
                                                                                                           ~ACCA[1],dest_2,OPERA,       2'b10,2'b00,4'h0  };
813 11 ns32kum
                          state_5A = {   addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_2,OPERA,       2'b01,2'b00,4'h0  };    // empty cycle for TRUNC => TEMP !
814 9 ns32kum
                        end
815
                5'b01_001 :     // SCALBF : RMW critical !
816
                        begin
817
                          STATE_0  = ACCA[3] ?          // _M...
818
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
819
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0  };
820
                          state_50 = ACCA[3] ?          // _M...
821
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
822
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0  };
823
                          state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0  };
824
                          state_54 = ACCA[1] ?
825
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }
826
                                           : {   addr_nop,8'h1F, rtmph, SRC_2, 1'b1,dest_2,OPERA,       2'b11,2'b00,4'h0  };
827
                          state_55 = dont_care;
828
                          state_58 = {   addr_nop,8'h1F, rtmph, imme,  1'b0,dest_x,OPERA,       2'b11,2'b00,4'h0  };
829
                          state_59 = dont_care;
830
                          state_5A = dont_care;
831
                        end
832
                5'b01_100 :     // POLYL
833
                        begin
834
                          STATE_0  = ACCA[3] ?          // _M...
835
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
836
                                           : {   addr_nop,8'h54, SRC_1, F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0  };
837
                          state_50 = ACCA[3] ?          // _M...
838
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
839
                                           : {   addr_nop,8'h54, SRC_1, F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0  };
840
                          state_53 = {   addr_nop,8'h54, imme,  F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,get8b_s };
841
                          state_54 = {   addr_nop,8'h64, (ACCA[3] ? imme : src_1l),
842
                                                                                                        F0,    1'b1,temp_h,op_mull, 2'b10,2'b00,4'h0  };
843
                          state_55 = dont_care;
844
                          state_58 = {   addr_nop,8'h59, imme,  rtmph, 1'b0,dest_x,op_addl, 2'b01,2'b00,get8b_d };
845
                          state_59 = {   addr_nop,8'h62, (ACCA[1] ? imme : src_2l),
846
                                                                                                        rtmpl, 1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0  };
847
                          state_5A = dont_care;
848
                        end
849
                5'b01_101 :     // POLYF
850
                        begin
851
                          STATE_0  = ACCA[3] ?          // _M...
852
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
853
                                           : {   addr_nop,8'h54, SRC_1, F0,    1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };
854
                          state_50 = ACCA[3] ?          // _M...
855
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
856
                                           : {   addr_nop,8'h54, SRC_1, F0,    1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };
857
                          state_53 = {   addr_nop,8'h54, imme,  F0,    1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };
858
                          state_54 = ACCA[1] ?
859
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }
860
                                           : {   addr_nop,8'h00, rtmph, SRC_2, 1'b1,w_F0  ,op_addf, 2'b00,2'b00,4'h0  };
861
                          state_55 = dont_care;
862
                          state_58 = {   addr_nop,8'h00, rtmph, imme,  1'b1,w_F0  ,op_addf, 2'b00,2'b00,4'h0  };
863
                          state_59 = dont_care;
864
                          state_5A = dont_care;
865
                        end
866
                5'b01_110 :     // DOTL
867
                        begin
868
                          STATE_0  = (~ACCA[3] & ~ACCA[1]) ?            // _R.R.
869
                                                 {       addr_nop,8'h59, SRC_1, SRC_2, 1'b0,dest_x,op_mull, 2'b01,2'b00,4'h0  }
870
                                           : (  ACCA[3] ?               // _M...
871
                                                    {ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
872
                                                  : {ADRD2,   phsrc2,src_x, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 } );
873
                          state_50 = ACCA[3] ?          // _M...
874
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
875
                                           : {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };
876
                          state_53 = ACCA[1] ?          // _..M.
877
                                                 {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_mov,  2'b00,2'b00,get8b_s }
878
                                           : {   addr_nop,8'h59, imme,  SRC_2, 1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_s };
879
                          state_54 = {   addr_nop,8'h55, imme,  src_x, 1'b1,temp_l,op_mov,  2'b00,2'b00,4'h0  };
880
                          state_55 = {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };
881
                          state_58 = {   addr_nop,8'h59, (ACCA[3] ? rtmph : SRC_1),             //_M...
882
                                                                                                        imme,  1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_d };
883 11 ns32kum
                          state_59 = {   addr_nop,8'h5A, (ACCA[3] ? (ACCA[1] ? rtmpl : imme) : src_1l), (ACCA[1] ? imme : src_2l),
884 9 ns32kum
                                                                                                                   1'b1,temp_h,op_mull, 2'b10,2'b00,4'h0  };
885
                          state_5A = {   addr_nop,8'h61, rtmph, F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0  };
886
                        end
887
                5'b01_111 :     // DOTF
888
                        begin
889
                          STATE_0  = (~ACCA[3] & ~ACCA[1]) ?            // _R.R.
890
                                                 {       addr_nop,8'h63, SRC_1 ,SRC_2 ,1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  }         // opera = MULF
891
                                           : (  ACCA[3] ?               // _M...
892
                                                    {ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
893
                                                  : {ADRD2,   phsrc2,src_x, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 } );
894
                          state_50 = ACCA[3] ?          // _M...
895
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
896
                                           : {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };
897
                          state_53 = ACCA[1] ?          // _..M.
898
                                                 {   addr_nop,8'h55, imme,  src_x, 1'b1,temp_h,op_mov,  2'b00,2'b00,4'h0  }
899
                                           : {   addr_nop,8'h63, imme,  SRC_2 ,1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };
900
                          state_54 = dont_care;
901
                          state_55 = {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };
902
                          state_58 = {   addr_nop,8'h63, (ACCA[3] ? rtmph : SRC_1),             //_M...
903
                                                                                                        imme,  1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };
904
                          state_59 = dont_care;
905
                          state_5A = dont_care;
906
                        end
907
                default
908
                        begin
909
                          STATE_0  = dont_care;
910
                          state_50 = dont_care;
911
                          state_53 = dont_care;
912
                          state_54 = dont_care;
913
                          state_55 = dont_care;
914
                          state_58 = dont_care;
915
                          state_59 = dont_care;
916
                          state_5A = dont_care;
917
                        end
918
                endcase
919
 
920
        always @(*)
921
          casex (PHASE)
922
                 4'h0 : STATE_GROUP_50 = state_50;
923
                // Phase 51 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1
924 11 ns32kum
                 4'h1 : STATE_GROUP_50 = {exr11,   8'h52, src_x,imme , 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'b1111};
925 9 ns32kum
                // Phase 52 : Memory-Pointer for Memory Relative and last access External
926 11 ns32kum
                 4'h2 : STATE_GROUP_50 = {EXR12,   8'h53, IRRW1,imme , 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'b1111};  // atys[0] !
927 9 ns32kum
                 4'h3 : STATE_GROUP_50 = state_53;
928
                 4'h4 : STATE_GROUP_50 = state_54;
929
                 4'h5 : STATE_GROUP_50 = state_55;
930
                // Phase 56 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1
931 11 ns32kum
                 4'h6 : STATE_GROUP_50 = {exr11,   8'h57, src_x,imme , 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'b1111};
932 9 ns32kum
                // Phase 57 : Memory-Pointer for Memory Relative and last access External
933 11 ns32kum
                 4'h7 : STATE_GROUP_50 = {EXR22,   8'h58, IRRW2,imme , 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'b1111};  // atyd[0] !
934 9 ns32kum
                 4'h8 : STATE_GROUP_50 = state_58;
935
                 4'h9 : STATE_GROUP_50 = state_59;
936
                 4'hA : STATE_GROUP_50 = state_5A;
937
          default : STATE_GROUP_50 = dont_care;
938
          endcase
939
 
940
        always @(*)
941
          casex (PHASE)
942 11 ns32kum
                 4'h0 : STATE_GROUP_60 = {       addr_nop,8'h00, src_x, src_x, 1'b1,chkreg,op_adr,  2'b00,2'b00,4'h0  };        // for INDEX
943
                 4'h1 : STATE_GROUP_60 = {       addr_nop,8'h62, rtmpl, F0,    1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0  };        // for DOTL
944
                 4'h2 : STATE_GROUP_60 = {       addr_nop,8'h00, src_x, src_x, 1'b0,w_F0_h,op_addl, 2'b00,2'b00,4'h0  };        // for DOTL & POLYL !
945
                 4'h3 : STATE_GROUP_60 = {       addr_nop,8'h00, rtmph, F0,    1'b1,w_F0,  op_addf, 2'b00,2'b00,4'h0  };        // for DOTF
946 9 ns32kum
                 4'h4 : STATE_GROUP_60 = ACCA[1] ?      // ..M.
947
                                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,temp_h,op_mull, 2'b00,2'b00,NXRW2 }
948
                                                           : {   addr_nop,8'h59, SRC_2, rtmph, 1'b0,temp_h,op_addl, 2'b01,2'b00,4'h0  };        // for POLYL
949 11 ns32kum
                 4'h5 : STATE_GROUP_60 = {       addr_nop,8'h59, src_x, src_x, 1'b1,temp_l,op_kust, 2'b00,2'b00,4'h0  };        // for MOVM/CMPM
950
                 4'h6 : STATE_GROUP_60 = {       addr_nop,8'h01, rtmph, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h0  };    // for JUMP/JSR/CASE
951
                 4'h7 : STATE_GROUP_60 = {       addr_nop,8'hC0, (op_reg_reg[0] ? rtmpl : 7'h00),                                                        // Jump to String execution
952 9 ns32kum
                                                                                                                        src_x, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h0  };    // LD_OUT set, CMPS F-Flag
953
                // for INS                                                                                                              
954 11 ns32kum
                 4'h8 : STATE_GROUP_60 = {       addr_nop,8'h69, rd_reg,rtmph, 1'b1,temp_h,op_lsh,      2'b00,2'b00,4'h0  };    // SRC1 shift
955
                 4'h9 : STATE_GROUP_60 = {       addr_nop,8'h59, rd_reg,rtmp1, 1'b0,dest_x,op_lsh,      2'b00,2'b00,4'h0  };    // Mask shift
956
                 4'hA : STATE_GROUP_60 = {       addr_nop,8'h5A, imme,  src_x, 1'b1,temp_l,op_mov,      2'b00,2'b00,imdi  };    // Imme./Disp. read
957 9 ns32kum
                // for CXPD, this State is decoded explicitly in DECODER
958 11 ns32kum
                 4'hB : STATE_GROUP_60 = {       addr_nop,8'h39, imme,  src_x, 1'b1,temp_l,op_mov,      2'b00,2'b00,4'h0  };    // pass PC
959 9 ns32kum
          default : STATE_GROUP_60 = dont_care;
960
          endcase
961
 
962
endmodule

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