OpenCores
URL https://opencores.org/ocsvn/m32632/m32632/trunk

Subversion Repositories m32632

[/] [m32632/] [trunk/] [rtl/] [STEUER_MISC.v] - Blame information for rev 23

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 ns32kum
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6 23 ns32kum
//      Filename:       STEUER_MISC.v
7
//      Version:        2.0
8
//      History:        1.0 first release of 30 Mai 2015
9
//      Date:           14 August 2016
10 9 ns32kum
//
11 14 ns32kum
// Copyright (C) 2016 Udo Moeller
12 9 ns32kum
// 
13
// This source file may be used and distributed without 
14
// restriction provided that this copyright statement is not 
15
// removed from the file and that any derivative work contains 
16
// the original copyright notice and the associated disclaimer.
17
// 
18
// This source file is free software; you can redistribute it 
19
// and/or modify it under the terms of the GNU Lesser General 
20
// Public License as published by the Free Software Foundation;
21
// either version 2.1 of the License, or (at your option) any 
22
// later version. 
23
// 
24
// This source is distributed in the hope that it will be 
25
// useful, but WITHOUT ANY WARRANTY; without even the implied 
26
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
27
// PURPOSE. See the GNU Lesser General Public License for more 
28
// details. 
29
// 
30
// You should have received a copy of the GNU Lesser General 
31
// Public License along with this source; if not, download it 
32
// from http://www.opencores.org/lgpl.shtml 
33
// 
34
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
35
//
36
//      Modules contained in this file:
37
//      1. OPDEC_REG    Central Instruction Register
38
//      2. PROG_COUNTER Program Counters
39
//      3. REG_LIST             Register List Evaluation
40
//      4. ILL_UNDEF    Illegal and Undefined Opcodes Detection
41
//      5. GRUPPE_2             Decoder and State Machine for GRUPPE_2 Opcodes
42
//
43 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
44 9 ns32kum
 
45 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
46 9 ns32kum
//
47
//      1. OPDEC_REG    Central Instruction Register
48
//
49 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
50
module OPDEC_REG ( BCLK, BRESET, NEW, ACC_STAT, PROT_ERROR, ALSB, USED, IC_DIN, IC_INIT, DC_INIT, Y_INIT, RESTART, STOP_IC,
51 9 ns32kum
                                   OPREG, ANZ_VAL, IC_READ, NEW_PC, NEXT_ADR, DATA_HOLD, ABORT, IC_TEX, INIT_DONE);
52
 
53
        input                   BCLK,BRESET;
54
        input                   NEW;            // a program jump took place
55
        input    [3:0]   ACC_STAT;       // ICACHE signals data is available or Abort
56
        input                   PROT_ERROR;     // comes direct from ICACHE
57
        input    [1:0]   ALSB;           // lower addressbits of access address to ICACHE
58
        input    [2:0]   USED;           // Message from DECODER how many bytes were used
59
        input   [31:0]   IC_DIN;         // ICACHE Data
60
        input                   IC_INIT,DC_INIT,Y_INIT; // Initialising or new setting is running
61
        input                   RESTART;        // "Break" of Instruction Pipeline - set up new i.e. after load of PSR
62
        input                   STOP_IC;        // For LMR and CINV
63
 
64
        output  [55:0]   OPREG;          // this is the Central Opcode Decode Register, length = 7 bytes
65
        output   [2:0]   ANZ_VAL;
66
        output                  IC_READ;
67
        output                  NEW_PC;
68
        output                  NEXT_ADR;
69
        output                  DATA_HOLD;
70
        output                  ABORT;
71
        output   [2:0]   IC_TEX;
72
        output                  INIT_DONE;
73
 
74
        reg             [55:0]   OPREG;
75
        reg              [2:0]   ANZ_VAL;
76
        reg                             IC_READ;
77
        reg                             ABORT;
78
        reg                             abort_flag;
79
        reg              [2:0]   IC_TEX;
80
        reg             [55:0]   data_to_ri;
81
        reg                             old_init;
82
        reg                             pre_new;
83
        reg                             new_reg;
84
        reg                             nseq_flag;
85
        reg                             stop_init;
86
 
87
        wire     [2:0]   new_anz;
88
        wire                    new_restart;
89
        wire                    acc_err,acc_ok,acc_ende;
90
 
91
        // ++++++++++++++++++++  Evaluation of ACC_STAT from Instructioncache  ++++++++++++++++++++++++++++
92
 
93
        // ACC_STAT[3:0] : PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK
94
 
95
        assign acc_err = ACC_STAT[3] | ACC_STAT[1] | PROT_ERROR;
96
        assign acc_ok  = ACC_STAT[0];
97
 
98
        always @(posedge BCLK or negedge BRESET)        // is kept until DECODER really needs the data !
99
                if (!BRESET) ABORT <= 1'b0;
100
                  else ABORT <=  (acc_err & ~(new_restart | pre_new)) | (ABORT & ~NEW_PC);
101
 
102 11 ns32kum
        always @(posedge BCLK) if (acc_err) IC_TEX <= (ACC_STAT[3] | PROT_ERROR) ? {nseq_flag,2'b11} : {nseq_flag,~ACC_STAT[2],ACC_STAT[2]};
103 9 ns32kum
 
104
        always @(posedge BCLK) nseq_flag <= NEW_PC | (nseq_flag & ~acc_ok);     // for MMU Status Register
105
 
106
        always @(posedge BCLK) abort_flag <= acc_err;
107 11 ns32kum
        assign acc_ende = ~IC_READ | acc_ok | abort_flag;       // abort_flag one cycle later is ok ! If no ICache access always end
108 9 ns32kum
 
109
        assign new_restart = NEW | RESTART;     // They are pulses
110
 
111
        // Branch work out : NEW/RESTART notice if access still not ended
112
        always @(posedge BCLK) pre_new <= (new_restart & ~acc_ende) | (pre_new & ~acc_ende & BRESET);
113
 
114
        assign NEW_PC = (new_restart | pre_new) & acc_ende;     // At the end of access geenerate new address !
115
 
116 11 ns32kum
        // There are 2 "NEW/RESTART" : "new_restart" combinatorical out of DECODER, "pre_new" out of Register
117 9 ns32kum
        always @(posedge BCLK) new_reg <= new_restart | pre_new | (new_reg & ~acc_ende & BRESET);
118
 
119
        always @(USED or OPREG) // Data first shift to the right
120
                case (USED)
121
                  3'b000 : data_to_ri = OPREG;
122
                  3'b001 : data_to_ri =               { 8'hxx, OPREG[55:8]};
123
                  3'b010 : data_to_ri =             {16'hxxxx,OPREG[55:16]};
124
                  3'b011 : data_to_ri =          {24'hxx_xxxx,OPREG[55:24]};
125
                  3'b100 : data_to_ri =        {32'hxxxx_xxxx,OPREG[55:32]};
126
                  3'b101 : data_to_ri =     {40'hxx_xxxx_xxxx,OPREG[55:40]};
127
                  3'b110 : data_to_ri =   {48'hxxxx_xxxx_xxxx,OPREG[55:48]};
128
                  3'b111 : data_to_ri = 56'hxx_xxxx_xxxx_xxxx;
129
                endcase
130
 
131
        assign new_anz = ANZ_VAL - USED;
132
 
133
        always @(posedge BCLK)
134
                casex ({new_reg,acc_ok,ALSB,new_anz})
135
                  7'b1_100_xxx : OPREG <=        {24'hxx_xxxx,IC_DIN};
136
                  7'b1_101_xxx : OPREG <=      {32'hxxxx_xxxx,IC_DIN[31:8]};
137
                  7'b1_110_xxx : OPREG <=   {40'hxx_xxxx_xxxx,IC_DIN[31:16]};
138
                  7'b1_111_xxx : OPREG <= {48'hxxxx_xxxx_xxxx,IC_DIN[31:24]};
139
                  7'b0_0xx_xxx : OPREG <= data_to_ri;
140
                  7'b0_1xx_000 : OPREG <= {24'hxx_xxxx,IC_DIN};
141
                  7'b0_1xx_001 : OPREG <= {   16'hxxxx,IC_DIN, data_to_ri[7:0]};
142
                  7'b0_1xx_010 : OPREG <= {      8'hxx,IC_DIN,data_to_ri[15:0]};
143
                  7'b0_1xx_011 : OPREG <= {            IC_DIN,data_to_ri[23:0]};
144
                  7'b0_1xx_1xx : OPREG <= data_to_ri;
145
                endcase
146
 
147
        always @(posedge BCLK or negedge BRESET)
148
                if (!BRESET) ANZ_VAL <= 3'b000;
149
                  else
150
                        casex ({new_restart,new_reg,acc_ok,new_anz[2]})
151
                          4'b1x_x_x : ANZ_VAL <= 3'b000;        // hard setting to 0
152
                          4'b01_0_x : ANZ_VAL <= 3'b000;
153
                          4'b01_1_x : ANZ_VAL <= pre_new ? 3'b000 : 3'b100 - {1'b0,ALSB};
154
                          4'b00_0_x : ANZ_VAL <= new_anz;
155
                          4'b00_1_0 : ANZ_VAL <= new_anz + 3'b100;
156
                          4'b00_1_1 : ANZ_VAL <= new_anz;
157
                        endcase
158
 
159 11 ns32kum
        assign NEXT_ADR = new_reg ? (acc_ok & ~pre_new) : (acc_ok & ~new_anz[2]);       // switches MUX at PC resp. ICACHE
160 9 ns32kum
 
161
        // Instruction CACHE Control : READ is coming after all INITs are done
162
 
163
        always @(posedge BCLK) old_init <= IC_INIT | DC_INIT | Y_INIT;
164
 
165
        assign INIT_DONE = old_init & ~IC_INIT & ~DC_INIT;
166
 
167
        always @(posedge BCLK or negedge BRESET)
168
                if (!BRESET) stop_init <= 1'b0;
169
                        else stop_init <= stop_init | IC_READ;
170
 
171 11 ns32kum
        // The INIT_DONE should come after Reset. But it comes too at LMR PTB therefore extra enable after Reset !
172 9 ns32kum
        always @(posedge BCLK or negedge BRESET)
173
                if (!BRESET) IC_READ <= 1'b0;
174
                        else IC_READ <= (IC_READ & ~acc_err & ~(STOP_IC & acc_ok)) | NEW_PC | (INIT_DONE & ~stop_init);
175
 
176
        // The Opcode-Register can not store the data : keep them in ICACHE at IO-access
177
        assign DATA_HOLD = ~new_restart & ~new_reg & acc_ok & new_anz[2];
178
 
179
endmodule
180
 
181 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
182 9 ns32kum
//
183
//      2. PROG_COUNTER Program Counters
184
//
185 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
186
module PROG_COUNTER ( BCLK, BRESET, NEW, LOAD_PC, NEW_PC, NEXT_ADR, NEXT_PCA, DISP, PC_NEW, USED, USER, SAVE_PC, FPU_TRAP,
187 9 ns32kum
                                          ADIVAR, PC_ARCHI, PC_ICACHE, PC_SAVE, ALSB, IC_USER);
188
 
189
        input                   BCLK,BRESET;
190
        input                   NEW;
191
        input                   LOAD_PC;
192
        input                   NEW_PC;
193
        input                   NEXT_ADR;
194
        input                   NEXT_PCA;
195
        input   [31:0]   DISP;
196
        input   [31:0]   PC_NEW;
197
        input    [2:0]   USED;
198
        input                   USER;
199
        input                   SAVE_PC;
200
        input                   FPU_TRAP;
201
        input                   ADIVAR;
202
 
203
        output  [31:0]   PC_ARCHI;       // goes to Datapath
204
        output  [31:0]   PC_ICACHE;
205
        output  [31:0]   PC_SAVE;        // is the return address
206
        output   [1:0]   ALSB;
207
        output                  IC_USER;
208
 
209
        reg             [31:0]   PC_ARCHI;
210
        reg             [31:0]   pc_adduse;
211
        reg             [31:0]   pc_ic_reg;
212
        reg             [31:0]   fpu_trap_pc;
213
        reg                             IC_USER;
214
 
215 23 ns32kum
        wire    [31:0]   branch,pc_jump,pc_icache_i;
216 9 ns32kum
 
217
        assign PC_SAVE = pc_adduse + {29'h0,USED};
218
        assign branch  = PC_ARCHI + DISP;
219
 
220
        assign pc_jump = LOAD_PC ? PC_NEW : branch;
221
 
222
        always @(posedge BCLK or negedge BRESET)
223
                if (!BRESET) pc_adduse <= 32'h0;
224
                  else
225 23 ns32kum
                        pc_adduse <= NEW ? pc_jump : PC_SAVE;   // Only at NEW is the DISP correct !
226 9 ns32kum
 
227
        // The Architectur - PC : Address mode "Programm Memory"-relativ
228
        // no BRESET because NEXT_PCA is immediately valid
229
        always @(posedge BCLK)
230
                if (FPU_TRAP) PC_ARCHI <= fpu_trap_pc;  // go back !
231
                  else
232
                        if (NEXT_PCA) PC_ARCHI <= pc_adduse;
233
 
234
        always @(posedge BCLK) if (SAVE_PC) fpu_trap_pc <= PC_ARCHI;    // Special storage for PC for FPU Trap
235
 
236
        always @(posedge BCLK or negedge BRESET)
237
                if (!BRESET) pc_ic_reg <= 32'h0;
238
                  else
239
                        pc_ic_reg <= pc_icache_i;
240
 
241 11 ns32kum
        // NEW is only one cycle long - but in pc_adduse is the PC stored when ACC_OK is not there and therefore NEW_PC
242 9 ns32kum
        // is used to initiate a new access in ICACHE
243 11 ns32kum
        assign pc_icache_i = NEW_PC ? (NEW ? pc_jump : pc_adduse) : (NEXT_ADR ? ({pc_ic_reg[31:2],2'b00} + 32'h0000_0004) : pc_ic_reg);
244 9 ns32kum
 
245
        // This MUX is extra for LMR IVAR,... and CINV build in
246
        assign PC_ICACHE = {(ADIVAR ? PC_NEW[31:4] : pc_icache_i[31:4]),pc_icache_i[3:0]};
247
 
248
        assign ALSB = pc_ic_reg[1:0];    // for OPDEC_REG
249
 
250
        // The IC_USER flag is allowed to switch synchronously with one cycle delay to PC_ICACHE
251
        always @(posedge BCLK or negedge BRESET)
252
                if (!BRESET) IC_USER <= 1'b0;
253
                  else
254
                        if (NEW_PC) IC_USER <= USER;
255
 
256
endmodule
257
 
258 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
259 9 ns32kum
//
260
//      3. REG_LIST             Register List Evaluation
261
//
262 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
263 9 ns32kum
module REG_LIST ( DIN, IPOS, INIT, OPOS, VALID);
264
 
265
        // Detects set bits in register list for SAVE/RESTORE & ENTER/EXIT
266
 
267
        input    [7:0]   DIN;
268
        input    [2:0]   IPOS;
269
        input                   INIT;
270
        output   [2:0]   OPOS;
271
        output                  VALID;
272
 
273
        reg              [7:1]  filter;
274
        wire     [7:0]   mdat_0;
275
        wire     [3:0]   mdat_1;
276
 
277
        always @(IPOS or DIN)
278
                case (IPOS)
279
                  3'd0 : filter =  DIN[7:1];
280
                  3'd1 : filter = {DIN[7:2],1'b0};
281
                  3'd2 : filter = {DIN[7:3],2'b0};
282
                  3'd3 : filter = {DIN[7:4],3'b0};
283
                  3'd4 : filter = {DIN[7:5],4'b0};
284
                  3'd5 : filter = {DIN[7:6],5'b0};
285
                  3'd6 : filter = {DIN[7]  ,6'b0};
286
                  3'd7 : filter =           7'b0;
287
                endcase
288
 
289
        assign mdat_0  = INIT ? DIN : {filter,1'b0};
290
        assign OPOS[2] = (mdat_0[3:0] == 4'h0);
291
        assign mdat_1  = OPOS[2] ? mdat_0[7:4] : mdat_0[3:0];
292 23 ns32kum
        assign OPOS[1] =   (mdat_1[1:0] == 2'b00);
293
        assign OPOS[0] = ~((mdat_1[2:1] == 2'b10) | mdat_1[0]);
294
        assign VALID   =   (mdat_1 != 4'b0000);
295 9 ns32kum
 
296
endmodule
297
 
298 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
299 9 ns32kum
//
300
//      4. ILL_UNDEF    Illegal and Undefined Opcodes Detection
301
//
302 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
303 9 ns32kum
module ILL_UNDEF (OPREG, ANZ_VAL, USER, CFG, ILL, UNDEF );
304
 
305
        input   [23:0]   OPREG;
306
        input    [2:0]   ANZ_VAL;
307
        input    [3:1]  CFG;            // 3=CUSTOM,2=MMU,1=FPU
308
        input                   USER;
309
 
310
        output  reg             ILL;
311
        output                  UNDEF;
312
 
313
        reg                             undef_opc;
314
        reg                             undef_am;
315
        reg                             undef_im;
316
 
317
        wire     [2:0]   valid;
318
        wire                    gen12,gen22,gen13,gen23;
319
        wire                    igen12,igen22,igen13,igen23;
320
        wire                    lsbes;
321
 
322
        parameter udef_amode = 5'b10011;        // Undefined Addressing Mode
323
        parameter imode          = 5'b10100;    // Immediate Addressing Mode 
324
 
325
        // [2]= minimum 3, [1]= minimum 2, [0]=minimum 1
326 11 ns32kum
        assign valid = {(ANZ_VAL[2] | (ANZ_VAL[1:0] == 2'b11)),(ANZ_VAL[2:1] != 2'b00),(ANZ_VAL != 3'b000)};
327 9 ns32kum
        assign lsbes = (OPREG[1:0] == 2'b10);    // Tag of all 3 Byte opcodes
328
 
329
        // +++++++++++++++++++++++++  Detect illegale opcodes  +++++++++++++++++++
330
 
331
        always @(OPREG or lsbes or valid or USER)
332
                casex ({valid[2:1],OPREG[13:2],lsbes})
333
                  15'bx1_xx_x000_1x10_11_0 : ILL = USER;        // SPRi/LPRi DCR
334
                  15'bx1_xx_x001_xx10_11_0 : ILL = USER;        // SPRi/LPRi BPC/DSR
335
                  15'bx1_xx_xx10_xx10_11_0 : ILL = USER;        // SPRi/LPRi CAR/CFG/PSR
336
                  15'bx1_xx_x101_1x10_11_0 : ILL = USER;        // SPRi/LPRi USP
337
                  15'bx1_xx_x111_0x10_11_0 : ILL = USER;        // SPRi/LPRi INTBASE
338
                  15'bx1_xx_x0x1_0111_11_x : ILL = USER & OPREG[0];      // BICPSRW,BISPSRW
339
                  15'bx1_00_10xx_0000_11_1 : ILL = USER;        // SETCFG - Achtung : is coded as 2 Byte Opcode 
340
                  15'b1x_00_xxxx_0001_11_1 : ILL = USER;        // LMR/SMR/RDVAL/WRVAL
341
                  15'b1x_10_01xx_0001_11_1 : ILL = USER;        // CINV
342
                  default                                  : ILL = 1'b0;
343
                endcase
344
 
345
        // ++++++++++++++++++++++++ Detect Undefined opcodes  +++++++++++++++
346
 
347
        always @(OPREG or lsbes or valid or CFG)
348
                casex ({valid,OPREG[13:2],lsbes})
349
                  16'bx1x_xx_xxxx_1111_110 : undef_opc = 1'b1;          // Format 3 : xxx1
350
                  16'bx1x_xx_x100_0111_110 : undef_opc = 1'b1;          // Format 3 : 1000
351
                  16'b1xx_1x_xxxx_0000_111 : undef_opc = 1'b1;          // Format 5 : 1xxx
352
                  16'b1xx_01_xxxx_0000_111 : undef_opc = 1'b1;          // Format 5 : 01xx
353
                  16'b1xx_01_00xx_0100_111 : undef_opc = 1'b1;          // Format 6 : 0100
354
                  16'b1xx_10_10xx_x100_111 : undef_opc = 1'b1;          // Format 6/7 : 1010
355 11 ns32kum
                  16'b1xx_xx_xxxx_x011_111 : undef_opc = ~CFG[1];       // Format 9/11 : FPU Befehle wie MOVif etc. und ADDf etc.
356 9 ns32kum
                  16'b1xx_xx_xxxx_1111_111 : undef_opc = ~CFG[1];       // Format 12 : FPU Befehle wie POLYf etc.
357
                  16'b1xx_x1_xxxx_0001_111 : undef_opc = 1'b1;          // Format 14 : x1xx 
358
                  16'b1xx_10_00xx_0001_111 : undef_opc = 1'b1;          // Format 14 : 1000
359
                  16'b1xx_10_1xxx_0001_111 : undef_opc = 1'b1;          // Format 14 : 101x
360
                  16'b1xx_00_1xxx_0001_111 : undef_opc = ~CFG[2] | ~OPREG[18];  // Format 14 : LMR/SMR
361
                  16'b1xx_xx_xxxx_x011_011 : undef_opc = ~CFG[3];       // Format 15.1/15.5 : CUSTOM CCV0, CCAL0 etc.
362
                  16'b1xx_xx_xxxx_0001_011 : undef_opc = 1'b1;          // Format 15.0 - not yet in, requires HW change
363
                  16'b1xx_xx_xxxx_x1x1_011 : undef_opc = 1'b1;          // Format 15 : rest
364
                  16'b1xx_xx_xxxx_1001_011 : undef_opc = 1'b1;          // Format 15.4
365
                // completely undefined :
366
                  16'bxx1_xx_xxxx_0111_111 : undef_opc = 1'b1;          // Format 10
367
                  16'bxx1_xx_xxxx_100x_111 : undef_opc = 1'b1;          // Format 13/18
368
                  16'bxx1_xx_xxxx_x101_111 : undef_opc = 1'b1;          // Format 16/17
369
                  16'bxx1_xx_xxxx_xxx0_011 : undef_opc = 1'b1;          // Format 19
370
                  default                                  : undef_opc = 1'b0;
371
                endcase
372
 
373
        // 2. Undefined Addressing mode 5'b10011
374
 
375
        assign gen12 = (OPREG[15:11] == udef_amode);
376
        assign gen22 = (OPREG[10:6]  == udef_amode);
377
        assign gen13 = (OPREG[23:19] == udef_amode);
378
        assign gen23 = (OPREG[18:14] == udef_amode);
379
 
380
        always @(OPREG or valid or gen12 or gen22 or gen13 or gen23)
381 11 ns32kum
                if (valid[2] && (OPREG[7:5] != 3'b000) && (OPREG[3:0] == 4'b1110)) undef_am = gen13 | gen23;     // nearly all 3 Byte opcodes
382 9 ns32kum
                  else
383 11 ns32kum
                    undef_am = valid[1] & gen12 & (OPREG[1:0] != 2'b10) & ((OPREG[3:2] != 2'b11) & gen22);       // all 2 Byte opcodes
384 9 ns32kum
 
385
        // 3. When is Immediate not allowed ?
386
 
387
        assign igen12 = (OPREG[15:11] == imode);
388
        assign igen22 = (OPREG[10:6]  == imode);
389
        assign igen13 = (OPREG[23:19] == imode);
390
        assign igen23 = (OPREG[18:14] == imode);
391
 
392
        always @(*)
393
                casex ({valid[2:1],OPREG[13:2],lsbes})
394 11 ns32kum
                  15'bx1_xxxxxx_x0xx11_0 : undef_im =  igen12 & (OPREG[5:4] != 2'b01);  // Format 2 : ADDQD,SPR,Scond
395 9 ns32kum
                  15'bx1_xxxxxx_x10111_0 : undef_im =  igen12;          // Format 2 : ACB,MOVQ
396
                  15'bx1_xxxxx0_011111_0 : undef_im =  igen12;          // Format 3 : CXPD,JUMP,JSR
397
                  15'bx1_xxxxxx_xxxxx0_0 : undef_im =  igen22;          // Format 4
398 11 ns32kum
                  15'bx1_xxxxxx_xxxx01_0 : undef_im = (igen12 & (OPREG[5:4] == 2'b10))  // Format 4 : SRC1 - not ADDR
399 9 ns32kum
                                                                                         |(igen22 & (OPREG[5:4] != 2'b00)); // Format 4 : SRC2 - CMP
400
                  15'b1x_xxxxxx_x10011_1 : undef_im =  igen23;          // Format 6+7
401
                  15'b1x_xxx0xx_0x1011_1 : undef_im =  igen13 | igen23; // Format 8 EXT,CVTP
402
                  15'b1x_xxx0xx_101011_1 : undef_im =  igen23;          // Format 8 : INS
403
                  15'b1x_xxx0xx_111011_1 : undef_im =  igen13;          // Format 8 : CHECK
404
                  15'b1x_xxx1xx_101011_1 : undef_im =  igen13 | igen23; // Format 8 MOVUS,MOVSU
405
                  15'b1x_xxx1xx_011011_1 : undef_im =  igen23;          // Format 8 : FFS
406
                  15'b1x_xxxxxx_001111_1 : undef_im =  igen23;          // Format 9
407
                  15'b1x_xxxxxx_101111_1 : undef_im =  igen23 & (OPREG[13:10] != 4'h2); // Format 10 without CMPf
408
                  15'b1x_010xxx_111111_1 : undef_im =  igen23;          // Format 12 SCALB+LOGB
409
                  15'b1x_000xxx_000111_1 : undef_im =  igen13;          // Format 14 RDVAL+WRVAL
410
                  15'b1x_0011xx_000111_1 : undef_im =  igen13;          // Format 14 SMR
411
                  default                                : undef_im = 1'b0;
412
                endcase
413
 
414
        // Final Message :
415
 
416
        assign UNDEF = undef_opc | undef_am | undef_im;
417
 
418
endmodule
419
 
420 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
421 9 ns32kum
//
422
//      5. GRUPPE_2             Decoder and State Machine for GRUPPE_2 Opcodes
423
//
424 11 ns32kum
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
425
module GRUPPE_2 ( BCLK, PHASE_0, OPREG, PHASE, SRC_1, SRC_2, REGA1, REGA2, IRRW1, IRRW2, ADRD1, ADRD2, EXR12, EXR22,
426 9 ns32kum
                                  PHRD1, PHRD2, NXRD1, NXRW2, ACCA, OPERA,
427
                                  STATE_0, STATE_GROUP_50, STATE_GROUP_60 );
428
 
429
 
430
        input                   BCLK,PHASE_0;
431 14 ns32kum
        input   [18:0]   OPREG;
432 9 ns32kum
        input    [3:0]   PHASE;  // nur die 4 LSBs
433
        // Source 1 & 2 Inputs
434
        input    [6:0]   SRC_1,SRC_2,REGA1,REGA2,IRRW1,IRRW2;
435
        input   [18:0]   ADRD1,ADRD2,EXR12,EXR22;
436
        input    [3:0]   PHRD1,PHRD2;
437
        input    [3:0]   NXRD1,NXRW2;
438
        input    [3:0]   ACCA;   // ACCA = Access type : 0x Register
439
                                                        //      [3:2] or [1:0]          10 Memory
440
                                                        //                                              11 Memory + Index
441
        input   [10:0]   OPERA;
442
 
443
        output  [66:0]   STATE_0;
444
        output  [66:0]   STATE_GROUP_50,STATE_GROUP_60;
445
 
446
        reg             [66:0]   STATE_GROUP_50,STATE_GROUP_60;
447
        reg             [66:0]   STATE_0,state_50,state_53,state_54,state_55,state_58,state_59,state_5A;
448
        reg              [4:0]   op_code,op_reg_reg;
449
        reg              [7:0]   phsrc1,phsrc2;
450
        reg              [5:0]   chkreg;
451
        reg              [1:0]   bwdreg;
452
        reg                             tbit_flag,size_dw;
453
        reg                             inss_flag;
454 14 ns32kum
        reg                             ext_tos;
455 9 ns32kum
 
456 14 ns32kum
        wire    [18:0]   exoffset,re_wr,rexwr;
457 9 ns32kum
        wire    [10:0]   op_kust,op_bwd;
458
        wire     [7:0]   phchk;
459
        wire     [4:0]   op_reg;
460
        wire     [6:0]   src_1l,src_2l;
461
        wire     [5:0]   dest_2;
462
        wire     [3:0]   get8b_s,get8b_d;
463
        wire     [6:0]   rd_reg;
464
        wire    [10:0]   op_zext;
465
        wire     [3:0]   imdi;
466
 
467
        parameter dont_care     = 67'hx_xxxx_xxxx_xxxx_xxxx;
468
        // Address-Field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
469
        parameter addr_nop      = 19'h0;        // alle Parameter auf 0
470
        parameter disp2ea       = 19'bxx_0010_0000_0_0000_0010; // pass DISP
471
        parameter case_op       = 19'bxx_0010_1000_0_0000_0001; // SRC1 add to PC_ARCHI
472
        parameter read_byb      = 19'b00_1011_11xx_0_0000_0011; // read of SRC2 for Bit opcodes
473 11 ns32kum
        parameter exr11         = {2'b10  ,4'b1011,4'h0 ,9'h080};       // 2. access External with Mem.-Pointer + 4* Disp
474 9 ns32kum
        parameter adrcvtp       = 19'bxx_0010_0111_0_0000_0000; // for CVTP
475 11 ns32kum
        parameter addone        = 19'bxx_0010_0100_0_0000_0000; // for INDEX : SRC1 + SRC2 , simple Add without Flags
476 9 ns32kum
        parameter addind        = 19'bxx_0010_0100_0_0000_0011; // for INDEX : SRC1 + EA
477
        parameter src_x         = 7'hxx;
478
        parameter dest_x        = 6'hxx;
479
        parameter imme          = {1'b1,6'hxx};
480
        parameter F0            = 7'h20;
481
        parameter F0_h          = 7'h21;
482
        parameter w_F0          = 6'h20;
483
        parameter w_F0_h        = 6'h21;
484
        parameter temp_l        = 6'h3C;
485
        parameter temp_h        = 6'h3D;        // Second last place for 8B TEMP Register
486
        parameter temp_1        = 6'h3E;
487
        parameter rtmpl         = 7'h3C;
488
        parameter rtmph         = 7'h3D;
489
        parameter rtmp1         = 7'h3E;
490 14 ns32kum
        parameter op_mov        = {3'bx1x,8'h45};
491
        parameter op_adr        = {3'bx1x,8'h49};
492
        parameter op_addl       = {3'b01x,8'hB0};
493
        parameter op_addf       = {3'b11x,8'hB0};
494
        parameter op_mull       = {3'b01x,8'hBC};
495
        parameter op_mulf       = {3'b11x,8'hBC};
496
        parameter op_stpr       = {3'b11x,8'h54};       // Special-Op for String opcodes
497 9 ns32kum
        parameter op_lsh        = {3'b011,8'h65};       // EXT : shift to right : DOUBLE !
498
        parameter op_msk        = {3'b011,8'h80};       // reuse of EXT Opcode at INS !
499
        parameter op_mul        = {3'b011,8'h78};       // INDEX
500 14 ns32kum
        parameter op_rwv        = {3'bx1x,8'hE0};       // RDVAL+WRVAL
501 9 ns32kum
 
502
        always @(OPREG) // whether the Opcode is valid is decided in DECODER !
503 14 ns32kum
          casex (OPREG[13:0])
504 23 ns32kum
                14'bxx_xxxx_1111_1110 : op_code = {3'b011,OPREG[10],OPREG[8]};  // DOT/POLY
505 9 ns32kum
                14'b00_0xxx_0000_1110 : op_code = 5'b1_0000;    // MOVS/CMPS
506
                14'b00_11xx_0000_1110 : op_code = 5'b1_0000;    // SKPS
507
                14'b00_0xxx_1100_1110 : op_code = 5'b1_0001;    // MOVM/CMPM
508
                14'bxx_xx10_0111_11xx : op_code = 5'b1_0010;    // JUMP/JSR
509
                14'bxx_x111_0111_11xx : op_code = 5'b1_0011;    // CASE
510
                14'bxx_xxxx_xx11_010x : op_code = 5'b1_0100;    // TBIT
511
                14'bxx_xxxx_xx11_0111 : op_code = 5'b1_0100;    // TBIT
512
                14'b0x_1xxx_0100_1110 : op_code = 5'b1_0100;    // CBIT/SBIT
513
                14'b11_10xx_0100_1110 : op_code = 5'b1_0100;    // IBIT
514
                14'b00_11xx_1100_1110 : op_code = 5'b1_0101;    // EXTS
515
                14'b10_x1xx_1100_1110 : op_code = 5'b1_0111;    // DEI/MEI
516
                14'bxx_x0xx_1110_1110 : op_code = 5'b1_1000;    // CHECK
517
                14'bxx_x0xx_0010_1110 : op_code = 5'b1_1010;    // EXT
518
                14'bxx_x0xx_1010_1110 : op_code = 5'b1_1011;    // INS
519
                14'b00_10xx_1100_1110 : op_code = 5'b1_1011;    // INSS, the same like INS !
520
                14'bxx_x0xx_0110_1110 : op_code = 5'b1_1100;    // CVTP
521
                14'bxx_x1xx_0010_1110 : op_code = 5'b1_1101;    // INDEX
522
                14'bxx_x000_0111_11xx : op_code = 5'b1_1110;    // CXPD
523
                14'b00_0xxx_0001_1110 : op_code = 5'b1_1111;    // RDVAL+WRVAL
524
                default                           : op_code = 5'b00_xxx;
525
          endcase
526
 
527
        always @(posedge BCLK) if (PHASE_0) op_reg_reg <= op_code;
528
        assign op_reg = PHASE_0 ? op_code : op_reg_reg;
529
 
530
        always @(PHRD1) // recode of States
531
          casex (PHRD1)
532
                 4'h5 : phsrc1 = 8'h51;
533
                 4'h6 : phsrc1 = 8'h52;
534
                 4'hB : phsrc1 = 8'h53; // ok, is in default ...
535
          default : phsrc1 = 8'h53;
536
          endcase
537
 
538
        assign get8b_s = (PHRD1 == 4'hB) ? 4'hC : 4'h0; // Special case 8B Immeadiate, is used in State 53
539
 
540
        always @(PHRD2) // recode of States
541
          casex (PHRD2)
542
                 4'h5 : phsrc2 = 8'h56;
543
                 4'h6 : phsrc2 = 8'h57;
544
                 4'hB : phsrc2 = 8'h58; // ok, is in default ...
545
          default : phsrc2 = 8'h58;
546
          endcase
547
 
548
        assign get8b_d = (PHRD2 == 4'hB) ? 4'hC : 4'h0; // Special case 8B Immeadiate, is used in State 58
549
 
550
        assign src_1l = {SRC_1[6:1],1'b0};
551 23 ns32kum
        assign src_2l = {SRC_2[6:1],~SRC_2[0]};  // used only for DEI and MEI 
552 9 ns32kum
        assign dest_2 =  SRC_2[5:0];
553
 
554
        assign phchk = {7'b0101_010,size_dw};   // Phase 54 or 55
555
 
556
        assign op_kust = {1'bx,OPERA[9:8],8'h7A};       // Special-Opcode for MOVM/CMPM
557
        assign op_bwd  = {1'bx,OPERA[9:8],8'h45};       // for CASE and Bit opcodes
558
 
559 11 ns32kum
        assign re_wr   = {EXR22[18:17],4'b0101,4'h0, 9'h003};   // REUSE Address : Write of rmw , top 2 Bits contain size
560 9 ns32kum
 
561 23 ns32kum
        always @(posedge BCLK) if (PHASE_0) ext_tos <= (OPREG[18:14] == 5'h17); // TOS Address mode
562
        assign rexwr   = {EXR22[18:17],4'b0101,4'h0, ext_tos, 8'h03};   // REUSE Address : Write of rmw , only for EXT and EXTS
563 14 ns32kum
 
564 9 ns32kum
        always @(posedge BCLK) tbit_flag <= ~OPERA[1];  // due to Timing ...
565
        always @(posedge BCLK) size_dw   <=  OPERA[9];
566
 
567
        always @(posedge BCLK) if (PHASE_0) chkreg <= {3'b000,OPREG[13:11]};    // for CHECK
568
        assign rd_reg = (PHASE_0) ? {4'b0,OPREG[13:11]} : {1'b0,chkreg};        // for read operation at EXT/INS
569
 
570
        always @(posedge BCLK) if (PHASE_0) bwdreg <= OPREG[9:8];               // only for INS/INSS !
571
        assign op_zext = {1'bx,(PHASE_0 ? OPREG[9:8] : bwdreg),8'h76};
572
 
573
        always @(posedge BCLK) if (PHASE_0) inss_flag <= OPREG[6];      // Difference INSS to INS
574
        assign imdi = inss_flag ? 4'h8 : 4'hE;  // read Immediate or Displacement
575
        assign exoffset = inss_flag ? 19'b10_1011_0000_0_0000_0011      // Read of SRC2 at INSS
576
                                                                : 19'b10_1011_1100_0_0000_0011; // Read of SRC1+Offset at EXT, SRC2+Offset at INS 
577
 
578
        always @(*)
579
          casex (op_reg)
580 11 ns32kum
                5'b1_0000 :     // MOVS Phase 0 : Entry 1. Pointer "in Page"-test prepare, 2. test for R0=0 , then jump to x'C0
581 9 ns32kum
                        begin
582 11 ns32kum
                          STATE_0  = {   addr_nop,8'h67, 7'h01, 7'h02, 1'b0,dest_x,op_stpr,     2'b00,2'b00,4'h0  };    // String-Pointer prepare
583 9 ns32kum
                          state_50 = dont_care;
584
                          state_53 = dont_care;
585
                          state_54 = dont_care;
586
                          state_55 = dont_care;
587
                          state_58 = dont_care;
588
                          state_59 = dont_care;
589
                          state_5A = dont_care;
590
                        end
591
                5'b1_0001 :     // MOVM Phase 0 : Entry with test for R0=0 , then jump to x'C0
592
                        begin
593
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
594
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
595
                          state_53 = {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b1,temp_h,op_adr,  2'b00,2'b00,NXRW2 };
596
                          state_54 = dont_care;
597
                          state_55 = dont_care;
598 11 ns32kum
                          state_58 = {   disp2ea, 8'h65, src_x, src_x, 1'b1,temp_1,op_adr,  2'b00,2'b00,4'b1110 };      // Read of DISP for count
599
                          state_59 = {   addr_nop,8'h67, rtmph, rtmp1, 1'b0,dest_x,op_stpr,     2'b00,2'b00,4'h0  };    // String-Pointer prepare
600 9 ns32kum
                          state_5A = dont_care;
601
                        end
602
                5'b1_0010 :     // JUMP/JSR
603
                        begin
604
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
605
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
606
                          state_53 = {   addr_nop,8'h66, src_x, src_x, 1'b1,temp_h,op_adr,  2'b00,2'b00,4'h0  };
607
                          state_54 = dont_care;
608
                          state_55 = dont_care;
609
                          state_58 = dont_care;
610
                          state_59 = dont_care;
611
                          state_5A = dont_care;
612
                        end
613
                5'b1_1110 :     // CXPD
614
                        begin
615
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
616
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
617
                          state_53 = {   addr_nop,8'h6B, imme,  src_x, 1'b1,temp_h,op_mov,  2'b00,2'b00,4'h0  };
618
                          state_54 = dont_care;
619
                          state_55 = dont_care;
620
                          state_58 = dont_care;
621
                          state_59 = dont_care;
622
                          state_5A = dont_care;
623
                        end
624
                5'b1_1111 :     // RDVAL+WRVAL
625
                        begin
626
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
627
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
628 11 ns32kum
                          state_53 = {   addr_nop,8'h00, src_x, src_x, 1'b0,dest_x,op_rwv,  2'b00,2'b10,4'h0  };        // LD_OUT set because of "F"
629 9 ns32kum
                          state_54 = dont_care;
630
                          state_55 = dont_care;
631
                          state_58 = dont_care;
632
                          state_59 = dont_care;
633
                          state_5A = dont_care;
634
                        end
635
                5'b1_0011 :     // CASE
636
                        begin
637
                          STATE_0  = ACCA[3] ?          // _M...
638
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
639
                                           : {   case_op, 8'h54, SRC_1, src_x, 1'b0,dest_x,op_bwd,      2'b00,2'b00,4'h0  };
640 11 ns32kum
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };        // only one operand in mem.
641 9 ns32kum
                          state_53 = {   case_op, 8'h54, imme,  src_x, 1'b0,dest_x,op_bwd,      2'b00,2'b00,4'h0  };
642
                          state_54 = {   addr_nop,8'h66, src_x, src_x, 1'b1,temp_h,op_adr,  2'b00,2'b00,4'h0  };
643
                          state_55 = dont_care;
644
                          state_58 = dont_care;
645
                          state_59 = dont_care;
646
                          state_5A = dont_care;
647
                        end
648 11 ns32kum
                5'b1_0100 : // all Bit opcodes with Bit in memory. RMW Test in Phase x'59 = Special case, otherwise x'58
649 9 ns32kum
                        begin
650
                          STATE_0  = ACCA[3] ?          // _M...
651
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
652
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
653
                          state_50 = ACCA[3] ?          // _M...
654
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
655
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
656
                          state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
657 11 ns32kum
                          state_54 = {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };        // here SRC1 => TEMP_H
658 9 ns32kum
                          state_55 = dont_care;
659 11 ns32kum
                          state_58 = {   read_byb,8'h59, rtmph, src_x, 1'b0,dest_x,op_bwd,      2'b00,2'b00,4'h1  };    // next read of Byte
660 9 ns32kum
                          state_59 = tbit_flag ?
661
                                                 {       addr_nop,8'h00, src_x, imme,  1'b0,dest_x,OPERA,       2'b00,2'b10,4'h0  }             // TBIT end
662 11 ns32kum
                                           : {   re_wr,   8'h27, src_x, imme,  1'b0,dest_x,OPERA,       2'b00,2'b10,4'h1  };    // CBIT/SBIT/IBIT end
663 9 ns32kum
                          state_5A = dont_care;
664
                        end
665
                5'b1_0101 : // EXTS : BASE Operand => TEMP, calculate address of Destination
666
                        begin
667
                          STATE_0  = ACCA[3] ?          // _M...
668
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
669
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
670
                          state_50 = ACCA[3] ?          // _M...
671
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
672
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
673
                          state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
674
                          state_54 = ACCA[1] ?
675 11 ns32kum
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }         // here Adr(DEST) => EA
676
                                           : {   addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h8  };    // 1 Byte Immediate read
677 9 ns32kum
                          state_55 = dont_care;
678 11 ns32kum
                          state_58 = {   addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h8  };    // 1 Byte Immediate read
679 9 ns32kum
                          state_59 = ACCA[1] ?          // _..M.
680 14 ns32kum
                                                 {       rexwr,   8'h27, imme,  rtmph, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h1  }             // result in memory
681 11 ns32kum
                                           : {   addr_nop,8'h00, imme,  rtmph, 1'b1,dest_2,OPERA,       2'b00,2'b00,4'h0  };    // result in Register
682 9 ns32kum
                          state_5A = dont_care;
683
                        end
684
                5'b1_1010 : // EXT : BASE Operand => TEMP, calculate address of Destination
685
                        begin
686
                          STATE_0  = ACCA[3] ?          // _M...
687
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
688
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
689
                          state_50 = ACCA[3] ?          // _M...
690
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
691
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
692 11 ns32kum
                          state_53 = {   addr_nop,8'h55, src_x, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h0  };    // Addr => EA Reg
693 9 ns32kum
                          state_54 = ACCA[1] ?
694
                                                  ( ACCA[3] ?
695
                                                    {addr_nop,8'h5A, imme,  src_x, 1'b1,temp_h,op_mov,  2'b00,2'b00,4'h0  }
696 11 ns32kum
                                                   :{ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }     )       // here Adr(DEST) => EA
697 9 ns32kum
                                           : {   addr_nop,8'h59, rd_reg,(ACCA[3] ? imme : rtmph),
698
                                                                                                                   1'b1,temp_h,op_lsh,  2'b00,2'b00,4'hE  };    // Displacement read
699 11 ns32kum
                          state_55 = {   exoffset,8'h54, rd_reg,src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h1  };    // Read Source, EA reuse
700
                          state_58 = {   addr_nop,8'h59, rd_reg,rtmph, 1'b1,temp_h,op_lsh,      2'b00,2'b00,4'hE  };    // Displacement read
701 9 ns32kum
                          state_59 = ACCA[1] ?          // _..M.
702 14 ns32kum
                                                 {       rexwr,   8'h27, src_x, rtmph, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h1  }             // result in memory
703 11 ns32kum
                                           : {   addr_nop,8'h00, src_x, rtmph, 1'b1,dest_2,OPERA,       2'b00,2'b00,4'h0  };    // result in Register
704
                          state_5A = {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,      2'b00,2'b00,NXRW2 };    // special case Mem-Mem
705 9 ns32kum
                        end
706 11 ns32kum
                5'b1_1011 : // INS/INSS : BASE Operand => TEMP, SRC2 read as Double ! RMW not tested (Phase x'6A) but uncritical
707 9 ns32kum
                        begin
708
                          STATE_0  = ACCA[3] ?          // _M...
709
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
710
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };
711
                          state_50 = ACCA[3] ?          // _M...
712
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
713
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };
714 11 ns32kum
                          state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };        // zext(SRC1) => TEMP
715 9 ns32kum
                          state_54 = ACCA[1] ?
716 11 ns32kum
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,      2'b00,2'b00,NXRW2 }             // here Adr(DEST) => EA
717
                                           : {   addr_nop,8'h5A, SRC_2, src_x, 1'b1,temp_l,op_mov,      2'b00,2'b00,imdi  };    // Imme./Disp. read
718
                          state_55 = {   exoffset,8'h6A, rd_reg,src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h1  };    // Read Source, EA reuse
719 9 ns32kum
                          state_58 = {   addr_nop,8'h55, src_x, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h0  };    // 
720
                          state_59 = ACCA[1] ?          // _..M.
721
                                                 {       re_wr,   8'h27, rtmph, rtmpl, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h1  }             // result in memory
722 11 ns32kum
                                           : {   addr_nop,8'h00, rtmph, rtmpl, 1'b1,dest_2,OPERA,       2'b00,2'b00,4'h0  };    // result in Register
723
                          state_5A = {   addr_nop,8'h68, imme,  src_x, 1'b1,temp_1,op_msk,      2'b00,2'b00,4'h0  };    // Mask generate
724 9 ns32kum
                        end
725
                5'b1_1101 : // INDEX : 
726
                        begin
727
                          STATE_0  = ACCA[3] ?          // _M...
728
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
729
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };
730
                          state_50 = ACCA[3] ?          // _M...
731
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
732
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };
733 11 ns32kum
                          state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };        // zext(SRC1) => TEMP_H
734 9 ns32kum
                          state_54 = ACCA[1] ?
735 11 ns32kum
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,      2'b00,2'b00,NXRW2 }             // zext(SRC2) => TEMP_L
736 9 ns32kum
                                           : {   addr_nop,8'h55, SRC_2, src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0  };
737 11 ns32kum
                          state_55 = {   addr_nop,8'h5A, rd_reg,rtmph, 1'b1,temp_h,op_mul,      2'b00,2'b00,4'h0  };    // Multiplication
738 9 ns32kum
                          state_58 = {   addr_nop,8'h55, imme,  src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0  };        // 
739 11 ns32kum
                          state_59 = {   addind,  8'h60, rtmpl, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h0  };    // Add of Index in EA
740
                          state_5A = {   addone,  8'h59, rd_reg,rtmph, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h0  };    // Add of EA (=+1)
741 9 ns32kum
                        end
742
                5'b1_0111 :     // DEI + MEI , both read 8B from DEST ! RMW critical !
743
                        begin
744
                          STATE_0  = ACCA[3] ?          // _M...
745
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
746
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
747
                          state_50 = ACCA[3] ?          // _M...
748
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
749
                                           : {   addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
750
                          state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };
751
                          state_54 = ACCA[1] ?
752 11 ns32kum
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }         // here SRC1 => TEMP_H
753
                                           : {   addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_x,OPERA,       2'b01,2'b00,4'h0  };    // 1. part of Register
754 9 ns32kum
                          state_55 = dont_care;
755
                          state_58 = size_dw ?
756 11 ns32kum
                                                 {       addr_nop,8'h59, rtmph, imme,  1'b0,dest_x,OPERA,       2'b01,2'b00,4'h0  }             // D needs 2 accesses
757
                                           : {   addr_nop,8'h1F, rtmph, imme,  1'b0,dest_x,OPERA,       2'b11,2'b00,4'h0  };    // B+W start at once
758 9 ns32kum
                          state_59 = {   addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l),                                                      // SRC2 = memory or Reg
759
                                                                                                           ~ACCA[1],dest_2,OPERA,       2'b10,2'b00,4'h0  };
760
                          state_5A = dont_care;
761
                        end
762
                5'b1_1000 :     // CHECK
763
                        begin
764 11 ns32kum
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };        // No Register !
765 9 ns32kum
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
766 11 ns32kum
                          state_53 = {   addr_nop,phchk, imme,  src_x, 1'b1,temp_h,op_mov,      2'b00,2'b00,4'h0  };    // No Immediate !
767 9 ns32kum
                          state_54 = ACCA[1] ?
768
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }
769
                                           : (  size_dw ?
770 11 ns32kum
                                                        {addr_nop,8'h5A, SRC_2, rtmpl, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h0  }             // Upper Bound - pointer
771 9 ns32kum
                                                  : {addr_nop,8'h00, rtmph, SRC_2, 1'b1,chkreg,OPERA,   2'b00,2'b10,4'h0  } );
772
                          state_55 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_l,op_mov,      2'b00,2'b00,4'h0  };
773
                          state_58 = size_dw ?
774 11 ns32kum
                                                 {       addr_nop,8'h59, imme,  src_x, 1'b1,temp_1,op_mov,      2'b00,2'b00,4'h0  }             // here SRC2 => TEMP_1
775 9 ns32kum
                                           : {   addr_nop,8'h00, rtmph, imme,  1'b1,chkreg,OPERA,       2'b00,2'b10,4'h0  };
776 11 ns32kum
                          state_59 = {   addr_nop,8'h5A, rtmp1, rtmpl, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h0  };    // Upper Bound - pointer
777 9 ns32kum
                          state_5A = {   addr_nop,8'h00, rtmph, (ACCA[1] ? rtmp1 : SRC_2),
778
                                                                                                                   1'b1,chkreg,OPERA,   2'b00,2'b10,4'h0  };    // pointer - Lower Bound
779
                        end
780
                5'b1_1100 :     // CVTP
781
                        begin
782 11 ns32kum
                          STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };        // Address
783 9 ns32kum
                          state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };
784
                          state_53 = {   addr_nop,8'h54, src_x, src_x, 1'b1,temp_h,op_adr,      2'b00,2'b00,4'h0  };
785 11 ns32kum
                          state_54 = {   adrcvtp, 8'h73, rtmph, rd_reg,1'b0,dest_x,op_mov,  2'b00,2'b00,4'h0  };        // 8*TEMP+Offset
786 9 ns32kum
                          state_55 = dont_care;
787
                          state_58 = dont_care;
788
                          state_59 = dont_care;
789
                          state_5A = dont_care;
790
                        end
791
                5'b01_100 :     // POLYL
792
                        begin
793
                          STATE_0  = ACCA[3] ?          // _M...
794
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
795
                                           : {   addr_nop,8'h54, SRC_1, F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0  };
796
                          state_50 = ACCA[3] ?          // _M...
797
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
798
                                           : {   addr_nop,8'h54, SRC_1, F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0  };
799
                          state_53 = {   addr_nop,8'h54, imme,  F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,get8b_s };
800
                          state_54 = {   addr_nop,8'h64, (ACCA[3] ? imme : src_1l),
801
                                                                                                        F0,    1'b1,temp_h,op_mull, 2'b10,2'b00,4'h0  };
802
                          state_55 = dont_care;
803
                          state_58 = {   addr_nop,8'h59, imme,  rtmph, 1'b0,dest_x,op_addl, 2'b01,2'b00,get8b_d };
804
                          state_59 = {   addr_nop,8'h62, (ACCA[1] ? imme : src_2l),
805
                                                                                                        rtmpl, 1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0  };
806
                          state_5A = dont_care;
807
                        end
808
                5'b01_101 :     // POLYF
809
                        begin
810
                          STATE_0  = ACCA[3] ?          // _M...
811
                                                 {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
812 23 ns32kum
                                           : {   addr_nop,8'h55, SRC_1, F0,    1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0  };
813 9 ns32kum
                          state_50 = ACCA[3] ?          // _M...
814
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
815 23 ns32kum
                                           : {   addr_nop,8'h55, SRC_1, F0,    1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0  };
816
                          state_53 = {   addr_nop,8'h55, imme,  F0,    1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0  };
817 9 ns32kum
                          state_54 = ACCA[1] ?
818
                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }
819 23 ns32kum
                                           : {   addr_nop,8'h6E, rtmph, SRC_2, 1'b0,dest_x,op_addf, 2'b11,2'b00,4'h0  };
820
                          state_55 = {   addr_nop,8'h54, src_x, src_x, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };
821
                          state_58 = {   addr_nop,8'h6E, rtmph, imme,  1'b0,dest_x,op_addf, 2'b11,2'b00,4'h0  };
822 9 ns32kum
                          state_59 = dont_care;
823
                          state_5A = dont_care;
824
                        end
825
                5'b01_110 :     // DOTL
826
                        begin
827
                          STATE_0  = (~ACCA[3] & ~ACCA[1]) ?            // _R.R.
828
                                                 {       addr_nop,8'h59, SRC_1, SRC_2, 1'b0,dest_x,op_mull, 2'b01,2'b00,4'h0  }
829
                                           : (  ACCA[3] ?               // _M...
830
                                                    {ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
831
                                                  : {ADRD2,   phsrc2,src_x, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 } );
832
                          state_50 = ACCA[3] ?          // _M...
833
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
834
                                           : {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };
835
                          state_53 = ACCA[1] ?          // _..M.
836
                                                 {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_mov,  2'b00,2'b00,get8b_s }
837
                                           : {   addr_nop,8'h59, imme,  SRC_2, 1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_s };
838
                          state_54 = {   addr_nop,8'h55, imme,  src_x, 1'b1,temp_l,op_mov,  2'b00,2'b00,4'h0  };
839
                          state_55 = {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };
840
                          state_58 = {   addr_nop,8'h59, (ACCA[3] ? rtmph : SRC_1),             //_M...
841
                                                                                                        imme,  1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_d };
842 11 ns32kum
                          state_59 = {   addr_nop,8'h5A, (ACCA[3] ? (ACCA[1] ? rtmpl : imme) : src_1l), (ACCA[1] ? imme : src_2l),
843 9 ns32kum
                                                                                                                   1'b1,temp_h,op_mull, 2'b10,2'b00,4'h0  };
844
                          state_5A = {   addr_nop,8'h61, rtmph, F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0  };
845
                        end
846
                5'b01_111 :     // DOTF
847
                        begin
848
                          STATE_0  = (~ACCA[3] & ~ACCA[1]) ?            // _R.R.
849 23 ns32kum
                                                 {       addr_nop,8'h63, SRC_1 ,SRC_2 ,1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0  }         // opera = MULF
850 9 ns32kum
                                           : (  ACCA[3] ?               // _M...
851
                                                    {ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
852
                                                  : {ADRD2,   phsrc2,src_x, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 } );
853
                          state_50 = ACCA[3] ?          // _M...
854
                                                 {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }
855
                                           : {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };
856
                          state_53 = ACCA[1] ?          // _..M.
857
                                                 {   addr_nop,8'h55, imme,  src_x, 1'b1,temp_h,op_mov,  2'b00,2'b00,4'h0  }
858 23 ns32kum
                                           : {   addr_nop,8'h63, imme,  SRC_2 ,1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0  };
859 9 ns32kum
                          state_54 = dont_care;
860
                          state_55 = {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };
861
                          state_58 = {   addr_nop,8'h63, (ACCA[3] ? rtmph : SRC_1),             //_M...
862 23 ns32kum
                                                                                                        imme,  1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0  };
863 9 ns32kum
                          state_59 = dont_care;
864
                          state_5A = dont_care;
865
                        end
866
                default
867
                        begin
868
                          STATE_0  = dont_care;
869
                          state_50 = dont_care;
870
                          state_53 = dont_care;
871
                          state_54 = dont_care;
872
                          state_55 = dont_care;
873
                          state_58 = dont_care;
874
                          state_59 = dont_care;
875
                          state_5A = dont_care;
876
                        end
877
                endcase
878
 
879
        always @(*)
880
          casex (PHASE)
881
                 4'h0 : STATE_GROUP_50 = state_50;
882
                // Phase 51 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1
883 11 ns32kum
                 4'h1 : STATE_GROUP_50 = {exr11,   8'h52, src_x,imme , 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'b1111};
884 9 ns32kum
                // Phase 52 : Memory-Pointer for Memory Relative and last access External
885 11 ns32kum
                 4'h2 : STATE_GROUP_50 = {EXR12,   8'h53, IRRW1,imme , 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'b1111};  // atys[0] !
886 9 ns32kum
                 4'h3 : STATE_GROUP_50 = state_53;
887
                 4'h4 : STATE_GROUP_50 = state_54;
888
                 4'h5 : STATE_GROUP_50 = state_55;
889
                // Phase 56 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1
890 11 ns32kum
                 4'h6 : STATE_GROUP_50 = {exr11,   8'h57, src_x,imme , 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'b1111};
891 9 ns32kum
                // Phase 57 : Memory-Pointer for Memory Relative and last access External
892 11 ns32kum
                 4'h7 : STATE_GROUP_50 = {EXR22,   8'h58, IRRW2,imme , 1'b0,dest_x,             op_mov, 2'b00,2'b00,    4'b1111};  // atyd[0] !
893 9 ns32kum
                 4'h8 : STATE_GROUP_50 = state_58;
894
                 4'h9 : STATE_GROUP_50 = state_59;
895
                 4'hA : STATE_GROUP_50 = state_5A;
896
          default : STATE_GROUP_50 = dont_care;
897
          endcase
898
 
899
        always @(*)
900
          casex (PHASE)
901 11 ns32kum
                 4'h0 : STATE_GROUP_60 = {       addr_nop,8'h00, src_x, src_x, 1'b1,chkreg,op_adr,  2'b00,2'b00,4'h0  };        // for INDEX
902
                 4'h1 : STATE_GROUP_60 = {       addr_nop,8'h62, rtmpl, F0,    1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0  };        // for DOTL
903
                 4'h2 : STATE_GROUP_60 = {       addr_nop,8'h00, src_x, src_x, 1'b0,w_F0_h,op_addl, 2'b00,2'b00,4'h0  };        // for DOTL & POLYL !
904 23 ns32kum
                 4'h3 : STATE_GROUP_60 = {       addr_nop,8'h6F, src_x, src_x, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };        // for DOTF
905
                 4'hF : STATE_GROUP_60 = {       addr_nop,8'h6E, rtmph, F0,    1'b0,dest_x,op_addf, 2'b11,2'b00,4'h0  };
906
                 4'hE : STATE_GROUP_60 = {       addr_nop,8'h00, src_x, src_x, 1'b1,w_F0,  op_addf, 2'b00,2'b00,4'h0  };        // for DOTF & POLYF
907 9 ns32kum
                 4'h4 : STATE_GROUP_60 = ACCA[1] ?      // ..M.
908
                                                                 {       ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,temp_h,op_mull, 2'b00,2'b00,NXRW2 }
909
                                                           : {   addr_nop,8'h59, SRC_2, rtmph, 1'b0,temp_h,op_addl, 2'b01,2'b00,4'h0  };        // for POLYL
910 11 ns32kum
                 4'h5 : STATE_GROUP_60 = {       addr_nop,8'h59, src_x, src_x, 1'b1,temp_l,op_kust, 2'b00,2'b00,4'h0  };        // for MOVM/CMPM
911
                 4'h6 : STATE_GROUP_60 = {       addr_nop,8'h01, rtmph, src_x, 1'b0,dest_x,op_mov,      2'b00,2'b00,4'h0  };    // for JUMP/JSR/CASE
912
                 4'h7 : STATE_GROUP_60 = {       addr_nop,8'hC0, (op_reg_reg[0] ? rtmpl : 7'h00),                                                        // Jump to String execution
913 9 ns32kum
                                                                                                                        src_x, 1'b0,dest_x,OPERA,       2'b00,2'b10,4'h0  };    // LD_OUT set, CMPS F-Flag
914
                // for INS                                                                                                              
915 11 ns32kum
                 4'h8 : STATE_GROUP_60 = {       addr_nop,8'h69, rd_reg,rtmph, 1'b1,temp_h,op_lsh,      2'b00,2'b00,4'h0  };    // SRC1 shift
916
                 4'h9 : STATE_GROUP_60 = {       addr_nop,8'h59, rd_reg,rtmp1, 1'b0,dest_x,op_lsh,      2'b00,2'b00,4'h0  };    // Mask shift
917
                 4'hA : STATE_GROUP_60 = {       addr_nop,8'h5A, imme,  src_x, 1'b1,temp_l,op_mov,      2'b00,2'b00,imdi  };    // Imme./Disp. read
918 9 ns32kum
                // for CXPD, this State is decoded explicitly in DECODER
919 11 ns32kum
                 4'hB : STATE_GROUP_60 = {       addr_nop,8'h39, imme,  src_x, 1'b1,temp_l,op_mov,      2'b00,2'b00,4'h0  };    // pass PC
920 9 ns32kum
          default : STATE_GROUP_60 = dont_care;
921
          endcase
922
 
923
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.