OpenCores
URL https://opencores.org/ocsvn/m32632/m32632/trunk

Subversion Repositories m32632

[/] [m32632/] [trunk/] [rtl/] [TOP_MISC.v] - Blame information for rev 9

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 ns32kum
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2
//
3
// This file is part of the M32632 project
4
// http://opencores.org/project,m32632
5
//
6
// Filename: TOP_MISC.v
7
// Version:  1.0
8
// Date:     30 May 2015
9
//
10
// Copyright (C) 2015 Udo Moeller
11
// 
12
// This source file may be used and distributed without 
13
// restriction provided that this copyright statement is not 
14
// removed from the file and that any derivative work contains 
15
// the original copyright notice and the associated disclaimer.
16
// 
17
// This source file is free software; you can redistribute it 
18
// and/or modify it under the terms of the GNU Lesser General 
19
// Public License as published by the Free Software Foundation;
20
// either version 2.1 of the License, or (at your option) any 
21
// later version. 
22
// 
23
// This source is distributed in the hope that it will be 
24
// useful, but WITHOUT ANY WARRANTY; without even the implied 
25
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
26
// PURPOSE. See the GNU Lesser General Public License for more 
27
// details. 
28
// 
29
// You should have received a copy of the GNU Lesser General 
30
// Public License along with this source; if not, download it 
31
// from http://www.opencores.org/lgpl.shtml 
32
// 
33
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
34
//
35
//      Modules contained in this file:
36
//      1. IO_SWITCH    Switch between ICACHE and DCACHE to IO Path
37
//      2. MAKE_STAT    Generate Statistic Signals
38
//
39
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
40
 
41
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
42
//
43
//      1. IO_SWITCH    Switch between ICACHE and DCACHE to IO Path
44
//
45
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
46
module IO_SWITCH ( BCLK, BRESET, I_IOA, D_IOA, I_IORD, D_IORD, D_IOWR, IO_READY, GENSTAT, D_IOBE, IL
47
                                   IO_A, IO_RD, IO_WR, IO_BE, I_IORDY, D_IORDY, STATUS, ILO );
48
 
49
        input                   BCLK,BRESET;
50
        input   [31:0]   I_IOA,D_IOA;
51
        input                   I_IORD;
52
        input                   D_IORD,D_IOWR;
53
        input    [3:0]   D_IOBE;
54
        input                   IO_READY;
55
        input    [2:0]   GENSTAT;
56
        input                   ILO_SIG;
57
        input    [1:0]   DCWACC;
58
 
59
        output  [31:0]   IO_A;
60
        output                  IO_RD,IO_WR;
61
        output   [3:0]   IO_BE;
62
        output                  I_IORDY;
63
        output                  D_IORDY;
64
        output   [3:0]   STATUS;
65
        output                  ILO;
66
 
67
        reg              [3:0]   STATUS;
68
        reg              [1:0]   select;
69
        reg                             ilo_flag;
70
 
71
        wire                    daten;
72
        wire                    sel_dp;
73
        wire                    interrupt;
74
        wire                    ilo_keep;
75
 
76
        assign daten = D_IORD | D_IOWR;
77
 
78
        // DCACHE has priority.
79
        always @(posedge BCLK or negedge BRESET)
80
                if (!BRESET) select <= 2'b0;
81
                  else
82
                        casex ({I_IORD,D_IORD,D_IOWR,IO_READY,ilo_keep,select})
83
                          7'b000xx_00 : select <= 2'b00;
84
                          7'b1000x_00 : select <= 2'b11;
85
                          7'bx100x_00 : select <= 2'b10;
86
                          7'bxx10x_00 : select <= 2'b10;
87
                        // the access has in the same cycle a READY !
88
                          7'b1001x_00 : select <= 2'b00;
89
                          7'bx101x_00 : select <= 2'b00;
90
                          7'bxx11x_00 : select <= 2'b00;
91
                        // Datea Access
92
                          7'bxxx0x_10 : select <= 2'b10;
93
                          7'bxxx11_10 : select <= 2'b10;        // keep because of Interlocked
94
                          7'bxxx10_10 : select <= 2'b00;
95
                        // Instruction Access     
96
                          7'bxxx0x_11 : select <= 2'b11;
97
                          7'bxxx1x_11 : select <= 2'b00;
98
                          default         : select <= 2'b00;
99
                        endcase
100
 
101
        assign sel_dp = (select == 2'b10) | ((select == 2'b00) & daten);
102
 
103
        assign IO_RD   =  sel_dp ? D_IORD : I_IORD;
104
        assign IO_WR   =  sel_dp ? D_IOWR : 1'b0;
105
        assign IO_A    =  sel_dp ? D_IOA  : I_IOA;
106
        assign IO_BE   =  sel_dp ? D_IOBE : 4'b1111;    // Instruction read always 32 Bit
107
 
108
        assign D_IORDY =  sel_dp & IO_READY;
109
        assign I_IORDY = ~sel_dp & IO_READY;
110
 
111
        assign interrupt = GENSTAT[1] | GENSTAT[0];
112
 
113
        always @(*)
114
                casex ({sel_dp,daten,interrupt,I_IORD})
115
                  4'b110x : STATUS = 4'hA;                                              // Daten
116
                  4'b111x : STATUS = GENSTAT[1] ? 4'h4 : 4'h6;  // Int Ack. : End of Int
117
                  4'b0xx1 : STATUS = 4'h8;                                              // Programm
118
                  default : STATUS = {3'd0,GENSTAT[2]};                 // WAIT or Inactive
119
                endcase
120
 
121
        // +++++++++++  ILO Control  ++++++++++++++++++
122
 
123
        always @(posedge BCLK)
124
                if (!ILO_SIG) ilo_flag <= 1'b0; // Flag is set at read and cleared with write
125
                  else ilo_flag <= (D_IORD & sel_dp) | DCWACC[0] | ilo_keep;
126
 
127
        assign ilo_keep = ilo_flag & ~D_IOWR & ~DCWACC[1];
128
 
129
        assign ILO = ILO_SIG & ((D_IORD & sel_dp) | DCWACC[0] | ilo_flag | D_IOWR | DCWACC[1]);
130
 
131
endmodule
132
 
133
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
134
//
135
//      2. MAKE_STAT    Generate Statistic Signals
136
//
137
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
138
module MAKE_STAT ( BCLK, READ, DACC_OK, DC_ACC, DPTE_ACC, DC_MDONE, DRAM_WR, IC_READ, IACC_OK, DATA_
139
                                   IC_ACC, IPTE_ACC, IC_MDONE, KOLLISION, STATSIGS );
140
 
141
        input   BCLK;
142
        input   READ,DACC_OK;
143
        input   DC_ACC,DPTE_ACC,DC_MDONE;
144
        input   DRAM_WR;
145
        input   IC_READ,IACC_OK,DATA_HOLD;
146
        input   IC_ACC,IPTE_ACC,IC_MDONE;
147
        input   KOLLISION;
148
 
149
        output  reg [7:0]        STATSIGS;
150
 
151
        always @(posedge BCLK)
152
                begin
153
                        STATSIGS[7] <= KOLLISION;                                               // 7 : from ICACHE : collisions
154
                        STATSIGS[6] <= IPTE_ACC;                                                // 6 : Instruction PTE access
155
                        STATSIGS[5] <= IC_ACC & IC_MDONE;                               // 5 : Instruction Memory read
156
                        STATSIGS[4] <= IC_READ & IACC_OK & ~DATA_HOLD;  // 4 : Instruction read , can be IO-Port too !
157
                        STATSIGS[3] <= DRAM_WR;                                                 // 3 : Data write
158
                        STATSIGS[2] <= DPTE_ACC;                                                // 2 : Data PTE access
159
                        STATSIGS[1] <= DC_ACC & DC_MDONE;                               // 1 : Data Memory read
160
                        STATSIGS[0] <= READ & DACC_OK;                                   // 0 : Data read , can be IO-Port too !
161
                end
162
 
163
endmodule
164
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.