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[/] [m65c02/] [trunk/] [Sim/] [tb_M65C02_Core.v] - Blame information for rev 2

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///////////////////////////////////////////////////////////////////////////////
//
//  Copyright 2012 by Michael A. Morris, dba M. A. Morris & Associates
//
//  All rights reserved. The source code contained herein is publicly released
//  under the terms and conditions of the GNU Lesser Public License. No part of
//  this source code may be reproduced or transmitted in any form or by any
//  means, electronic or mechanical, including photocopying, recording, or any
//  information storage and retrieval system in violation of the license under
//  which the source code is released.
//
//  The source code contained herein is free; it may be redistributed and/or 
//  modified in accordance with the terms of the GNU Lesser General Public
//  License as published by the Free Software Foundation; either version 2.1 of
//  the GNU Lesser General Public License, or any later version.
//
//  The source code contained herein is freely released WITHOUT ANY WARRANTY;
//  without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
//  PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
//  more details.)
//
//  A copy of the GNU Lesser General Public License should have been received
//  along with the source code contained herein; if not, a copy can be obtained
//  by writing to:
//
//  Free Software Foundation, Inc.
//  51 Franklin Street, Fifth Floor
//  Boston, MA  02110-1301 USA
//
//  Further, no use of this source code is permitted in any form or means
//  without inclusion of this banner prominently in any derived works. 
//
//  Michael A. Morris
//  Huntsville, AL
//
///////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
///////////////////////////////////////////////////////////////////////////////
// Company:         M. A. Morris & Associates
// Engineer:        Michael A. Morris
//
// Create Date:     21:38:27 02/04/2012
// Design Name:     M65C02_Core - WDC W65C02 Microprocessor Re-Implementation
// Module Name:     tb_MAM65C02_Core.v
// Project Name:    C:/XProjects/ISE10.1i/MAM6502
// Target Device:   XC3S200AN-4FT256I 
// Tool versions:   Xilinx ISE 10.1i SP3
//  
// Description: 
//
// Verilog Test Fixture created by ISE for module: M65C02_Core
//
// Dependencies:
// 
// Revision:
// 
//  0.01    12B04   MAM     Initial coding. 
//
// Additional Comments:
// 
///////////////////////////////////////////////////////////////////////////////
 
module tb_M65C02_Core;
 
//    parameter pRst_Vector = 16'hF800;
//    parameter pIRQ_Vector = 16'hF808;
//    parameter pBrk_Vector = 16'hF808;
    parameter pRst_Vector = 16'hFFFC;
    parameter pIRQ_Vector = 16'hFFFE;
    parameter pBrk_Vector = 16'hFFFE;
 
    parameter pInt_Hndlr  = 9'h021;
 
    parameter pIRQ_On     = 16'hFFF8;
    parameter pIRQ_Off    = 16'hFFF9;
 
    parameter pIO_WR      = 2'b01;
 
    parameter pRAM_AddrWidth = 11;
 
    // System
 
    reg  Rst;                   // System Reset
    reg  Clk;                   // System Clock
 
    //  Processor
 
    wire IRQ_Msk;               // Interrupt Mask Bit from P
    reg  Int;                   // Interrupt Request
    reg  xIRQ;                  // Maskable Interrupt Request
    reg  [15:0] Vector;         // Interrupt Vector
 
    wire Done;                  // Instruction Complete
    wire SC;                    // Single Cycle Instruction
    wire [2:0] Mode;            // Instruction Type/Mode
    wire RMW;                   // Read-Modify-Write Operation
    wire IntSvc;                // Interrupt Service Start
    wire ISR;                   // Interrupt Vector Pull Start
 
    wire [1:0] MC;              // Microcycle State
    wire [1:0] MemTyp;          // Memory Access Type
    reg  Wait;                  // Microcycle Wait State Request
    wire Rdy;                   // Internal Ready
 
    wire [1:0] IO_Op;           // Bus Operation: 1 - WR; 2 - RD; 3 - IF
 
    wire [15:0] AO;             // Address Output Bus
    wire [ 7:0] DI;             // Data Input Bus
    wire [ 7:0] DO;             // Data Output Bus
 
        wire [ 7:0] A;              // Internal Register - Accumulator
        wire [ 7:0] X;              // Internal Register - Pre-Index Register X
        wire [ 7:0] Y;              // Internal Register - Post-Index Register Y
        wire [ 7:0] S;              // Internal Register - Stack Pointer
        wire [ 7:0] P;              // Internal Register - Program Status Word
        wire [15:0] PC;             // Internal Register - Program Counter
 
        wire [7:0] IR;              // Internal Register - Instruction Register
        wire [7:0] OP1;             // Internal Register - Operand Register 1
        wire [7:0] OP2;             // Internal Register - Operand Register 2
 
    // Simulation Variables
 
    wire    Phi1O, Phi2O;           // M65C02 Clock Outputs
    reg     [1:0] VP, Ref_VP;       // Vector Pull FFs
    wire    nVP;
 
    reg     nWr;
 
    reg     Sim_Int    = 0;
 
    integer cycle_cnt  = 0;
    integer instr_cnt  = 0;
 
    integer Loop_Start = 0;         // Flags the first loop
 
    integer Hist_File  = 0;         // File handle for instruction histogram
    integer SV_Output  = 0;         // File handle for State Vector Outputs
 
    reg     [15:0] Hist [255:0];    // Instruction Histogram array
    reg     [15:0] val;             // Instruction Histogram variable
    reg     [ 7:0] i, j;            // loop counters
 
    reg     [((5*8) - 1):0] Op;     // Processor Mode Mnemonics String
    reg     [((6*8) - 1):0] Opcode; // Opcode Mnemonics String
    reg     [((9*8) - 1):0] AddrMd; // Addressing Mode Mnemonics String
 
// Instantiate the Unit Under Test (UUT)
 
M65C02_Core #(
                .pInt_Hndlr(pInt_Hndlr),
                .pM65C02_uPgm("M65C02_uPgm_V3a.coe"),
                .pM65C02_IDec("M65C02_Decoder_ROM.coe")
            ) uut (
            .Rst(Rst),
            .Clk(Clk),
 
            .IRQ_Msk(IRQ_Msk),
            .Int(Int),
            .xIRQ(xIRQ),
            .Vector(Vector),
 
            .Done(Done),
            .SC(SC),
            .Mode(Mode),
            .RMW(RMW),
            .IntSvc(IntSvc),
            .ISR(ISR),
 
            .MC(MC),
            .MemTyp(MemTyp),
            .uLen(2'b11),     // Len 4 Cycle 
//            .uLen(2'b1),      // Len 2 Cycle 
//            .uLen(2'b0),      // Len 1 Cycle
            .Wait(Wait),
            .Rdy(Rdy),
 
            .IO_Op(IO_Op),
            .AO(AO),
            .DI(DI),
            .DO(DO),
 
            .A(A),
            .X(X),
            .Y(Y),
            .S(S),
            .P(P),
            .PC(PC),
 
            .IR(IR),
            .OP1(OP1),
            .OP2(OP2)
        );
 
// Instantiate the Reference Unit for Unit Under Test
 
    //  Processor
 
    wire Ref_IRQ_Msk;           // Interrupt Mask Bit from P
 
    wire Ref_Done;              // Instruction Complete
    wire Ref_SC;                // Single Cycle Instruction
    wire [2:0] Ref_Mode;        // Instruction Type/Mode
    wire Ref_RMW;               // Read-Modify-Write Operation
    wire Ref_IntSvc;            // Interrupt Service Start
    wire Ref_ISR;               // Interrupt Pull Start Flag
 
    wire Ref_Rdy;               // Internal Ready
 
    wire [1:0] Ref_IO_Op;       // Bus Operation: 1 - WR; 2 - RD; 3 - IF
    reg  Ref_Ack;               // External Transfer Acknowledge
 
    wire [15:0] Ref_AO;         // Address Output Bus
    wire [ 7:0] Ref_DO;         // Data Output Bus
 
        wire [ 7:0] Ref_A;          // Internal Register - Accumulator
        wire [ 7:0] Ref_X;          // Internal Register - Pre-Index Register X
        wire [ 7:0] Ref_Y;          // Internal Register - Post-Index Register Y
        wire [ 7:0] Ref_S;          // Internal Register - Stack Pointer
        wire [ 7:0] Ref_P;          // Internal Register - Program Status Word
        wire [15:0] Ref_PC;         // Internal Register - Program Counter
 
        wire [7:0] Ref_IR;          // Internal Register - Instruction Register
        wire [7:0] Ref_OP1;         // Internal Register - Operand Register 1
        wire [7:0] Ref_OP2;         // Internal Register - Operand Register 2
 
M65C02_Base #(
                .pInt_Hndlr(pInt_Hndlr),
                .pM65C02_uPgm("M65C02_uPgm_V3.coe"),
                .pM65C02_IDec("M65C02_Decoder_ROM.coe")
            ) ref (
            .Rst(Rst),
            .Clk(Clk),
 
            .IRQ_Msk(Ref_IRQ_Msk),
            .Int(Int),
            .xIRQ(xIRQ),
            .Vector(Vector),
 
            .Done(Ref_Done),
            .SC(Ref_SC),
            .Mode(Ref_Mode),
            .RMW(Ref_RMW),
            .IntSvc(Ref_IntSvc),
            .ISR(Ref_ISR),
 
            .Rdy(Ref_Rdy),
 
            .IO_Op(Ref_IO_Op),
            .Ack_In(Ref_Ack),
 
            .AO(Ref_AO),
            .DI(DI),
            .DO(Ref_DO),
 
            .A(Ref_A),
            .X(Ref_X),
            .Y(Ref_Y),
            .S(Ref_S),
            .P(Ref_P),
            .PC(Ref_PC),
 
            .IR(Ref_IR),
            .OP1(Ref_OP1),
            .OP2(Ref_OP2)
        );
 
//  Instantiate RAM Module
 
wire    [7:0] ROM_DO;
reg     ROM_WE;
 
M65C02_RAM  #(
                .pAddrSize(pRAM_AddrWidth),
                .pDataSize(8),
                .pFileName("M65C02_Tst3.txt")
            ) ROM (
                .Clk(Clk),
                .Ext(1'b1),     // 4 cycle memory
                .ZP(1'b0),
//                .Ext(1'b0),     // 2 cycle memory
//                .ZP(1'b0),
//                .Ext(1'b0),     // 1 cycle memory
//                .ZP(1'b1),
                .WE(ROM_WE),
                .AI(AO[(pRAM_AddrWidth - 1):0]),
                .DI(DO),
                .DO(ROM_DO)
            );
 
//  Instantiate RAM Module
 
wire    [7:0] RAM_DO;
reg     RAM_WE;
 
M65C02_RAM  #(
                .pAddrSize(pRAM_AddrWidth),
                .pDataSize(8),
                .pFileName("M65C02_RAM.txt")
            ) RAM (
                .Clk(Clk),
                .Ext(1'b1),     // 4 cycle memory
                .ZP(1'b0),
//                .Ext(1'b0),     // 2 cycle memory
//                .ZP(1'b0),
//                .Ext(1'b0),     // 1 cycle memory
//                .ZP(1'b1),
                .WE(RAM_WE),
                .AI(AO[(pRAM_AddrWidth - 1):0]),
                .DI(DO),
                .DO(RAM_DO)
            );
 
initial begin
    // Initialize Inputs
    Rst    = 1;
    Clk    = 1;
    Int    = 0;
    Wait   = 0;
    Vector = pRst_Vector;
 
    // Intialize Simulation Time Format
 
    $timeformat (-9, 3, " ns", 12);
 
    //  Initialize Instruction Execution Histogram array
 
    for(cycle_cnt = 0; cycle_cnt < 256; cycle_cnt = cycle_cnt + 1)
        Hist[cycle_cnt] = 0;
    cycle_cnt = 0;
 
    Hist_File = $fopen("M65C02_Hist_File.txt", "w");
    SV_Output = $fopen("M65C02_SV_Output.txt", "w");
 
    // Wait 100 ns for global reset to finish
 
    #101 Rst = 0;
 
    // Add stimulus here
 
end
 
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//  Clocks
//
 
always #5 Clk = ~Clk;
 
assign Phi1O =  MC[1];
assign Phi2O = ~MC[1];
 
////////////////////////////////////////////////////////////////////////////////
//
//  Generate Bus Control Signals
//
 
assign C1 =  (MC == 2);
assign C2 =   MC[1];
assign C3 =  |MC;
assign C4 = ~|MC;
 
assign WE = ~IO_Op[1] & IO_Op[0] & ~C4;
assign RE =  IO_Op[1];
 
always @(negedge Clk) nWr <= #1 ((Rst) ? 1 : ~WE);
 
////////////////////////////////////////////////////////////////////////////////
//
//  Generate Vector Pull signals
//
 
always @(posedge Clk)
begin
    if(Rst)
        VP <= #1 0;
    else if(Rdy)
        VP <= #1 ((ISR) ? 2'b11 : {VP[0], 1'b0});
end
 
assign nVP = ~VP[1];
 
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//  Generate Write Enables for "ROM" and "RAM" modules and multiplex DO onto DI
//
 
always @(*) ROM_WE = (IO_Op == 1) & ( &AO[15:pRAM_AddrWidth]);
always @(*) RAM_WE = (IO_Op == 1) & (~|AO[15:pRAM_AddrWidth]);
 
assign DI = ((&AO[15:pRAM_AddrWidth]) ? ROM_DO : RAM_DO);
 
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//  Generate Ack for Reference Core - M65C02_Base
//
 
always @(*) Ref_Ack = (MC == 0);
 
///////////////////////////////////////////////////////////////////////////////
//
//  Reset/NMI/Brk/IRQ Vector Generator
//
 
always @(*)
begin
    Vector = ((Mode == 3'b010) ? pBrk_Vector
                               : ((Int) ? pIRQ_Vector
                                        : pRst_Vector));
end
 
// Simulate Interrupts
 
always @(*)
begin
    if((AO == pIRQ_On) && (IO_Op == pIO_WR))
        Sim_Int = 1;
    else if((AO == pIRQ_Off) && (IO_Op == pIO_WR))
        Sim_Int = 0;
end
 
always @(*)
begin
    Int  = ((IRQ_Msk) ? 0 : (Sim_Int | (Mode == 3'b111)));
    xIRQ = (Mode == 3'b111);
end
 
//  Count number of cycles and the number of instructions between between
//      0x0210 and the repeat at 0x0210 
 
always @(posedge Clk)
begin
    if(Rst)
        cycle_cnt = 0;
    else
        cycle_cnt = ((Done & (AO == 16'h0210)) ? 1 : (cycle_cnt + 1));
end
 
always @(posedge Clk)
begin
    if(Rst)
        instr_cnt = 0;
    else if(Done & Rdy)
        instr_cnt = ((AO == 16'h0210) ? 1 : (instr_cnt + 1));
end
 
//  Perform Instruction Histogramming for coverage puposes
 
always @(posedge Clk)
begin
    $fstrobe(SV_Output, "%b, %b, %b, %h, %b, %b, %h, %b, %b, %b, %h, %b, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h",
             IRQ_Msk, Sim_Int, Int, Vector, Done, SC, Mode, RMW, IntSvc, Rdy, IO_Op, Ref_Ack, AO, DI, DO, A, X, Y, S, P, PC, IR, OP1, OP2);
 
    if(Done & Rdy) begin
        if((AO == 16'hF800)) begin
            if((Loop_Start == 1)) begin
                for(i = 0; i < 16; i = i + 1)
                    for(j = 0; j < 16; j = j + 1) begin
                        val = Hist[(j * 16) + i];
                        Hist[(j * 16) + i] = 0;
                        if((j == 0))
                            $fwrite(Hist_File, "\n%h : %h", ((j * 16) + i), val);
                        else
                            $fwrite(Hist_File, " %h", val);
                    end
                $fclose(Hist_File);
                $fclose(SV_Output);
 
                $display("\nTest Loop Complete\n");
 
                $stop;
            end else begin
                Loop_Start = 1;
            end
        end
        val = Hist[IR];
        Hist[IR] = val + 1;
    end
end
 
//  Test Monitor System Function
 
always @(*)
begin
    $monitor("%b, %b, %b, %h, %b, %b, %h, %b, %b, %b, %h, %b, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h",
             IRQ_Msk, Sim_Int, Int, Vector, Done, SC, Mode, RMW, IntSvc, Rdy, IO_Op, Ref_Ack, AO, DI, DO, A, X, Y, S, P, PC, IR, OP1, OP2);
end
 
//  Compare UUT to REF, and pause simulation when differences encountered
 
always @(posedge Clk)
begin
    #1.1;
    if(Ref_IRQ_Msk != IRQ_Msk) begin
        $display("\tError(%t): IRQ_Msk incorrect - found %b; expected %b\n", $realtime, IRQ_Msk, Ref_IRQ_Msk);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_Done != Done) begin
        $display("\tError(%t): Done incorrect - found %b; expected %b\n", $realtime, Done, Ref_Done);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_SC != SC) begin
        $display("\tError(%t): SC incorrect - found %b; expected %b\n", $realtime, SC, Ref_SC);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_Mode != Mode) begin
        $display("\tError(%t): Mode incorrect - found %h; expected %h\n", $realtime, Mode, Ref_Mode);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_RMW != RMW) begin
        $display("\tError(%t): RMW incorrect - found %b; expected %b\n", $realtime, RMW, Ref_RMW);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_IntSvc != IntSvc) begin
        $display("\tError(%t): IntSvc incorrect - found %b; expected %b\n", $realtime, IntSvc, Ref_IntSvc);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_Rdy != Rdy) begin
        $display("\tError(%t): Rdy incorrect - found %b; expected %b\n", $realtime, Rdy, Ref_Rdy);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_IO_Op != IO_Op) begin
        $display("\tError(%t): IO_Op incorrect - found %d; expected %d\n", $realtime, IO_Op, Ref_IO_Op);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_AO != AO) begin
        $display("\tError(%t): AO incorrect - found %h; expected %h\n", $realtime, AO, Ref_AO);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_DO != DO) begin
        $display("\tError(%t): DO incorrect - found %h; expected %h\n", $realtime, DO, Ref_DO);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_A != A) begin
        $display("\tError(%t): A incorrect - found %h; expected %h\n", $realtime, A, Ref_A);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_X != X) begin
        $display("\tError(%t): X incorrect - found %h; expected %h\n", $realtime, X, Ref_X);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_Y != Y) begin
        $display("\tError(%t): Y incorrect - found %h; expected %h\n", $realtime, Y, Ref_Y);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_S != S) begin
        $display("\tError(%t): S incorrect - found %h; expected %h\n", $realtime, S, Ref_S);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_P != P) begin
        $display("\tError(%t): P incorrect - found %h; expected %h\n", $realtime, P, Ref_P);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_PC != PC) begin
        $display("\tError(%t): PC incorrect - found %h; expected %h\n", $realtime, PC, Ref_PC);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_IR != IR) begin
        $display("\tError(%t): IR incorrect - found %h; expected %h\n", $realtime, IR, Ref_IR);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_OP1 != OP1) begin
        $display("\tError(%t): OP1 incorrect - found %h; expected %h\n", $realtime, OP1, Ref_OP1);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end else if(Ref_OP2 != OP2) begin
        $display("\tError(%t): OP2 incorrect - found %h; expected %h\n", $realtime, OP2, Ref_OP2);
        @(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);
        $stop;
    end
end
 
////////////////////////////////////////////////////////////////////////////////
 
`include "M65C02_Mnemonics.txt"
 
endmodule

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Subversion Repositories m65c02

[/] [m65c02/] [trunk/] [Sim/] [tb_M65C02_Core.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	MichaelA	`///////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Copyright 2012 by Michael A. Morris, dba M. A. Morris & Associates`
4			`//`
5			`// All rights reserved. The source code contained herein is publicly released`
6			`// under the terms and conditions of the GNU Lesser Public License. No part of`
7			`// this source code may be reproduced or transmitted in any form or by any`
8			`// means, electronic or mechanical, including photocopying, recording, or any`
9			`// information storage and retrieval system in violation of the license under`
10			`// which the source code is released.`
11			`//`
12			`// The source code contained herein is free; it may be redistributed and/or`
13			`// modified in accordance with the terms of the GNU Lesser General Public`
14			`// License as published by the Free Software Foundation; either version 2.1 of`
15			`// the GNU Lesser General Public License, or any later version.`
16			`//`
17			`// The source code contained herein is freely released WITHOUT ANY WARRANTY;`
18			`// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A`
19			`// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for`
20			`// more details.)`
21			`//`
22			`// A copy of the GNU Lesser General Public License should have been received`
23			`// along with the source code contained herein; if not, a copy can be obtained`
24			`// by writing to:`
25			`//`
26			`// Free Software Foundation, Inc.`
27			`// 51 Franklin Street, Fifth Floor`
28			`// Boston, MA 02110-1301 USA`
29			`//`
30			`// Further, no use of this source code is permitted in any form or means`
31			`// without inclusion of this banner prominently in any derived works.`
32			`//`
33			`// Michael A. Morris`
34			`// Huntsville, AL`
35			`//`
36			`///////////////////////////////////////////////////////////////////////////////`
37
38			`timescale 1ns / 1ps
39
40			`///////////////////////////////////////////////////////////////////////////////`
41			`// Company: M. A. Morris & Associates`
42			`// Engineer: Michael A. Morris`
43			`//`
44			`// Create Date: 21:38:27 02/04/2012`
45			`// Design Name: M65C02_Core - WDC W65C02 Microprocessor Re-Implementation`
46			`// Module Name: tb_MAM65C02_Core.v`
47			`// Project Name: C:/XProjects/ISE10.1i/MAM6502`
48			`// Target Device: XC3S200AN-4FT256I`
49			`// Tool versions: Xilinx ISE 10.1i SP3`
50			`//`
51			`// Description:`
52			`//`
53			`// Verilog Test Fixture created by ISE for module: M65C02_Core`
54			`//`
55			`// Dependencies:`
56			`//`
57			`// Revision:`
58			`//`
59			`// 0.01 12B04 MAM Initial coding.`
60			`//`
61			`// Additional Comments:`
62			`//`
63			`///////////////////////////////////////////////////////////////////////////////`
64
65			`module tb_M65C02_Core;`
66
67			`// parameter pRst_Vector = 16'hF800;`
68			`// parameter pIRQ_Vector = 16'hF808;`
69			`// parameter pBrk_Vector = 16'hF808;`
70			`parameter pRst_Vector = 16'hFFFC;`
71			`parameter pIRQ_Vector = 16'hFFFE;`
72			`parameter pBrk_Vector = 16'hFFFE;`
73
74			`parameter pInt_Hndlr = 9'h021;`
75
76			`parameter pIRQ_On = 16'hFFF8;`
77			`parameter pIRQ_Off = 16'hFFF9;`
78
79			`parameter pIO_WR = 2'b01;`
80
81			`parameter pRAM_AddrWidth = 11;`
82
83			`// System`
84
85			`reg Rst; // System Reset`
86			`reg Clk; // System Clock`
87
88			`// Processor`
89
90			`wire IRQ_Msk; // Interrupt Mask Bit from P`
91			`reg Int; // Interrupt Request`
92			`reg xIRQ; // Maskable Interrupt Request`
93			`reg [15:0] Vector; // Interrupt Vector`
94
95			`wire Done; // Instruction Complete`
96			`wire SC; // Single Cycle Instruction`
97			`wire [2:0] Mode; // Instruction Type/Mode`
98			`wire RMW; // Read-Modify-Write Operation`
99			`wire IntSvc; // Interrupt Service Start`
100			`wire ISR; // Interrupt Vector Pull Start`
101
102			`wire [1:0] MC; // Microcycle State`
103			`wire [1:0] MemTyp; // Memory Access Type`
104			`reg Wait; // Microcycle Wait State Request`
105			`wire Rdy; // Internal Ready`
106
107			`wire [1:0] IO_Op; // Bus Operation: 1 - WR; 2 - RD; 3 - IF`
108
109			`wire [15:0] AO; // Address Output Bus`
110			`wire [ 7:0] DI; // Data Input Bus`
111			`wire [ 7:0] DO; // Data Output Bus`
112
113			`wire [ 7:0] A; // Internal Register - Accumulator`
114			`wire [ 7:0] X; // Internal Register - Pre-Index Register X`
115			`wire [ 7:0] Y; // Internal Register - Post-Index Register Y`
116			`wire [ 7:0] S; // Internal Register - Stack Pointer`
117			`wire [ 7:0] P; // Internal Register - Program Status Word`
118			`wire [15:0] PC; // Internal Register - Program Counter`
119
120			`wire [7:0] IR; // Internal Register - Instruction Register`
121			`wire [7:0] OP1; // Internal Register - Operand Register 1`
122			`wire [7:0] OP2; // Internal Register - Operand Register 2`
123
124			`// Simulation Variables`
125
126			`wire Phi1O, Phi2O; // M65C02 Clock Outputs`
127			`reg [1:0] VP, Ref_VP; // Vector Pull FFs`
128			`wire nVP;`
129
130			`reg nWr;`
131
132			`reg Sim_Int = 0;`
133
134			`integer cycle_cnt = 0;`
135			`integer instr_cnt = 0;`
136
137			`integer Loop_Start = 0; // Flags the first loop`
138
139			`integer Hist_File = 0; // File handle for instruction histogram`
140			`integer SV_Output = 0; // File handle for State Vector Outputs`
141
142			`reg [15:0] Hist [255:0]; // Instruction Histogram array`
143			`reg [15:0] val; // Instruction Histogram variable`
144			`reg [ 7:0] i, j; // loop counters`
145
146			`reg [((5*8) - 1):0] Op; // Processor Mode Mnemonics String`
147			`reg [((6*8) - 1):0] Opcode; // Opcode Mnemonics String`
148			`reg [((9*8) - 1):0] AddrMd; // Addressing Mode Mnemonics String`
149
150			`// Instantiate the Unit Under Test (UUT)`
151
152			`M65C02_Core #(`
153			`.pInt_Hndlr(pInt_Hndlr),`
154			`.pM65C02_uPgm("M65C02_uPgm_V3a.coe"),`
155			`.pM65C02_IDec("M65C02_Decoder_ROM.coe")`
156			`) uut (`
157			`.Rst(Rst),`
158			`.Clk(Clk),`
159
160			`.IRQ_Msk(IRQ_Msk),`
161			`.Int(Int),`
162			`.xIRQ(xIRQ),`
163			`.Vector(Vector),`
164
165			`.Done(Done),`
166			`.SC(SC),`
167			`.Mode(Mode),`
168			`.RMW(RMW),`
169			`.IntSvc(IntSvc),`
170			`.ISR(ISR),`
171
172			`.MC(MC),`
173			`.MemTyp(MemTyp),`
174			`.uLen(2'b11), // Len 4 Cycle`
175			`// .uLen(2'b1), // Len 2 Cycle`
176			`// .uLen(2'b0), // Len 1 Cycle`
177			`.Wait(Wait),`
178			`.Rdy(Rdy),`
179
180			`.IO_Op(IO_Op),`
181			`.AO(AO),`
182			`.DI(DI),`
183			`.DO(DO),`
184
185			`.A(A),`
186			`.X(X),`
187			`.Y(Y),`
188			`.S(S),`
189			`.P(P),`
190			`.PC(PC),`
191
192			`.IR(IR),`
193			`.OP1(OP1),`
194			`.OP2(OP2)`
195			`);`
196
197			`// Instantiate the Reference Unit for Unit Under Test`
198
199			`// Processor`
200
201			`wire Ref_IRQ_Msk; // Interrupt Mask Bit from P`
202
203			`wire Ref_Done; // Instruction Complete`
204			`wire Ref_SC; // Single Cycle Instruction`
205			`wire [2:0] Ref_Mode; // Instruction Type/Mode`
206			`wire Ref_RMW; // Read-Modify-Write Operation`
207			`wire Ref_IntSvc; // Interrupt Service Start`
208			`wire Ref_ISR; // Interrupt Pull Start Flag`
209
210			`wire Ref_Rdy; // Internal Ready`
211
212			`wire [1:0] Ref_IO_Op; // Bus Operation: 1 - WR; 2 - RD; 3 - IF`
213			`reg Ref_Ack; // External Transfer Acknowledge`
214
215			`wire [15:0] Ref_AO; // Address Output Bus`
216			`wire [ 7:0] Ref_DO; // Data Output Bus`
217
218			`wire [ 7:0] Ref_A; // Internal Register - Accumulator`
219			`wire [ 7:0] Ref_X; // Internal Register - Pre-Index Register X`
220			`wire [ 7:0] Ref_Y; // Internal Register - Post-Index Register Y`
221			`wire [ 7:0] Ref_S; // Internal Register - Stack Pointer`
222			`wire [ 7:0] Ref_P; // Internal Register - Program Status Word`
223			`wire [15:0] Ref_PC; // Internal Register - Program Counter`
224
225			`wire [7:0] Ref_IR; // Internal Register - Instruction Register`
226			`wire [7:0] Ref_OP1; // Internal Register - Operand Register 1`
227			`wire [7:0] Ref_OP2; // Internal Register - Operand Register 2`
228
229			`M65C02_Base #(`
230			`.pInt_Hndlr(pInt_Hndlr),`
231			`.pM65C02_uPgm("M65C02_uPgm_V3.coe"),`
232			`.pM65C02_IDec("M65C02_Decoder_ROM.coe")`
233			`) ref (`
234			`.Rst(Rst),`
235			`.Clk(Clk),`
236
237			`.IRQ_Msk(Ref_IRQ_Msk),`
238			`.Int(Int),`
239			`.xIRQ(xIRQ),`
240			`.Vector(Vector),`
241
242			`.Done(Ref_Done),`
243			`.SC(Ref_SC),`
244			`.Mode(Ref_Mode),`
245			`.RMW(Ref_RMW),`
246			`.IntSvc(Ref_IntSvc),`
247			`.ISR(Ref_ISR),`
248
249			`.Rdy(Ref_Rdy),`
250
251			`.IO_Op(Ref_IO_Op),`
252			`.Ack_In(Ref_Ack),`
253
254			`.AO(Ref_AO),`
255			`.DI(DI),`
256			`.DO(Ref_DO),`
257
258			`.A(Ref_A),`
259			`.X(Ref_X),`
260			`.Y(Ref_Y),`
261			`.S(Ref_S),`
262			`.P(Ref_P),`
263			`.PC(Ref_PC),`
264
265			`.IR(Ref_IR),`
266			`.OP1(Ref_OP1),`
267			`.OP2(Ref_OP2)`
268			`);`
269
270			`// Instantiate RAM Module`
271
272			`wire [7:0] ROM_DO;`
273			`reg ROM_WE;`
274
275			`M65C02_RAM #(`
276			`.pAddrSize(pRAM_AddrWidth),`
277			`.pDataSize(8),`
278			`.pFileName("M65C02_Tst3.txt")`
279			`) ROM (`
280			`.Clk(Clk),`
281			`.Ext(1'b1), // 4 cycle memory`
282			`.ZP(1'b0),`
283			`// .Ext(1'b0), // 2 cycle memory`
284			`// .ZP(1'b0),`
285			`// .Ext(1'b0), // 1 cycle memory`
286			`// .ZP(1'b1),`
287			`.WE(ROM_WE),`
288			`.AI(AO[(pRAM_AddrWidth - 1):0]),`
289			`.DI(DO),`
290			`.DO(ROM_DO)`
291			`);`
292
293			`// Instantiate RAM Module`
294
295			`wire [7:0] RAM_DO;`
296			`reg RAM_WE;`
297
298			`M65C02_RAM #(`
299			`.pAddrSize(pRAM_AddrWidth),`
300			`.pDataSize(8),`
301			`.pFileName("M65C02_RAM.txt")`
302			`) RAM (`
303			`.Clk(Clk),`
304			`.Ext(1'b1), // 4 cycle memory`
305			`.ZP(1'b0),`
306			`// .Ext(1'b0), // 2 cycle memory`
307			`// .ZP(1'b0),`
308			`// .Ext(1'b0), // 1 cycle memory`
309			`// .ZP(1'b1),`
310			`.WE(RAM_WE),`
311			`.AI(AO[(pRAM_AddrWidth - 1):0]),`
312			`.DI(DO),`
313			`.DO(RAM_DO)`
314			`);`
315
316			`initial begin`
317			`// Initialize Inputs`
318			`Rst = 1;`
319			`Clk = 1;`
320			`Int = 0;`
321			`Wait = 0;`
322			`Vector = pRst_Vector;`
323
324			`// Intialize Simulation Time Format`
325
326			`$timeformat (-9, 3, " ns", 12);`
327
328			`// Initialize Instruction Execution Histogram array`
329
330			`for(cycle_cnt = 0; cycle_cnt < 256; cycle_cnt = cycle_cnt + 1)`
331			`Hist[cycle_cnt] = 0;`
332			`cycle_cnt = 0;`
333
334			`Hist_File = $fopen("M65C02_Hist_File.txt", "w");`
335			`SV_Output = $fopen("M65C02_SV_Output.txt", "w");`
336
337			`// Wait 100 ns for global reset to finish`
338
339			`#101 Rst = 0;`
340
341			`// Add stimulus here`
342
343			`end`
344
345			`////////////////////////////////////////////////////////////////////////////////`
346			`////////////////////////////////////////////////////////////////////////////////`
347			`//`
348			`// Clocks`
349			`//`
350
351			`always #5 Clk = ~Clk;`
352
353			`assign Phi1O = MC[1];`
354			`assign Phi2O = ~MC[1];`
355
356			`////////////////////////////////////////////////////////////////////////////////`
357			`//`
358			`// Generate Bus Control Signals`
359			`//`
360
361			`assign C1 = (MC == 2);`
362			`assign C2 = MC[1];`
363			`assign C3 = \|MC;`
364			`assign C4 = ~\|MC;`
365
366			`assign WE = ~IO_Op[1] & IO_Op[0] & ~C4;`
367			`assign RE = IO_Op[1];`
368
369			`always @(negedge Clk) nWr <= #1 ((Rst) ? 1 : ~WE);`
370
371			`////////////////////////////////////////////////////////////////////////////////`
372			`//`
373			`// Generate Vector Pull signals`
374			`//`
375
376			`always @(posedge Clk)`
377			`begin`
378			`if(Rst)`
379			`VP <= #1 0;`
380			`else if(Rdy)`
381			`VP <= #1 ((ISR) ? 2'b11 : {VP[0], 1'b0});`
382			`end`
383
384			`assign nVP = ~VP[1];`
385
386			`////////////////////////////////////////////////////////////////////////////////`
387			`////////////////////////////////////////////////////////////////////////////////`
388			`//`
389			`// Generate Write Enables for "ROM" and "RAM" modules and multiplex DO onto DI`
390			`//`
391
392			`always @(*) ROM_WE = (IO_Op == 1) & ( &AO[15:pRAM_AddrWidth]);`
393			`always @(*) RAM_WE = (IO_Op == 1) & (~\|AO[15:pRAM_AddrWidth]);`
394
395			`assign DI = ((&AO[15:pRAM_AddrWidth]) ? ROM_DO : RAM_DO);`
396
397			`///////////////////////////////////////////////////////////////////////////////`
398			`///////////////////////////////////////////////////////////////////////////////`
399			`//`
400			`// Generate Ack for Reference Core - M65C02_Base`
401			`//`
402
403			`always @(*) Ref_Ack = (MC == 0);`
404
405			`///////////////////////////////////////////////////////////////////////////////`
406			`//`
407			`// Reset/NMI/Brk/IRQ Vector Generator`
408			`//`
409
410			`always @(*)`
411			`begin`
412			`Vector = ((Mode == 3'b010) ? pBrk_Vector`
413			`: ((Int) ? pIRQ_Vector`
414			`: pRst_Vector));`
415			`end`
416
417			`// Simulate Interrupts`
418
419			`always @(*)`
420			`begin`
421			`if((AO == pIRQ_On) && (IO_Op == pIO_WR))`
422			`Sim_Int = 1;`
423			`else if((AO == pIRQ_Off) && (IO_Op == pIO_WR))`
424			`Sim_Int = 0;`
425			`end`
426
427			`always @(*)`
428			`begin`
429			`Int = ((IRQ_Msk) ? 0 : (Sim_Int \| (Mode == 3'b111)));`
430			`xIRQ = (Mode == 3'b111);`
431			`end`
432
433			`// Count number of cycles and the number of instructions between between`
434			`// 0x0210 and the repeat at 0x0210`
435
436			`always @(posedge Clk)`
437			`begin`
438			`if(Rst)`
439			`cycle_cnt = 0;`
440			`else`
441			`cycle_cnt = ((Done & (AO == 16'h0210)) ? 1 : (cycle_cnt + 1));`
442			`end`
443
444			`always @(posedge Clk)`
445			`begin`
446			`if(Rst)`
447			`instr_cnt = 0;`
448			`else if(Done & Rdy)`
449			`instr_cnt = ((AO == 16'h0210) ? 1 : (instr_cnt + 1));`
450			`end`
451
452			`// Perform Instruction Histogramming for coverage puposes`
453
454			`always @(posedge Clk)`
455			`begin`
456			`$fstrobe(SV_Output, "%b, %b, %b, %h, %b, %b, %h, %b, %b, %b, %h, %b, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h",`
457			`IRQ_Msk, Sim_Int, Int, Vector, Done, SC, Mode, RMW, IntSvc, Rdy, IO_Op, Ref_Ack, AO, DI, DO, A, X, Y, S, P, PC, IR, OP1, OP2);`
458
459			`if(Done & Rdy) begin`
460			`if((AO == 16'hF800)) begin`
461			`if((Loop_Start == 1)) begin`
462			`for(i = 0; i < 16; i = i + 1)`
463			`for(j = 0; j < 16; j = j + 1) begin`
464			`val = Hist[(j * 16) + i];`
465			`Hist[(j * 16) + i] = 0;`
466			`if((j == 0))`
467			`$fwrite(Hist_File, "\n%h : %h", ((j * 16) + i), val);`
468			`else`
469			`$fwrite(Hist_File, " %h", val);`
470			`end`
471			`$fclose(Hist_File);`
472			`$fclose(SV_Output);`
473
474			`$display("\nTest Loop Complete\n");`
475
476			`$stop;`
477			`end else begin`
478			`Loop_Start = 1;`
479			`end`
480			`end`
481			`val = Hist[IR];`
482			`Hist[IR] = val + 1;`
483			`end`
484			`end`
485
486			`// Test Monitor System Function`
487
488			`always @(*)`
489			`begin`
490			`$monitor("%b, %b, %b, %h, %b, %b, %h, %b, %b, %b, %h, %b, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h",`
491			`IRQ_Msk, Sim_Int, Int, Vector, Done, SC, Mode, RMW, IntSvc, Rdy, IO_Op, Ref_Ack, AO, DI, DO, A, X, Y, S, P, PC, IR, OP1, OP2);`
492			`end`
493
494			`// Compare UUT to REF, and pause simulation when differences encountered`
495
496			`always @(posedge Clk)`
497			`begin`
498			`#1.1;`
499			`if(Ref_IRQ_Msk != IRQ_Msk) begin`
500			`$display("\tError(%t): IRQ_Msk incorrect - found %b; expected %b\n", $realtime, IRQ_Msk, Ref_IRQ_Msk);`
501			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
502			`$stop;`
503			`end else if(Ref_Done != Done) begin`
504			`$display("\tError(%t): Done incorrect - found %b; expected %b\n", $realtime, Done, Ref_Done);`
505			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
506			`$stop;`
507			`end else if(Ref_SC != SC) begin`
508			`$display("\tError(%t): SC incorrect - found %b; expected %b\n", $realtime, SC, Ref_SC);`
509			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
510			`$stop;`
511			`end else if(Ref_Mode != Mode) begin`
512			`$display("\tError(%t): Mode incorrect - found %h; expected %h\n", $realtime, Mode, Ref_Mode);`
513			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
514			`$stop;`
515			`end else if(Ref_RMW != RMW) begin`
516			`$display("\tError(%t): RMW incorrect - found %b; expected %b\n", $realtime, RMW, Ref_RMW);`
517			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
518			`$stop;`
519			`end else if(Ref_IntSvc != IntSvc) begin`
520			`$display("\tError(%t): IntSvc incorrect - found %b; expected %b\n", $realtime, IntSvc, Ref_IntSvc);`
521			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
522			`$stop;`
523			`end else if(Ref_Rdy != Rdy) begin`
524			`$display("\tError(%t): Rdy incorrect - found %b; expected %b\n", $realtime, Rdy, Ref_Rdy);`
525			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
526			`$stop;`
527			`end else if(Ref_IO_Op != IO_Op) begin`
528			`$display("\tError(%t): IO_Op incorrect - found %d; expected %d\n", $realtime, IO_Op, Ref_IO_Op);`
529			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
530			`$stop;`
531			`end else if(Ref_AO != AO) begin`
532			`$display("\tError(%t): AO incorrect - found %h; expected %h\n", $realtime, AO, Ref_AO);`
533			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
534			`$stop;`
535			`end else if(Ref_DO != DO) begin`
536			`$display("\tError(%t): DO incorrect - found %h; expected %h\n", $realtime, DO, Ref_DO);`
537			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
538			`$stop;`
539			`end else if(Ref_A != A) begin`
540			`$display("\tError(%t): A incorrect - found %h; expected %h\n", $realtime, A, Ref_A);`
541			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
542			`$stop;`
543			`end else if(Ref_X != X) begin`
544			`$display("\tError(%t): X incorrect - found %h; expected %h\n", $realtime, X, Ref_X);`
545			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
546			`$stop;`
547			`end else if(Ref_Y != Y) begin`
548			`$display("\tError(%t): Y incorrect - found %h; expected %h\n", $realtime, Y, Ref_Y);`
549			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
550			`$stop;`
551			`end else if(Ref_S != S) begin`
552			`$display("\tError(%t): S incorrect - found %h; expected %h\n", $realtime, S, Ref_S);`
553			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
554			`$stop;`
555			`end else if(Ref_P != P) begin`
556			`$display("\tError(%t): P incorrect - found %h; expected %h\n", $realtime, P, Ref_P);`
557			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
558			`$stop;`
559			`end else if(Ref_PC != PC) begin`
560			`$display("\tError(%t): PC incorrect - found %h; expected %h\n", $realtime, PC, Ref_PC);`
561			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
562			`$stop;`
563			`end else if(Ref_IR != IR) begin`
564			`$display("\tError(%t): IR incorrect - found %h; expected %h\n", $realtime, IR, Ref_IR);`
565			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
566			`$stop;`
567			`end else if(Ref_OP1 != OP1) begin`
568			`$display("\tError(%t): OP1 incorrect - found %h; expected %h\n", $realtime, OP1, Ref_OP1);`
569			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
570			`$stop;`
571			`end else if(Ref_OP2 != OP2) begin`
572			`$display("\tError(%t): OP2 incorrect - found %h; expected %h\n", $realtime, OP2, Ref_OP2);`
573			`@(posedge Clk); @(posedge Clk); @(posedge Clk); @(posedge Clk);`
574			`$stop;`
575			`end`
576			`end`
577
578			`////////////////////////////////////////////////////////////////////////////////`
579
580			`include "M65C02_Mnemonics.txt"
581
582			`endmodule`