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header
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Project: M65C02_Decoder_ROM
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File Revision: 0015
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Author(s): Michael A. Morris
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Description: M65C02 Instruction Decoder ROM
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endh
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--------------------------------------------------------------------------------
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--
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-- Copyright 2011-2012 by Michael A. Morris, dba M. A. Morris & Associates
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--
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-- All rights reserved. The source code contained herein is publicly released
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-- under the terms and conditions of the GNU Lesser Public License. No part of
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-- this source code may be reproduced or transmitted in any form or by any
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-- means, electronic or mechanical, including photocopying, recording, or any
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-- information storage and retrieval system in violation of the license under
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-- which the source code is released.
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--
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-- The source code contained herein is free; it may be redistributed and/or
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-- modified in accordance with the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either version 2.1 of
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-- the GNU Lesser General Public License, or any later version.
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--
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-- The source code contained herein is freely released WITHOUT ANY WARRANTY;
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-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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-- PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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-- more details.)
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--
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-- A copy of the GNU Lesser General Public License should have been received
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-- along with the source code contained herein; if not, a copy can be obtained
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-- by writing to:
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--
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-- Free Software Foundation, Inc.
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-- 51 Franklin Street, Fifth Floor
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-- Boston, MA 02110-1301 USA
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--
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-- Further, no use of this source code is permitted in any form or means
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-- without inclusion of this banner prominently in any derived works.
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--
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-- Michael A. Morris
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-- Huntsville, AL
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Revision History:
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--------------------------------------------------------------------------------
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--
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-- 0001 11D17 mam Initial development
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--
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-- 0002 11E14 mam Completed capture of MAM65C02 Instruction Decoder
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--
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-- 0003 11E28 mam Added Direct Page Relative addressing mode to tables
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--
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-- 0004 11K27 mam Changed number of operands for BRK instruction from
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-- 0 to 1, which will account for the fact that the
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-- return address pushed on the stack is $+2 instead of
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-- $+1 as would be the case if the byte after BRK was
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-- not treated as an operand.
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--
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-- 0005 12A21 mam Updated the instruction decoder so that the decoded
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-- addressing mode accounts for RO, WO, and RMW opera-
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-- tions. RO modes only read memory, WO modes only
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-- write to memory, and RMW modes perform operations on
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-- operands stored in memory. Renamed the various
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-- addressing modes so that it is easier to understand
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-- what is required for each addressing mode. Made some
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-- corrections to the instruction decode tables where
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-- incorrect addressing modes were being used for some
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-- instructions. Since DP,rel mode is not being imple-
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-- mented at this time, moved to the end of the decode
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-- table. Table increased from 29 to 37 distinct micro-
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-- program routines.
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--
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-- 0006 12A28 mam Changed the microword format. Deleted field indica-
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-- the number of operands, and replaced with single bit
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-- field that controls the selection of the index reg.
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--
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-- 0007 12B04 mam Changed the microword format. Replaced index regis-
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-- ter select field with Read-Modify-Write field.
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--
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-- 0008 12B18 mam Corrected CCSel field for most of the INC/DEC/INX/
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-- DEX/INY/DEY instructions. Most were set to update
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-- the N, Z, and C bits, when only N, Z are updated by
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-- these instructions. Similarly, corrected the CC bits
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-- updated by BIT instructions. Bit imm only updates Z,
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-- while the others update N, V, and Z.
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--
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-- 0009 12B19 mam Added missing instruction: STZ dp,X
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--
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-- 0010 12B20 mam Added WS_P to write field of all opcodes which modi-
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-- fy status bits in P, if a write to a internal regis-
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-- ter not already filled for the Write Select field.
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-- This is expected to preclude a change in the new
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-- register write enable decode logic that would add in
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-- an update to P whenever the CCSel field is in the
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-- appropriate range of values. This provides direct
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-- control, through the M65C02_ALU decoder, of updates
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-- to the processor status word.
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--
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-- 0011 12B23 mam Corrected incorrectly coded microword for NOP_1F.
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-- The ALU Op field was not set to XFR as it should
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-- have been.
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--
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-- 0012 12C04 mam Corrected two entries: ora (dp) and sta (dp),y. The
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-- first had an AND operation programmed instead of an
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-- ORA. The second was typed in as an sty (dp),y, so
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-- the output select field was set for Y instead of A.
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--
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-- 0013 12K17 mam RMW flag not set for INC and DEC instructions.
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--
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-- 0014 12L09 mam Change definitions of Mode to add STP and WAI. Up-
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-- dated Mode fields for JMP, and added the STP/WAI
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-- instructions. Corrected the mode of the PLA instruc-
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-- tion from INT to STK.
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--
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-- 0015 12L13 mam Completed addition of the Rockwell RMBx, SMBx, BBRx,
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-- and BBSx instruction. All 32 opcodes added into the
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-- instruction decode, and RMBx and SMBX marked as RMW.
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--
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--------------------------------------------------------------------------------
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-- Instruction (Next Address and Data) Field
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--------------------------------------------------------------------------------
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STP .asm 0 -- Stop Processor Instruction
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INV .asm 1 -- Invalid Instruction
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BRK .asm 2 -- BRK Instruction/Trap/Interrupt
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JMP .asm 3 -- Bcc/JMP/JSR/RTS/RTI Instruction
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STK .asm 4 -- Stack Operation Instruction (PLx/PHx)
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INT .asm 5 -- Internal Operation Instruction
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MEM .asm 6 -- Memory Operation Instruction
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WAI .asm 7 -- Waiting for Interrupt Instruction (NMI/IRQ)
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--------------------------------------------------------------------------------
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-- ROM ( output ) Field definitions
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--------------------------------------------------------------------------------
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Inst .def 3 -- Instruction (Addressing Mode)
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RMW .def 1 -- Read-Modify-Write Instruction Type Field
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ALU_OP .def 4 -- ALU Operation
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QSel .def 2 -- ALU Q Operand Select
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RSel .def 1 -- ALU R Operand Select
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AU_Mode .def 1 -- ALU Arithmetic Unit Mode (1 : Subtraction)
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CSel .def 1 -- ALU Arithmetic Unit Carry Input Select
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WSel .def 3 -- ALU Register Write Select
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OSel .def 3 -- ALU Register Output Select
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CCSel .def 5 -- ALU Condition Code Operation
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Opcode .def 8 -- Instruction Opcode
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--------------------------------------------------------------------------------
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-- Constant definitions
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- ALU Operation Field (ALU_Op) Definitions
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XFR .equ 0 -- ALU <= {OSel: 0, A, X, Y, P, S, M}
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-- Logic Unit Operations
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AND .equ 1 -- ALU <= A & M; N <= ALU[7]; Z <= ~|ALU;
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ORA .equ 2 -- ALU <= A | M; N <= ALU[7]; Z <= ~|ALU;
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EOR .equ 3 -- ALU <= A ^ M; N <= ALU[7]; Z <= ~|ALU;
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-- Arithmetic Unit Operations
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ADC .equ 4 -- ALU <= Q + M + C; N <= ALU[7]; Z <= ~|ALU;
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-- V <= OVF; C <= COut;
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SBC .equ 5 -- ALU <= Q + ~M + C; N <= ALU[7]; Z <= ~|ALU;
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-- V <= OVF; C <= COut;
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INC .equ 6 -- ALU <= Q + 1 + 0; N <= ALU[7]; Z <= ~|ALU;
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DEC .equ 7 -- ALU <= Q + ~1 + 1; N <= ALU[7]; Z <= ~|ALU;
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-- Shift Unit Operations
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ASL .equ 8 -- ALU <= R << 1; N <= ALU[6]; Z <= ~|ALU; C <= R[7]
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LSR .equ 9 -- ALU <= R >> 1; N <= 0; Z <= ~|ALU; C <= R[0]
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ROL .equ 10 -- ALU <= {R[6:0], C} N <= ALU[7]; Z <= ~|ALU; C <= R[7]
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ROR .equ 11 -- ALU <= {C, R[7:1]} N <= ALU[7]; Z <= ~|ALU; C <= R[0]
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-- Bit Unit Operations
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BIT .equ 12 -- ALU <= (A & M); N <= M[7]; Z <= ~|(A & M);
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-- V <= M[6];
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TRB .equ 13 -- ALU <= M & ~A; Z <= ~|(A & M);
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TSB .equ 14 -- ALU <= M | A; Z <= ~|(A & M);
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-- Arithmetic Unit Comparison Operation
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CMP .equ 15 -- ALU <= Q + ~M + 1 N <= ALU[7]; Z <= ~|ALU; C <= COut
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--------------------------------------------------------------------------------
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-- ALU Q Operand Select (default ALU Q Operand - A)
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--------------------------------------------------------------------------------
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QS_A .equ 0 -- Select A (default)
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QS_M .equ 1 -- Select M
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QS_X .equ 2 -- Select X
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QS_Y .equ 3 -- Select Y
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--------------------------------------------------------------------------------
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-- ALU R Operand Select: R <= (1) ? 8'h01 : M)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- ALU Arithmetic Unit Mode: Adder <= ((AU_Mode) ? Subtract : Add)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- ALU Carry Multiplexer Select: Ci <= ((CSel) ? AU_Mode : C)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- ALU Register Write Select Definitions
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WS_A .equ 1 -- Write Accumulator (Binary)
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WS_X .equ 2 -- Write X (Pre-Index Register)
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WS_Y .equ 3 -- Write Y (Post-Index Register)
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WS_S .equ 5 -- Write S (Stack Pointer)
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WS_P .equ 6 -- Write P (Processor Status Word)
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--------------------------------------------------------------------------------
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-- ALU Register Output Select Definitions
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OS_A .equ 1 -- Output Accumulator
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OS_X .equ 2 -- Output X
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OS_Y .equ 3 -- Output Y
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OS_Z .equ 4 -- Output Zero (0)
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OS_S .equ 5 -- Output S (Stack Pointer)
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OS_P .equ 6 -- Output P (Processor Status Word)
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OS_M .equ 7 -- Output M (Transfer)
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--------------------------------------------------------------------------------
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-- Condition Code Operation/Output Select Definitions
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-- Note: CC_Out = 1 unless ((CCSel[4:3] != 2'b01) | ((CCSel[4:1] == 3))
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SMBx .equ 4 -- Rockwell SMBx
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RMBx .equ 5 -- Rockwell RMBx
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BBSx .equ 6 -- Rockwell BBSx
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BBRx .equ 7 -- Rockwell BBRx
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--
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CC .equ 8 -- CC_Out = ~C;
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CS .equ 9 -- CC_Out = C;
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NE .equ 10 -- CC_Out = ~Z;
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EQ .equ 11 -- CC_Out = Z;
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VC .equ 12 -- CC_Out = ~V;
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VS .equ 13 -- CC_Out = V;
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PL .equ 14 -- CC_OUT = ~N;
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MI .equ 15 -- CC_Out = N;
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CLC .equ 16 -- C <= 0;
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SEC .equ 17 -- C <= 1;
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CLI .equ 18 -- I <= 0;
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SEI .equ 19 -- I <= 1;
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CLD .equ 20 -- D <= 0;
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SED .equ 21 -- D <= 1;
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CLV .equ 22 -- V <= 0;
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BRK .equ 23 -- B <= 1;
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Z .equ 24 -- Z <= ~|(A & M);
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NZ .equ 25 -- N <= ALU[7]; Z <= ~|ALU;
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NZC .equ 26 -- N <= ALU[7]; Z <= ~|ALU; C <= COut
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NVZ .equ 27 -- N <= M[7]; Z <= ~|(A & M); V <= M[6];
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NVZC .equ 28 -- N <= ALU[7]; Z <= ~|ALU; V <= OVF; C <= COut;
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-- .equ 29 -- Reserved
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-- .equ 30 -- Reserved
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PSW .equ 31 -- P <= M;
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--------------------------------------------------------------------------------
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_start: .org 0
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--------------------------------------------------------------------------------
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BRK 0,XFR,QS_A,0,0,0,WS_P, ,BRK ,0x00 -- 00: BRK #imm
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MEM 0,ORA,QS_A,0,0,0,WS_A, ,NZ ,0x01 -- 01: ORA (dp,X)
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INV 0,XFR,QS_A,0,0,0, , , ,0x02 -- 02: NOP
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INV 0,XFR,QS_A,0,0,0, , , ,0x03 -- 03: NOP
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MEM 1,TSB,QS_A,0,0,0,WS_P, ,Z ,0x04 -- 04: TSB dp
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MEM 0,ORA,QS_A,0,0,0,WS_A, ,NZ ,0x05 -- 05: ORA dp
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MEM 1,ASL,QS_M,0,0,0,WS_P, ,NZC ,0x06 -- 06: ASL dp
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MEM 1,XFR,QS_M,0,0,0, , ,RMBx,0xFE -- 07: RMB0 dp
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STK 0,XFR,QS_A,0,0,0, ,OS_P, ,0x08 -- 08: PHP
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MEM 0,ORA,QS_A,0,0,0,WS_A, ,NZ ,0x09 -- 09: ORA #imm
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INT 0,ASL,QS_A,0,0,0,WS_A, ,NZC ,0x0A -- 0A: ASL A
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INV 0,XFR,QS_A,0,0,0, , , ,0x0B -- 0B: NOP
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MEM 1,TSB,QS_A,0,0,0,WS_P, ,Z ,0x0C -- 0C: TSB abs
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MEM 0,ORA,QS_A,0,0,0,WS_A, ,NZ ,0x0D -- 0D: ORA abs
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MEM 1,ASL,QS_M,0,0,0,WS_P, ,NZC ,0x0E -- OE: ASL abs
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JMP 0,XFR,QS_M,0,0,0, , ,BBRx,0x01 -- 0F: BBR0 dp,rel
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--------------------------------------------------------------------------------
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JMP 0,XFR,QS_A,0,0,0, , ,PL ,0x10 -- 10: BPL rel
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MEM 0,ORA,QS_A,0,0,0,WS_A, ,NZ ,0x11 -- 11: ORA (dp),Y
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MEM 0,ORA,QS_A,0,0,0,WS_A, ,NZ ,0x12 -- 12: ORA (dp)
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INV 0,XFR,QS_A,0,0,0, , , ,0x13 -- 13: NOP
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MEM 1,TRB,QS_M,0,0,0,WS_P, ,Z ,0x14 -- 14: TRB dp
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MEM 0,ORA,QS_A,0,0,0,WS_A, ,NZ ,0x15 -- 15: ORA dp,X
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MEM 1,ASL,QS_M,0,0,0,WS_P, ,NZC ,0x16 -- 16: ASL dp,X
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MEM 1,XFR,QS_M,0,0,0, , ,RMBx,0xFD -- 17: RMB1 dp
|
| 300 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_P, ,CLC ,0x18 -- 18: CLC
|
| 301 |
|
|
MEM 0,ORA,QS_A,0,0,0,WS_A, ,NZ ,0x19 -- 19: ORA abs,Y
|
| 302 |
|
|
INT 0,INC,QS_A,1,0,1,WS_A, ,NZ ,0x1A -- 1A: INC A
|
| 303 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x1B -- 1B: NOP
|
| 304 |
|
|
MEM 1,TRB,QS_A,0,0,0,WS_P, ,Z ,0x1C -- 1C: TRB abs
|
| 305 |
|
|
MEM 0,ORA,QS_A,0,0,0,WS_A, ,NZ ,0x1D -- 1D: ORA abs,X
|
| 306 |
|
|
MEM 1,ASL,QS_M,0,0,0,WS_P, ,NZC ,0x1E -- 1E: ASL abs,X
|
| 307 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBRx,0x02 -- 1F: BBR1 dp,rel
|
| 308 |
|
|
|
| 309 |
|
|
--------------------------------------------------------------------------------
|
| 310 |
|
|
|
| 311 |
|
|
JMP 0,XFR,QS_A,0,0,0, , , ,0x20 -- 20: JSR abs
|
| 312 |
|
|
MEM 0,AND,QS_A,0,0,0,WS_A, ,NZ ,0x21 -- 21: AND (dp,X)
|
| 313 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x22 -- 22: NOP
|
| 314 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x23 -- 23: NOP
|
| 315 |
|
|
MEM 0,BIT,QS_A,0,0,0,WS_P, ,NVZ ,0x24 -- 24: BIT dp
|
| 316 |
|
|
MEM 0,AND,QS_A,0,0,0,WS_A, ,NZ ,0x25 -- 25: AND dp
|
| 317 |
|
|
MEM 1,ROL,QS_M,0,0,0,WS_P, ,NZC ,0x26 -- 26: ROL dp
|
| 318 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,RMBx,0xFB -- 27: RMB2 dp
|
| 319 |
|
|
STK 0,XFR,QS_A,0,0,0,WS_P, ,PSW ,0x28 -- 28: PLP
|
| 320 |
|
|
MEM 0,AND,QS_A,0,0,0,WS_A, ,NZ ,0x29 -- 29: AND #imm
|
| 321 |
|
|
INT 0,ROL,QS_A,0,0,0,WS_A, ,NZC ,0x2A -- 2A: ROL A
|
| 322 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x2B -- 2B: NOP
|
| 323 |
|
|
MEM 0,BIT,QS_A,0,0,0,WS_P, ,NVZ ,0x2C -- 2C: BIT abs
|
| 324 |
|
|
MEM 0,AND,QS_A,0,0,0,WS_A, ,NZ ,0x2D -- 2D: AND abs
|
| 325 |
|
|
MEM 1,ROL,QS_M,0,0,0,WS_P, ,NZC ,0x2E -- 2E: ROL abs
|
| 326 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBRx,0x04 -- 2F: BBR2 db,rel
|
| 327 |
|
|
|
| 328 |
|
|
--------------------------------------------------------------------------------
|
| 329 |
|
|
|
| 330 |
|
|
JMP 0,XFR,QS_A,0,0,0, , ,MI ,0x30 -- 30: BMI rel
|
| 331 |
|
|
MEM 0,AND,QS_A,0,0,0,WS_A, ,NZ ,0x31 -- 31: AND (dp),Y
|
| 332 |
|
|
MEM 0,AND,QS_A,0,0,0,WS_A, ,NZ ,0x32 -- 32: AND (dp)
|
| 333 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x33 -- 33: NOP
|
| 334 |
|
|
MEM 0,BIT,QS_A,0,0,0,WS_P, ,NVZ ,0x34 -- 34: BIT dp,X
|
| 335 |
|
|
MEM 0,AND,QS_A,0,0,0,WS_A, ,NZ ,0x35 -- 35: AND dp,X
|
| 336 |
|
|
MEM 1,ROL,QS_M,0,0,0,WS_P, ,NZC ,0x36 -- 36: ROL dp,X
|
| 337 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,RMBx,0xF7 -- 37: RMB3 dp
|
| 338 |
|
|
INT 0,AND,QS_A,0,0,0,WS_P, ,SEC ,0x38 -- 38: SEC
|
| 339 |
|
|
MEM 0,AND,QS_A,0,0,0,WS_A, ,NZ ,0x39 -- 39: AND abs,Y
|
| 340 |
|
|
INT 0,DEC,QS_A,1,1,1,WS_A, ,NZ ,0x3A -- 3A: DEC A
|
| 341 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x3B -- 3B: NOP
|
| 342 |
|
|
MEM 0,BIT,QS_A,0,0,0,WS_P, ,NVZ ,0x3C -- 3C: BIT abs,X
|
| 343 |
|
|
MEM 0,AND,QS_A,0,0,0,WS_A, ,NZ ,0x3D -- 3D: AND abs,X
|
| 344 |
|
|
MEM 1,ROL,QS_M,0,0,0,WS_P, ,NZC ,0x3E -- 3E: ROL abs,X
|
| 345 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBRx,0x08 -- 3F: BBR3 dp,rel
|
| 346 |
|
|
|
| 347 |
|
|
--------------------------------------------------------------------------------
|
| 348 |
|
|
|
| 349 |
|
|
JMP 0,XFR,QS_A,0,0,0,WS_P, ,PSW ,0x40 -- 40: RTI
|
| 350 |
|
|
MEM 0,EOR,QS_A,0,0,0,WS_A, ,NZ ,0x41 -- 41: EOR (dp,X)
|
| 351 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x42 -- 42: NOP
|
| 352 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x43 -- 43: NOP
|
| 353 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x44 -- 44: NOP
|
| 354 |
|
|
MEM 0,EOR,QS_A,0,0,0,WS_A, ,NZ ,0x45 -- 45: EOR dp
|
| 355 |
|
|
MEM 1,LSR,QS_M,0,0,0,WS_P, ,NZC ,0x46 -- 46: LSR dp
|
| 356 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,RMBx,0xEF -- 47: RMB4 dp
|
| 357 |
|
|
STK 0,XFR,QS_A,0,0,0, ,OS_A, ,0x48 -- 48: PHA
|
| 358 |
|
|
MEM 0,EOR,QS_A,0,0,0,WS_A, ,NZ ,0x49 -- 49: EOR #imm
|
| 359 |
|
|
INT 0,LSR,QS_A,0,0,0,WS_A, ,NZC ,0x4A -- 4A: LSR A
|
| 360 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x4B -- 4B: NOP
|
| 361 |
|
|
JMP 0,XFR,QS_A,0,0,0, , , ,0x4C -- 4C: JMP abs
|
| 362 |
|
|
MEM 0,EOR,QS_A,0,0,0,WS_A, ,NZ ,0x4D -- 4D: EOR abs
|
| 363 |
|
|
MEM 1,LSR,QS_M,0,0,0,WS_P, ,NZC ,0x4E -- 4E: LSR abs
|
| 364 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBRx,0x10 -- 4F: BBR4 dp,rel
|
| 365 |
|
|
|
| 366 |
|
|
--------------------------------------------------------------------------------
|
| 367 |
|
|
|
| 368 |
|
|
JMP 0,XFR,QS_A,0,0,0, , ,VC ,0x50 -- 50: BVC rel
|
| 369 |
|
|
MEM 0,EOR,QS_A,0,0,0,WS_A, ,NZ ,0x51 -- 51: EOR (dp),Y
|
| 370 |
|
|
MEM 0,EOR,QS_A,0,0,0,WS_A, ,NZ ,0x52 -- 52: EOR (dp)
|
| 371 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x53 -- 53: NOP
|
| 372 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x54 -- 54: NOP
|
| 373 |
|
|
MEM 0,EOR,QS_A,0,0,0,WS_A, ,NZ ,0x55 -- 55: EOR dp,X
|
| 374 |
|
|
MEM 1,LSR,QS_M,0,0,0,WS_P, ,NZC ,0x56 -- 56: LSR dp,X
|
| 375 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,RMBx,0xDF -- 57: RMB5 dp
|
| 376 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_P, ,CLI ,0x58 -- 58: CLI
|
| 377 |
|
|
MEM 0,EOR,QS_A,0,0,0,WS_A, ,NZ ,0x59 -- 59: EOR abs,Y
|
| 378 |
|
|
STK 0,XFR,QS_A,0,0,0, ,OS_Y, ,0x5A -- 5A: PHY
|
| 379 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x5B -- 5B: NOP
|
| 380 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x5C -- 5C: NOP
|
| 381 |
|
|
MEM 0,EOR,QS_A,0,0,0,WS_A, ,NZ ,0x5D -- 5D: EOR abs,X
|
| 382 |
|
|
MEM 1,LSR,QS_M,0,0,0,WS_P, ,NZC ,0x5E -- 5E: LSR abs,X
|
| 383 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBRx,0x20 -- 5F: BBR5 dp,rel
|
| 384 |
|
|
|
| 385 |
|
|
--------------------------------------------------------------------------------
|
| 386 |
|
|
|
| 387 |
|
|
JMP 0,XFR,QS_A,0,0,0, , , ,0x60 -- 60: RTS
|
| 388 |
|
|
MEM 0,ADC,QS_A,0,0,0,WS_A, ,NVZC,0x61 -- 61: ADC (dp,X)
|
| 389 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x62 -- 62: NOP
|
| 390 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x63 -- 63: NOP
|
| 391 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_Z, ,0x64 -- 64: STZ dp
|
| 392 |
|
|
MEM 0,ADC,QS_A,0,0,0,WS_A, ,NVZC,0x65 -- 65: ADC dp
|
| 393 |
|
|
MEM 1,ROR,QS_M,0,0,0,WS_P, ,NZC ,0x66 -- 66: ROR dp
|
| 394 |
|
|
INV 1,XFR,QS_M,0,0,0, , ,RMBx,0xBF -- 67: RMB6 dp
|
| 395 |
|
|
STK 0,XFR,QS_A,0,0,0,WS_A, ,NZ ,0x68 -- 68: PLA
|
| 396 |
|
|
MEM 0,ADC,QS_A,0,0,0,WS_A, ,NVZC,0x69 -- 69: ADC #imm
|
| 397 |
|
|
MEM 0,ROR,QS_A,0,0,0,WS_A, ,NZC ,0x6A -- 6A: ROR A
|
| 398 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x6B -- 6B: NOP
|
| 399 |
|
|
JMP 0,XFR,QS_A,0,0,0, , , ,0x6C -- 6C: JMP (abs)
|
| 400 |
|
|
MEM 0,ADC,QS_A,0,0,0,WS_A, ,NVZC,0x6D -- 6D: ADC abs
|
| 401 |
|
|
MEM 1,ROR,QS_M,0,0,0,WS_P, ,NZC ,0x6E -- 6E: ROR abs
|
| 402 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBRx,0x40 -- 6F: BBR6 dp,rel
|
| 403 |
|
|
|
| 404 |
|
|
--------------------------------------------------------------------------------
|
| 405 |
|
|
|
| 406 |
|
|
JMP 0,XFR,QS_A,0,0,0, , ,VS ,0x70 -- 70: BVS rel
|
| 407 |
|
|
MEM 0,ADC,QS_A,0,0,0,WS_A, ,NVZC,0x71 -- 71: ADC (dp),Y
|
| 408 |
|
|
MEM 0,ADC,QS_A,0,0,0,WS_A, ,NVZC,0x72 -- 72: ADC (dp)
|
| 409 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x73 -- 73: NOP
|
| 410 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_Z, ,0x74 -- 74: STZ dp,X
|
| 411 |
|
|
MEM 0,ADC,QS_A,0,0,0,WS_A, ,NVZC,0x75 -- 75: ADC dp,X
|
| 412 |
|
|
MEM 1,ROR,QS_M,0,0,0,WS_P, ,NZC ,0x76 -- 76: ROR dp,X
|
| 413 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,RMBx,0x7F -- 77: RMB7 dp
|
| 414 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_P, ,SEI ,0x78 -- 78: SEI
|
| 415 |
|
|
MEM 0,ADC,QS_A,0,0,0,WS_A, ,NVZC,0x79 -- 79: ADC abs,Y
|
| 416 |
|
|
STK 0,XFR,QS_M,0,0,0,WS_Y, ,NZ ,0x7A -- 7A: PLY
|
| 417 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x7B -- 7B: NOP
|
| 418 |
|
|
JMP 0,XFR,QS_A,0,0,0, , , ,0x7C -- 7C: JMP (abs,X)
|
| 419 |
|
|
MEM 0,ADC,QS_A,0,0,0,WS_A, ,NVZC,0x7D -- 7D: ADC abs,X
|
| 420 |
|
|
MEM 1,ROR,QS_M,0,0,0,WS_P, ,NZC ,0x7E -- 7E: ROR abs,X
|
| 421 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBRx,0x80 -- 7F: BBR7 dp,rel
|
| 422 |
|
|
|
| 423 |
|
|
--------------------------------------------------------------------------------
|
| 424 |
|
|
|
| 425 |
|
|
JMP 0,XFR,QS_A,0,0,0, , , ,0x80 -- 80: BRA rel
|
| 426 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_A, ,0x81 -- 81: STA (dp,X)
|
| 427 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x82 -- 82: NOP
|
| 428 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x83 -- 83: NOP
|
| 429 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_Y, ,0x84 -- 84: STY dp
|
| 430 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_A, ,0x85 -- 85: STA dp
|
| 431 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_X, ,0x86 -- 86: STX dp
|
| 432 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,SMBx,0x01 -- 87: SMB0 dp
|
| 433 |
|
|
INT 0,DEC,QS_Y,1,1,1,WS_Y,OS_Y,NZ ,0x88 -- 88: DEY
|
| 434 |
|
|
MEM 0,BIT,QS_A,0,0,0,WS_P, ,Z ,0x89 -- 89: BIT #imm
|
| 435 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_A,OS_X,NZ ,0x8A -- 8A: TXA
|
| 436 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x8B -- 8B: NOP
|
| 437 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_Y, ,0x8C -- 8C: STY abs
|
| 438 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_A, ,0x8D -- 8D: STA abs
|
| 439 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_X, ,0x8E -- 8E: STX abs
|
| 440 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBSx,0x01 -- 8F: BBS0 dp,rel
|
| 441 |
|
|
|
| 442 |
|
|
--------------------------------------------------------------------------------
|
| 443 |
|
|
|
| 444 |
|
|
JMP 0,XFR,QS_A,0,0,0, , ,CC ,0x90 -- 90: BCC rel
|
| 445 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_A, ,0x91 -- 91: STA (dp),Y
|
| 446 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_A, ,0x92 -- 92: STA (dp)
|
| 447 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x93 -- 93: NOP
|
| 448 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_Y, ,0x94 -- 94: STY dp,X
|
| 449 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_A, ,0x95 -- 95: STA dp,X
|
| 450 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_X, ,0x96 -- 96: STX dp,Y
|
| 451 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,SMBx,0x02 -- 97: SMB1 dp
|
| 452 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_A,OS_Y,NZ ,0x98 -- 98: TYA
|
| 453 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_A, ,0x99 -- 99: STA abs,Y
|
| 454 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_S,OS_X, ,0x9A -- 9A: TXS
|
| 455 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0x9B -- 9B: NOP
|
| 456 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_Z, ,0x9C -- 9C: STZ abs
|
| 457 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_A, ,0x9D -- 9D: STA abs,X
|
| 458 |
|
|
MEM 0,XFR,QS_A,0,0,0, ,OS_Z, ,0x9E -- 9E: STZ abs,X
|
| 459 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBSx,0x02 -- 9F: BBS1 dp,rel
|
| 460 |
|
|
|
| 461 |
|
|
--------------------------------------------------------------------------------
|
| 462 |
|
|
|
| 463 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_Y, ,NZ ,0xA0 -- A0: LDY #imm
|
| 464 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_A, ,NZ ,0xA1 -- A1: LDA (dp,X)
|
| 465 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_X, ,NZ ,0xA2 -- A2: LDX #imm
|
| 466 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xA3 -- A3: NOP
|
| 467 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_Y, ,NZ ,0xA4 -- A4: LDY dp
|
| 468 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_A, ,NZ ,0xA5 -- A5: LDA dp
|
| 469 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_X, ,NZ ,0xA6 -- A6: LDX dp
|
| 470 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,SMBx,0x04 -- A7: SMB2 dp
|
| 471 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_Y,OS_A,NZ ,0xA8 -- A8: TAY
|
| 472 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_A, ,NZ ,0xA9 -- A9: LDA #imm
|
| 473 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_X,OS_A,NZ ,0xAA -- AA: TAX
|
| 474 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xAB -- AB: NOP
|
| 475 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_Y, ,NZ ,0xAC -- AC: LDY abs
|
| 476 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_A, ,NZ ,0xAD -- AD: LDA abs
|
| 477 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_X, ,NZ ,0xAE -- AE: LDX abs
|
| 478 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBSx,0x04 -- AF: BBS2 dp,rel
|
| 479 |
|
|
|
| 480 |
|
|
--------------------------------------------------------------------------------
|
| 481 |
|
|
|
| 482 |
|
|
JMP 0,XFR,QS_A,0,0,0, , ,CS ,0xB0 -- B0: BCS rel
|
| 483 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_A, ,NZ ,0xB1 -- B1: LDA (dp),Y
|
| 484 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_A, ,NZ ,0xB2 -- B2: LDA (dp)
|
| 485 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xB3 -- B3: NOP
|
| 486 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_Y, ,NZ ,0xB4 -- B4: LDY dp,X
|
| 487 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_A, ,NZ ,0xB5 -- B5: LDA dp,X
|
| 488 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_X, ,NZ ,0xB6 -- B6: LDX dp,Y
|
| 489 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,SMBx,0x08 -- B7: SMB3 dp
|
| 490 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_P, ,CLV ,0xB8 -- B8: CLV
|
| 491 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_A, ,NZ ,0xB9 -- B9: LDA abs,Y
|
| 492 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_X,OS_S,NZ ,0xBA -- BA: TSX
|
| 493 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xBB -- BB: NOP
|
| 494 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_Y, ,NZ ,0xBC -- BC: LDY abs,X
|
| 495 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_A, ,NZ ,0xBD -- BD: LDA abs,X
|
| 496 |
|
|
MEM 0,XFR,QS_A,0,0,0,WS_X, ,NZ ,0xBE -- BE: LDX abs,Y
|
| 497 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBSx,0x08 -- BF: BBS3 dp,rel
|
| 498 |
|
|
|
| 499 |
|
|
--------------------------------------------------------------------------------
|
| 500 |
|
|
|
| 501 |
|
|
MEM 0,CMP,QS_Y,0,1,1,WS_P, ,NZC ,0xC0 -- C0: CPY #imm
|
| 502 |
|
|
MEM 0,CMP,QS_A,0,1,1,WS_P, ,NZC ,0xC1 -- C1: CMP (dp,X)
|
| 503 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xC2 -- C2: NOP
|
| 504 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xC3 -- C3: NOP
|
| 505 |
|
|
MEM 0,CMP,QS_Y,0,1,1,WS_P, ,NZC ,0xC4 -- C4: CPY dp
|
| 506 |
|
|
MEM 0,CMP,QS_A,0,1,1,WS_P, ,NZC ,0xC5 -- C5: CMP dp
|
| 507 |
|
|
MEM 1,DEC,QS_M,1,1,1,WS_P, ,NZ ,0xC6 -- C6: DEC dp
|
| 508 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,SMBx,0x10 -- C7: SMB4 dp
|
| 509 |
|
|
INT 0,INC,QS_Y,1,0,1,WS_Y, ,NZ ,0xC8 -- C8: INY
|
| 510 |
|
|
MEM 0,CMP,QS_A,0,1,1,WS_P, ,NZC ,0xC9 -- C9: CMP #imm
|
| 511 |
|
|
INT 0,DEC,QS_X,1,1,1,WS_X, ,NZ ,0xCA -- CA: DEX
|
| 512 |
|
|
WAI 0,XFR,QS_A,0,0,0, , , ,0xCB -- CB: WAI
|
| 513 |
|
|
MEM 0,CMP,QS_Y,0,1,1,WS_P, ,NZC ,0xCC -- CC: CPY abs
|
| 514 |
|
|
MEM 0,CMP,QS_A,0,1,1,WS_P, ,NZC ,0xCD -- CD: CMP abs
|
| 515 |
|
|
MEM 1,DEC,QS_M,1,1,1,WS_P, ,NZ ,0xCE -- CE: DEC abs
|
| 516 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBSx,0x10 -- CF: BBS4 dp,rel
|
| 517 |
|
|
|
| 518 |
|
|
--------------------------------------------------------------------------------
|
| 519 |
|
|
|
| 520 |
|
|
JMP 0,XFR,QS_A,0,0,0, , ,NE ,0xD0 -- D0: BNE rel
|
| 521 |
|
|
MEM 0,CMP,QS_A,0,1,1,WS_P, ,NZC ,0xD1 -- D1: CMP (dp),Y
|
| 522 |
|
|
MEM 0,CMP,QS_A,0,1,1,WS_P, ,NZC ,0xD2 -- D2: CMP (dp)
|
| 523 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xD3 -- D3: NOP
|
| 524 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xD4 -- D4: NOP
|
| 525 |
|
|
MEM 0,CMP,QS_A,0,1,1,WS_P, ,NZC ,0xD5 -- D5: CMP dp,X
|
| 526 |
|
|
MEM 1,DEC,QS_M,1,1,1,WS_P, ,NZ ,0xD6 -- D6: DEC dp,X
|
| 527 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,SMBx,0x20 -- D7: SMB5 dp
|
| 528 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_P, ,CLD ,0xD8 -- D8: CLD
|
| 529 |
|
|
MEM 0,CMP,QS_A,0,1,1,WS_P, ,NZC ,0xD9 -- D9: CMP abs,Y
|
| 530 |
|
|
STK 0,XFR,QS_A,0,0,0, ,OS_X, ,0xDA -- DA: PHX
|
| 531 |
|
|
STP 0,XFR,QS_A,0,0,0, , , ,0xDB -- DB: STP
|
| 532 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xDC -- DC: NOP
|
| 533 |
|
|
MEM 0,CMP,QS_A,0,1,1,WS_P, ,NZC ,0xDD -- DD: CMP abs,X
|
| 534 |
|
|
MEM 1,DEC,QS_M,1,1,1,WS_P, ,NZ ,0xDE -- DE: DEC abs,X
|
| 535 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBSx,0x20 -- DF: BBS5 dp,rel
|
| 536 |
|
|
|
| 537 |
|
|
--------------------------------------------------------------------------------
|
| 538 |
|
|
|
| 539 |
|
|
MEM 0,CMP,QS_X,0,1,1,WS_P, ,NZC ,0xE0 -- E0: CPX #imm
|
| 540 |
|
|
MEM 0,SBC,QS_A,0,1,0,WS_A, ,NVZC,0xE1 -- E1: SBC (dp,X)
|
| 541 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xE2 -- E2: NOP
|
| 542 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xE3 -- E3: NOP
|
| 543 |
|
|
MEM 0,CMP,QS_X,0,1,1,WS_P, ,NZC ,0xE4 -- E4: CPX dp
|
| 544 |
|
|
MEM 0,SBC,QS_A,0,1,0,WS_A, ,NVZC,0xE5 -- E5: SBC dp
|
| 545 |
|
|
MEM 1,INC,QS_M,1,0,1,WS_P, ,NZ ,0xE6 -- E6: INC dp
|
| 546 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,SMBx,0x40 -- E7: SMB6 dp
|
| 547 |
|
|
INT 0,INC,QS_X,1,0,1,WS_X, ,NZ ,0xE8 -- E8: INX
|
| 548 |
|
|
MEM 0,SBC,QS_A,0,1,0,WS_A, ,NVZC,0xE9 -- E9: SBC #imm
|
| 549 |
|
|
INT 0,XFR,QS_A,0,0,0, , , ,0xEA -- EA: NOP
|
| 550 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xEB -- EB: NOP
|
| 551 |
|
|
MEM 0,CMP,QS_X,0,1,1,WS_P, ,NZC ,0xEC -- EC: CPX abs
|
| 552 |
|
|
MEM 0,SBC,QS_A,0,1,0,WS_A, ,NVZC,0xED -- ED: SBC abs
|
| 553 |
|
|
MEM 1,INC,QS_M,1,0,1,WS_P, ,NZ ,0xEE -- EE: INC abs
|
| 554 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBSx,0x40 -- EF: BBS6 dp,rel
|
| 555 |
|
|
|
| 556 |
|
|
--------------------------------------------------------------------------------
|
| 557 |
|
|
|
| 558 |
|
|
JMP 0,XFR,QS_A,0,0,0, , ,EQ ,0xF0 -- F0: BEQ rel
|
| 559 |
|
|
MEM 0,SBC,QS_A,0,1,0,WS_A, ,NVZC,0xF1 -- F1: SBC (dp),Y
|
| 560 |
|
|
MEM 0,SBC,QS_A,0,1,0,WS_A, ,NVZC,0xF2 -- F2: SBC (dp)
|
| 561 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xF3 -- F3: NOP
|
| 562 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xF4 -- F4: NOP
|
| 563 |
|
|
MEM 0,SBC,QS_A,0,1,0,WS_A, ,NVZC,0xF5 -- F5: SBC dp,X
|
| 564 |
|
|
MEM 1,INC,QS_M,1,0,1,WS_P, ,NZ ,0xF6 -- F6: INC dp,X
|
| 565 |
|
|
MEM 1,XFR,QS_M,0,0,0, , ,SMBx,0x80 -- F7: SMB7 dp
|
| 566 |
|
|
INT 0,XFR,QS_A,0,0,0,WS_P, ,SED ,0xF8 -- F8: SED
|
| 567 |
|
|
MEM 0,SBC,QS_A,0,1,0,WS_A, ,NVZC,0xF9 -- F9: SBC abs,Y
|
| 568 |
|
|
STK 0,XFR,QS_M,0,0,0,WS_X, ,NZ ,0xFA -- FA: PLX
|
| 569 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xFB -- FB: NOP
|
| 570 |
|
|
INV 0,XFR,QS_A,0,0,0, , , ,0xFC -- FC: NOP
|
| 571 |
|
|
MEM 0,SBC,QS_A,0,1,0,WS_A, ,NVZC,0xFD -- FD: SBC abs,X
|
| 572 |
|
|
MEM 1,INC,QS_M,1,0,1,WS_P, ,NZ ,0xFE -- FE: INC abs,X
|
| 573 |
|
|
JMP 0,XFR,QS_M,0,0,0, , ,BBSx,0x80 -- FF: BBS7 dp,rel
|
| 574 |
|
|
|
| 575 |
|
|
--------------------------------------------------------------------------------
|
| 576 |
|
|
|
| 577 |
|
|
_end:
|
