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[/] [m65c02/] [trunk/] [Src/] [RTL/] [M65C02_ClkGen.v] - Blame information for rev 2

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1 2 MichaelA
////////////////////////////////////////////////////////////////////////////////
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//
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//  Copyright 2013 by Michael A. Morris, dba M. A. Morris & Associates
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//
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//  All rights reserved. The source code contained herein is publicly released
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//  under the terms and conditions of the GNU Lesser Public License. No part of
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//  this source code may be reproduced or transmitted in any form or by any
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//  means, electronic or mechanical, including photocopying, recording, or any
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//  information storage and retrieval system in violation of the license under
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//  which the source code is released.
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//
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//  The source code contained herein is free; it may be redistributed and/or
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//  modified in accordance with the terms of the GNU Lesser General Public
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//  License as published by the Free Software Foundation; either version 2.1 of
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//  the GNU Lesser General Public License, or any later version.
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//
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//  The source code contained herein is freely released WITHOUT ANY WARRANTY;
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//  without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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//  PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
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//  more details.)
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//
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//  A copy of the GNU Lesser General Public License should have been received
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//  along with the source code contained herein; if not, a copy can be obtained
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//  by writing to:
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//
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//  Free Software Foundation, Inc.
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//  51 Franklin Street, Fifth Floor
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//  Boston, MA  02110-1301 USA
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//
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//  Further, no use of this source code is permitted in any form or means
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//  without inclusion of this banner prominently in any derived works.
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//
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//  Michael A. Morris
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//  Huntsville, AL
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//
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:         M. A. Morris & Associates 
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// Engineer:        Michael A. Morris 
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// 
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// Create Date:     20:32:33 06/15/2013 
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// Design Name:     M65C02 - WDC W65C02 Microprocessor Re-Implementation 
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// Module Name:     M65C02_ClkGen 
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// Project Name:    C:\XProjects\ISE10.1i\M65C02
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// Target Devices:  RAM-based FPGAs: XC3S50A-xVQ100; XC3S200A-xVQ100
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// Tool versions:   Xilinx ISE 10.1i SP3
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// 
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// Description: 
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//
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//  This module combines an Architecture Wizard IP instatiation of a DCM_SP to 
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//  generate a 4x clock from an external crystal oscillator. It also generates
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//  a reset signal to external logic, and a reset signal for internal logic and
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//  the DCM. An external reset input is accepted, but buffered using a synchro-
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//  nizer.
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//  
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// Dependencies: ClkGen.xaw
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//
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// Revision:
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//
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//  0.01    13F15   MAM     Creation Date
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//
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//  1.00    13F21   MAM     Corrected error in the reset generation logic. An
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//                          AND reduction operator was applied to external reset
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//                          shift register. An OR reduction is necessary, and
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//                          is not applied. Asserting the external reset now
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//                          generates a reset pulse several clock cycles in
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//                          width to the internal logic. Added Clk_UART as an
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//                          output taken from the Clk2X output of DCM. Clk_UART
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//                          can noew be fixed at 2x ClkIn.
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//
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//  1.01    13H17   MAM     Adapted for use with the M65C02
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//
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// Additional Comments: 
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//
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////////////////////////////////////////////////////////////////////////////////
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module M65C02_ClkGen(
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    input   nRst,                       // External Reset Input (active low)
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    input   ClkIn,                      // Reference Input Clk
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    output  Clk,                        // Internal Clk - (M/D) x ClkIn
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    output  Clk_UART,                   // 2x ClkIn
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    output  Buf_ClkIn,                  // Buffered ClkIn
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    output  reg Rst                     // Internal Reset
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);
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////////////////////////////////////////////////////////////////////////////////
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//
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//  Declarations
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//
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wire    DCM_Locked;             // DCM Locked Status Signal
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reg     [3:0] DCM_Rst;          // Stretched DCM Reset (see Table 3-6 UG331)
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reg     nRst_IFD;               // Input FF for external Reset signal
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reg     [3:0] xRst;             // Stretched external reset (BufClkIn)
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wire    Rst_M65C02;             // Combination of DCM_Rst and xRst
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reg     [3:0] Rst_Dly;          // Stretched internal reset (BufClkIn)
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wire    FE_Rst_Dly;             // Falling edge of Rst_Dly (Clk)
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////////////////////////////////////////////////////////////////////////////////
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//
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//  Implementation
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//
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//  Implement internal clock generator using DCM and DFS. DCM/DFS multiplies
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//  external clock reference by 4.
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ClkGen  ClkGen (
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            .USER_RST_IN(DCM_Rst[0]),           // DCM Rst generated on FE Lock 
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            .CLKIN_IN(ClkIn),                   // ClkIn          = 14.7456 MHz
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            .CLKIN_IBUFG_OUT(Buf_ClkIn),        // Buffered ClkIn = 14.7456 MHz
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            .CLKFX_OUT(Clk),                    // DCM ClkFX_Out  = 58.9824 MHz 
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            .CLK0_OUT(),                        // Clk0_Out unused 
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            .CLK2X_OUT(Clk_UART),               // Clk2x_Out (FB) = 29.4912 MHz 
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            .LOCKED_OUT(DCM_Locked)             // When 1, DCM Locked 
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        );
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//  Detect falling edge of DCM_Locked, and generate DCM reset pulse at least 4
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//  ClkIn periods wide if a falling edge is detected. (see Table 3-6 UG331)
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fedet   FE1 (
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            .rst(1'b0),             // No reset required for this circuit 
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            .clk(Buf_ClkIn),        // Buffered DCM input Clock
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            .din(DCM_Locked),       // DCM Locked signal
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            .pls(FE_DCM_Locked)     // Falling Edge of DCM_Locked signal
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        );
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always @(posedge Buf_ClkIn or posedge FE_DCM_Locked)
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begin
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    if(FE_DCM_Locked)
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        DCM_Rst <= #1 4'b1111;
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    else
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        DCM_Rst <= #1 {1'b0, DCM_Rst[3:1]};
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end
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//  Synchronize asynchronous external reset, nRst, to internal clock and
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//      stretch (extend) by 16 clock cycles after external reset deasserted
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//
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//  With Spartan 3A(N) FPGA family use synchronous reset for reset operations
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//  per synthesis recommendations. so only these FFs will use asynchronous
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//  reset, and the remainder of the design will use synchronous reset.
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always @(posedge Buf_ClkIn or negedge DCM_Locked)
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begin
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    if(~DCM_Locked)
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        nRst_IFD <= #1 0;
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    else
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        nRst_IFD <= #1 nRst;
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end
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always @(posedge Buf_ClkIn or negedge DCM_Locked)
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begin
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    if(~DCM_Locked)
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        xRst <= #1 ~0;
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    else
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        xRst <= #1 {~nRst_IFD, xRst[2:1]};
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end
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assign Rst_M65C02 = ((|{~nRst_IFD, xRst}) | ~DCM_Locked);
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always @(posedge Buf_ClkIn or posedge Rst_M65C02)
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begin
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    if (Rst_M65C02)
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        Rst_Dly <= #1 ~0;
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    else
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        Rst_Dly <= #1 {1'b0, Rst_Dly[3:1]};
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end
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//  synchronize Rst to DCM/DFS output clock (if DCM Locked)
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fedet   FE2 (
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            .rst(Rst_M65C02),
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            .clk(Clk),              // System Clock
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            .din(|Rst_Dly),         // System Reset Delay
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            .pls(FE_Rst_Dly)        // Falling Edge of Rst_Dly
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        );
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always @(posedge Clk or posedge Rst_M65C02)
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begin
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    if(Rst_M65C02)
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        Rst <= #1 1;
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    else if(FE_Rst_Dly)
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        Rst <= #1 0;
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end
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endmodule

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