URL https://opencores.org/ocsvn/m65c02/m65c02/trunk

Subversion Repositories m65c02

[/] [m65c02/] [trunk/] [Src/] [RTL/] [fedet.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	MichaelA	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company: Alpha Beta Technologies, Inc.`
4			`// Engineer: Michael A. Morris`
5			`//`
6			`// Create Date: 03/01/2008`
7			`// Design Name: USB MBP HDL`
8			`// Module Name: fedet.v`
9			`// Project Name: 4020 HAWK ZAOM Upgrade`
10			`// Target Devices: XC2S150-5PQ208I`
11			`// Tool versions: ISE 8.2i`
12			`//`
13			`// Description: Multi-stage synchronizer with falling edge detection`
14			`//`
15			`// Dependencies: None`
16			`//`
17			`// Revision History:`
18			`//`
19			`// 0.01 08C01 MAM File Created`
20			`//`
21			`// Additional Comments:`
22			`//`
23			`///////////////////////////////////////////////////////////////////////////////`
24
25			`module fedet(rst, clk, din, pls);`
26
27			`///////////////////////////////////////////////////////////////////////////////`
28			`//`
29			`// Module Port Declarations`
30			`//`
31
32			`input rst;`
33			`input clk;`
34			`input din;`
35			`output pls;`
36
37			`///////////////////////////////////////////////////////////////////////////////`
38			`//`
39			`// Module Level Declarations`
40			`//`
41
42			`reg [2:0] QSync;`
43
44			`///////////////////////////////////////////////////////////////////////////////`
45			`//`
46			`// Implementation`
47			`//`
48
49			`always @(posedge clk or posedge rst) begin`
50			`if(rst)`
51			`#1 QSync <= 3'b011;`
52			`else`
53			`#1 QSync <= {~QSync[0] & QSync[1], QSync[0], din};`
54			`end`
55
56			`assign pls = QSync[2];`
57
58			`endmodule`