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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [dpq_modules.v] - Blame information for rev 2

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/*****************************************************************************/
// Id ..........dpq_modules.v                                                 //
// Author.......Ran Minerbi                                                   //
//                                                                            //
//   Unit Description   :                                                     //
//     dpq module make sure that any frame reside                             //
//  in the iba will be sent to Xbar as soon as                                //
//  it is ready to be sent.                                                   //
//  Iba notify dpq when frame transmission is done.                           //
//                                                                            //
/*****************************************************************************/
module Qp(reset,clk,transmit_done , Din,start_adr,T_q,adr_valid);
 
   input  reset,clk,transmit_done;
   input  [31:0] Din;
   output [15:0] start_adr;
   output [7:0]  T_q;
   output adr_valid;
 
   reg adr_valid ;
   reg [31:0] prev_input;
   reg div_2_clk, div_4_clk;
   reg write_fifo , read_fifo , TxFifoClear ;
   reg  update_prev_input;
   reg [1:0] state;
   wire            TxBufferFull;
   wire            TxBufferAlmostFull;
   wire            TxBufferAlmostEmpty;
   wire            TxBufferEmpty;
   wire [31:0] queue_out;
   wire [4:0] txfifo_cnt;
 
   assign start_adr = queue_out[23:8];
   assign T_q = queue_out[7:0];
 
       eth_fifo #(
           .DATA_WIDTH(32),
           .DEPTH(32),
           .CNT_WIDTH(5))
 qp_fifo (
         .clk            (clk),
         .reset          (reset),
         // Inputs
         .data_in        (Din),
         .write          (write_fifo),
         .read           (read_fifo),
         .clear          (TxFifoClear),
         // Outputs
         .data_out       (queue_out),
         .full           (TxBufferFull),
         .almost_full    (TxBufferAlmostFull),
         .almost_empty   (TxBufferAlmostEmpty),
         .empty          (TxBufferEmpty),
         .cnt            (txfifo_cnt)
        );
 
    initial begin
       div_2_clk=0;
       div_4_clk=0;
       read_fifo =0;
       adr_valid=0;
       prev_input =0;
        write_fifo=0;
        update_prev_input = 0;
        state = 0;
    end
 
 always @ (posedge clk or posedge reset )
   begin
       if (reset)
           begin
         //    Dout <= 0;
            end
           else
            begin
               div_2_clk  <= div_2_clk^clk;
 
               if (|(Din & 32'h0000000f))       // T_Q defined in FDB
               begin
                  prev_input <= Din;
                  update_prev_input =1;
                  write_fifo <= |(prev_input^Din);
               end
 
                 /*   if (read_fifo==1)
                   begin
                     read_fifo=0;
                     adr_valid=1;
                    end     */
            end
   end
 
   always @ (posedge div_2_clk or posedge reset )
   begin
       if (reset)
           begin
          //   Dout <= 0;
            end
           else
            begin
               div_4_clk <= div_4_clk^div_2_clk;
 
            end
   end
 
 /*   always @ (posedge clk)
    begin
       if (read_fifo==1)
           begin
            read_fifo=0;
           end
     else  if (txfifo_cnt > 1 && transmit_done==1)   //  txfifo_cnt > 1 cause when read from queue its size is at least 1
           begin
               read_fifo=1;      // only for single cycle need - set back to 0 in line ...never - bug
               adr_valid=0;
           end
           else  if (txfifo_cnt > 0)
                   begin
                     adr_valid=1;
                     //read_fifo=0;
 
                    end
 
      end
     always @ (negedge transmit_done)
      begin
         read_fifo=0;
        // adr_valid=0;   //this what shitting
      end   */
 
   /*
     state :
     0: Empty
     1: Valid
     2: Invalid_Queue_not_Empty
     3:Invalid_queue_empty
 
   */
 
    always @(posedge clk)
     begin
 
       case (state)   // state [2]
 
        2'h0 :            //Empty
            begin
              adr_valid=0;
              TxFifoClear = 0;
              if (txfifo_cnt > 0)
                  begin
                    state = 1;
                  end
            end
       2'h1:              //Valid
            begin
             adr_valid=1;
             read_fifo = 0;
             if (transmit_done == 1 && txfifo_cnt > 1)
               begin
                   state = 2;
               end
              if (transmit_done == 1 && txfifo_cnt == 1)
               begin
                 state = 3;
               end
            end
 
        2'h2:
            begin
              adr_valid = 0;
              read_fifo = 1;
              if (transmit_done == 0)
                  begin
                   state = 1;
                   end
            end
        2'h3:
            begin
              TxFifoClear = 1;
              adr_valid = 0;
              if (txfifo_cnt == 0)
                  begin
                    state = 0;
                   end
 
            end
 
       endcase
 
     end   //always
 
endmodule
 
 
 
/*
 
   transmit_done+ txfifo_cnt > 1
                 ||
                \/
              read_fifo  (one_cycle)
                 ||
                \/
               addr_valid
*/

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Subversion Repositories mac_layer_switch

[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [dpq_modules.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ranm11
2			`/*****************************************************************************/`
3			`// Id ..........dpq_modules.v //`
4			`// Author.......Ran Minerbi //`
5			`// //`
6			`// Unit Description : //`
7			`// dpq module make sure that any frame reside //`
8			`// in the iba will be sent to Xbar as soon as //`
9			`// it is ready to be sent. //`
10			`// Iba notify dpq when frame transmission is done. //`
11			`// //`
12			`/*****************************************************************************/`
13			`module Qp(reset,clk,transmit_done , Din,start_adr,T_q,adr_valid);`
14
15			`input reset,clk,transmit_done;`
16			`input [31:0] Din;`
17			`output [15:0] start_adr;`
18			`output [7:0] T_q;`
19			`output adr_valid;`
20
21			`reg adr_valid ;`
22			`reg [31:0] prev_input;`
23			`reg div_2_clk, div_4_clk;`
24			`reg write_fifo , read_fifo , TxFifoClear ;`
25			`reg update_prev_input;`
26			`reg [1:0] state;`
27			`wire TxBufferFull;`
28			`wire TxBufferAlmostFull;`
29			`wire TxBufferAlmostEmpty;`
30			`wire TxBufferEmpty;`
31			`wire [31:0] queue_out;`
32			`wire [4:0] txfifo_cnt;`
33
34			`assign start_adr = queue_out[23:8];`
35			`assign T_q = queue_out[7:0];`
36
37			`eth_fifo #(`
38			`.DATA_WIDTH(32),`
39			`.DEPTH(32),`
40			`.CNT_WIDTH(5))`
41			`qp_fifo (`
42			`.clk (clk),`
43			`.reset (reset),`
44			`// Inputs`
45			`.data_in (Din),`
46			`.write (write_fifo),`
47			`.read (read_fifo),`
48			`.clear (TxFifoClear),`
49			`// Outputs`
50			`.data_out (queue_out),`
51			`.full (TxBufferFull),`
52			`.almost_full (TxBufferAlmostFull),`
53			`.almost_empty (TxBufferAlmostEmpty),`
54			`.empty (TxBufferEmpty),`
55			`.cnt (txfifo_cnt)`
56			`);`
57
58			`initial begin`
59			`div_2_clk=0;`
60			`div_4_clk=0;`
61			`read_fifo =0;`
62			`adr_valid=0;`
63			`prev_input =0;`
64			`write_fifo=0;`
65			`update_prev_input = 0;`
66			`state = 0;`
67			`end`
68
69			`always @ (posedge clk or posedge reset )`
70			`begin`
71			`if (reset)`
72			`begin`
73			`// Dout <= 0;`
74			`end`
75			`else`
76			`begin`
77			`div_2_clk <= div_2_clk^clk;`
78
79			`if (\|(Din & 32'h0000000f)) // T_Q defined in FDB`
80			`begin`
81			`prev_input <= Din;`
82			`update_prev_input =1;`
83			`write_fifo <= \|(prev_input^Din);`
84			`end`
85
86			`/* if (read_fifo==1)`
87			`begin`
88			`read_fifo=0;`
89			`adr_valid=1;`
90			`end */`
91			`end`
92			`end`
93
94			`always @ (posedge div_2_clk or posedge reset )`
95			`begin`
96			`if (reset)`
97			`begin`
98			`// Dout <= 0;`
99			`end`
100			`else`
101			`begin`
102			`div_4_clk <= div_4_clk^div_2_clk;`
103
104			`end`
105			`end`
106
107			`/* always @ (posedge clk)`
108			`begin`
109			`if (read_fifo==1)`
110			`begin`
111			`read_fifo=0;`
112			`end`
113			`else if (txfifo_cnt > 1 && transmit_done==1) // txfifo_cnt > 1 cause when read from queue its size is at least 1`
114			`begin`
115			`read_fifo=1; // only for single cycle need - set back to 0 in line ...never - bug`
116			`adr_valid=0;`
117			`end`
118			`else if (txfifo_cnt > 0)`
119			`begin`
120			`adr_valid=1;`
121			`//read_fifo=0;`
122
123			`end`
124
125			`end`
126			`always @ (negedge transmit_done)`
127			`begin`
128			`read_fifo=0;`
129			`// adr_valid=0; //this what shitting`
130			`end */`
131
132			`/*`
133			`state :`
134			`0: Empty`
135			`1: Valid`
136			`2: Invalid_Queue_not_Empty`
137			`3:Invalid_queue_empty`
138
139			`*/`
140
141			`always @(posedge clk)`
142			`begin`
143
144			`case (state) // state [2]`
145
146			`2'h0 : //Empty`
147			`begin`
148			`adr_valid=0;`
149			`TxFifoClear = 0;`
150			`if (txfifo_cnt > 0)`
151			`begin`
152			`state = 1;`
153			`end`
154			`end`
155			`2'h1: //Valid`
156			`begin`
157			`adr_valid=1;`
158			`read_fifo = 0;`
159			`if (transmit_done == 1 && txfifo_cnt > 1)`
160			`begin`
161			`state = 2;`
162			`end`
163			`if (transmit_done == 1 && txfifo_cnt == 1)`
164			`begin`
165			`state = 3;`
166			`end`
167			`end`
168
169			`2'h2:`
170			`begin`
171			`adr_valid = 0;`
172			`read_fifo = 1;`
173			`if (transmit_done == 0)`
174			`begin`
175			`state = 1;`
176			`end`
177			`end`
178			`2'h3:`
179			`begin`
180			`TxFifoClear = 1;`
181			`adr_valid = 0;`
182			`if (txfifo_cnt == 0)`
183			`begin`
184			`state = 0;`
185			`end`
186
187			`end`
188
189			`endcase`
190
191			`end //always`
192
193			`endmodule`
194
195
196
197			`/*`
198
199			`transmit_done+ txfifo_cnt > 1`
200			`\|\|`
201			`\/`
202			`read_fifo (one_cycle)`
203			`\|\|`
204			`\/`
205			`addr_valid`
206			`*/`