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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_cop.v                                                   ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/project,ethmac                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/10/10 16:43:59  mohor
// Minor $display change.
//
// Revision 1.2  2002/09/09 12:54:13  mohor
// error acknowledge cycle termination added to display.
//
// Revision 1.1  2002/08/14 17:16:07  mohor
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
// interfaces:
// - Host connects to the master interface
// - Ethernet master (DMA) connects to the second master interface
// - Memory interface connects to the slave interface
// - Ethernet slave interface (access to registers and BDs) connects to second
//   slave interface
//
//
//
//
//
//   Created by Igor Mohor 
//   Changed by Ran Minerbi
 
`include "timescale.v"
 
module eth_cop
(
  // WISHBONE common
  wb_clk_i, wb_rst_i,
 
  // WISHBONE MASTER 1
  m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i,  m1_wb_dat_o,
  m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
  m1_wb_err_o,
 
  // WISHBONE MASTER 2
  m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i,  m2_wb_dat_o,
  m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
  m2_wb_err_o,
 
  // WISHBONE slave 1
        s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o,  s1_wb_cyc_o,
        s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
        s1_wb_dat_o,
 
  // WISHBONE slave 2
        s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o,  s2_wb_cyc_o,
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
        s2_wb_dat_o
);
 
parameter ETH_BASE     = 32'hd0000000;
parameter ETH_WIDTH    = 32'h800;
parameter MEMORY_BASE  = 32'h2000;
parameter MEMORY_WIDTH = 32'h10000;
 
// WISHBONE common
input wb_clk_i, wb_rst_i;
 
// WISHBONE MASTER 1
input  [31:0] m1_wb_adr_i, m1_wb_dat_i;
input   [3:0] m1_wb_sel_i;
input         m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
output [31:0] m1_wb_dat_o;
output        m1_wb_ack_o, m1_wb_err_o;
 
// WISHBONE MASTER 2
input  [31:0] m2_wb_adr_i, m2_wb_dat_i;
input   [3:0] m2_wb_sel_i;
input         m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
output [31:0] m2_wb_dat_o;
output        m2_wb_ack_o, m2_wb_err_o;
 
// WISHBONE slave 1
input  [31:0] s1_wb_dat_i;
input         s1_wb_ack_i, s1_wb_err_i;
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
output  [3:0] s1_wb_sel_o;
output        s1_wb_we_o,  s1_wb_cyc_o, s1_wb_stb_o;
 
// WISHBONE slave 2
input  [31:0] s2_wb_dat_i;
input         s2_wb_ack_i, s2_wb_err_i;
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
output  [3:0] s2_wb_sel_o;
output        s2_wb_we_o,  s2_wb_cyc_o, s2_wb_stb_o;
 
reg           m1_in_progress;
reg           m2_in_progress;
reg    [31:0] s1_wb_adr_o;
reg     [3:0] s1_wb_sel_o;
reg           s1_wb_we_o;
reg    [31:0] s1_wb_dat_o;
reg           s1_wb_cyc_o;
reg           s1_wb_stb_o;
reg    [31:0] s2_wb_adr_o;
reg     [3:0] s2_wb_sel_o;
reg           s2_wb_we_o;
reg    [31:0] s2_wb_dat_o;
reg           s2_wb_cyc_o;
reg           s2_wb_stb_o;
 
reg           m1_wb_ack_o;
reg    [31:0] m1_wb_dat_o;
reg           m2_wb_ack_o;
reg    [31:0] m2_wb_dat_o;
 
reg           m1_wb_err_o;
reg           m2_wb_err_o;
 
wire m_wb_access_finished;
wire m1_addressed_s1 = (m1_wb_adr_i >= ETH_BASE) &
                       (m1_wb_adr_i < (ETH_BASE + ETH_WIDTH));
wire m1_addressed_s2 = (m1_wb_adr_i >= MEMORY_BASE) &
                       (m1_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));
wire m2_addressed_s1 = (m2_wb_adr_i >= ETH_BASE) &
                       (m2_wb_adr_i < (ETH_BASE + ETH_WIDTH));
wire m2_addressed_s2 = (m2_wb_adr_i >= MEMORY_BASE) &
                       (m2_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));
 
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (m1_addressed_s1 | m1_addressed_s2);
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (m2_addressed_s1 | m2_addressed_s2);
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    begin
      m1_in_progress <= 0;
      m2_in_progress <= 0;
      s1_wb_adr_o    <= 0;
      s1_wb_sel_o    <= 0;
      s1_wb_we_o     <= 0;
      s1_wb_dat_o    <= 0;
      s1_wb_cyc_o    <= 0;
      s1_wb_stb_o    <= 0;
      s2_wb_adr_o    <= 0;
      s2_wb_sel_o    <= 0;
      s2_wb_we_o     <= 0;
      s2_wb_dat_o    <= 0;
      s2_wb_cyc_o    <= 0;
      s2_wb_stb_o    <= 0;
    end
  else
    begin
      case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished})  // synopsys_full_case synopsys_paralel_case
        5'b00_10_0, 5'b00_11_0 :
          begin
            m1_in_progress <= 1'b1;  // idle: m1 or (m1 & m2) want access: m1 -> m
            if(m1_addressed_s1)
              begin
                s1_wb_adr_o <= m1_wb_adr_i;
                s1_wb_sel_o <= m1_wb_sel_i;
                s1_wb_we_o  <= m1_wb_we_i;
                s1_wb_dat_o <= m1_wb_dat_i;
                s1_wb_cyc_o <= 1'b1;
                s1_wb_stb_o <= 1'b1;
              end
            else if(m1_addressed_s2)
              begin
                s2_wb_adr_o <= m1_wb_adr_i;
                s2_wb_sel_o <= m1_wb_sel_i;
                s2_wb_we_o  <= m1_wb_we_i;
                s2_wb_dat_o <= m1_wb_dat_i;
                s2_wb_cyc_o <= 1'b1;
                s2_wb_stb_o <= 1'b1;
              end
            else
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
          end
        5'b00_01_0 :
          begin
            m2_in_progress <= 1'b1;  // idle: m2 wants access: m2 -> m
            if(m2_addressed_s1)
              begin
                s1_wb_adr_o <= m2_wb_adr_i;
                s1_wb_sel_o <= m2_wb_sel_i;
                s1_wb_we_o  <= m2_wb_we_i;
                s1_wb_dat_o <= m2_wb_dat_i;
                s1_wb_cyc_o <= 1'b1;
                s1_wb_stb_o <= 1'b1;
              end
            else if(m2_addressed_s2)
              begin
                s2_wb_adr_o <= m2_wb_adr_i;
                s2_wb_sel_o <= m2_wb_sel_i;
                s2_wb_we_o  <= m2_wb_we_i;
                s2_wb_dat_o <= m2_wb_dat_i;
                s2_wb_cyc_o <= 1'b1;
                s2_wb_stb_o <= 1'b1;
              end
            else
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
          end
        5'b10_10_1, 5'b10_11_1 :
          begin
            m1_in_progress <= 1'b0;  // m1 in progress. Cycle is finished. Send ack or err to m1.
            if(m1_addressed_s1)
              begin
                s1_wb_cyc_o <= 1'b0;
                s1_wb_stb_o <= 1'b0;
              end
            else if(m1_addressed_s2)
              begin
                s2_wb_cyc_o <= 1'b0;
                s2_wb_stb_o <= 1'b0;
              end
          end
        5'b01_01_1, 5'b01_11_1 :
          begin
            m2_in_progress <= 1'b0;  // m2 in progress. Cycle is finished. Send ack or err to m2.
            if(m2_addressed_s1)
              begin
                s1_wb_cyc_o <= 1'b0;
                s1_wb_stb_o <= 1'b0;
              end
            else if(m2_addressed_s2)
              begin
                s2_wb_cyc_o <= 1'b0;
                s2_wb_stb_o <= 1'b0;
              end
          end
      endcase
    end
end
 
// Generating Ack for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m1_addressed_s1 or m1_addressed_s2)
begin
  if(m1_in_progress)
    begin
      if(m1_addressed_s1) begin
        m1_wb_ack_o <= s1_wb_ack_i;
        m1_wb_dat_o <= s1_wb_dat_i;
      end
      else if(m1_addressed_s2) begin
        m1_wb_ack_o <= s2_wb_ack_i;
        m1_wb_dat_o <= s2_wb_dat_i;
      end
    end
  else
    m1_wb_ack_o <= 0;
end
 
 
// Generating Ack for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m2_addressed_s1 or m2_addressed_s2)
begin
  if(m2_in_progress)
    begin
      if(m2_addressed_s1) begin
        m2_wb_ack_o <= s1_wb_ack_i;
        m2_wb_dat_o <= s1_wb_dat_i;
      end
      else if(m2_addressed_s2) begin
        m2_wb_ack_o <= s2_wb_ack_i;
        m2_wb_dat_o <= s2_wb_dat_i;
      end
    end
  else
    m2_wb_ack_o <= 0;
end
 
 
// Generating Err for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or
          m1_wb_cyc_i or m1_wb_stb_i)
begin
  if(m1_in_progress)  begin
    if(m1_addressed_s1)
      m1_wb_err_o <= s1_wb_err_i;
    else if(m1_addressed_s2)
      m1_wb_err_o <= s2_wb_err_i;
  end
  else if(m1_wb_cyc_i & m1_wb_stb_i & ~m1_addressed_s1 & ~m1_addressed_s2)
    m1_wb_err_o <= 1'b1;
  else
    m1_wb_err_o <= 1'b0;
end
 
 
// Generating Err for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or
          m2_wb_cyc_i or m2_wb_stb_i)
begin
  if(m2_in_progress)  begin
    if(m2_addressed_s1)
      m2_wb_err_o <= s1_wb_err_i;
    else if(m2_addressed_s2)
      m2_wb_err_o <= s2_wb_err_i;
  end
  else if(m2_wb_cyc_i & m2_wb_stb_i & ~m2_addressed_s1 & ~m2_addressed_s2)
    m2_wb_err_o <= 1'b1;
  else
    m2_wb_err_o <= 1'b0;
end
 
 
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
 
 
// Activity monitor
integer cnt;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    cnt <= 0;
  else
  if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
    cnt <= 0;
  else
  if(s1_wb_cyc_o | s2_wb_cyc_o)
    cnt <= cnt+1;
end
 
always @ (posedge wb_clk_i)
begin
  if(cnt==1000) begin
    $display("(%0t)(%m) ERROR: WB activity ??? ", $time);
    if(s1_wb_cyc_o) begin
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
    end
    else if(s2_wb_cyc_o) begin
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
    end
 
    $stop;
  end
end
 
 
always @ (posedge wb_clk_i)
begin
  if(s1_wb_err_i & s1_wb_cyc_o) begin
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
    $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
    $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
    $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
    $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
    $stop;
  end
  if(s2_wb_err_i & s2_wb_cyc_o) begin
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
    $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
    $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
    $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
    $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
    $stop;
  end
end
 
 
 
endmodule

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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ranm11	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_cop.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/project,ethmac ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001, 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.3 2002/10/10 16:43:59 mohor`
45			`// Minor $display change.`
46			`//`
47			`// Revision 1.2 2002/09/09 12:54:13 mohor`
48			`// error acknowledge cycle termination added to display.`
49			`//`
50			`// Revision 1.1 2002/08/14 17:16:07 mohor`
51			`// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave`
52			`// interfaces:`
53			`// - Host connects to the master interface`
54			`// - Ethernet master (DMA) connects to the second master interface`
55			`// - Memory interface connects to the slave interface`
56			`// - Ethernet slave interface (access to registers and BDs) connects to second`
57			`// slave interface`
58			`//`
59			`//`
60			`//`
61			`//`
62			`//`
63			`// Created by Igor Mohor`
64			`// Changed by Ran Minerbi`
65
66			`include "timescale.v"
67
68			`module eth_cop`
69			`(`
70			`// WISHBONE common`
71			`wb_clk_i, wb_rst_i,`
72
73			`// WISHBONE MASTER 1`
74			`m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o,`
75			`m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,`
76			`m1_wb_err_o,`
77
78			`// WISHBONE MASTER 2`
79			`m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o,`
80			`m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,`
81			`m2_wb_err_o,`
82
83			`// WISHBONE slave 1`
84			`s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o,`
85			`s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,`
86			`s1_wb_dat_o,`
87
88			`// WISHBONE slave 2`
89			`s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,`
90			`s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,`
91			`s2_wb_dat_o`
92			`);`
93
94			`parameter ETH_BASE = 32'hd0000000;`
95			`parameter ETH_WIDTH = 32'h800;`
96			`parameter MEMORY_BASE = 32'h2000;`
97			`parameter MEMORY_WIDTH = 32'h10000;`
98
99			`// WISHBONE common`
100			`input wb_clk_i, wb_rst_i;`
101
102			`// WISHBONE MASTER 1`
103			`input [31:0] m1_wb_adr_i, m1_wb_dat_i;`
104			`input [3:0] m1_wb_sel_i;`
105			`input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;`
106			`output [31:0] m1_wb_dat_o;`
107			`output m1_wb_ack_o, m1_wb_err_o;`
108
109			`// WISHBONE MASTER 2`
110			`input [31:0] m2_wb_adr_i, m2_wb_dat_i;`
111			`input [3:0] m2_wb_sel_i;`
112			`input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;`
113			`output [31:0] m2_wb_dat_o;`
114			`output m2_wb_ack_o, m2_wb_err_o;`
115
116			`// WISHBONE slave 1`
117			`input [31:0] s1_wb_dat_i;`
118			`input s1_wb_ack_i, s1_wb_err_i;`
119			`output [31:0] s1_wb_adr_o, s1_wb_dat_o;`
120			`output [3:0] s1_wb_sel_o;`
121			`output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o;`
122
123			`// WISHBONE slave 2`
124			`input [31:0] s2_wb_dat_i;`
125			`input s2_wb_ack_i, s2_wb_err_i;`
126			`output [31:0] s2_wb_adr_o, s2_wb_dat_o;`
127			`output [3:0] s2_wb_sel_o;`
128			`output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o;`
129
130			`reg m1_in_progress;`
131			`reg m2_in_progress;`
132			`reg [31:0] s1_wb_adr_o;`
133			`reg [3:0] s1_wb_sel_o;`
134			`reg s1_wb_we_o;`
135			`reg [31:0] s1_wb_dat_o;`
136			`reg s1_wb_cyc_o;`
137			`reg s1_wb_stb_o;`
138			`reg [31:0] s2_wb_adr_o;`
139			`reg [3:0] s2_wb_sel_o;`
140			`reg s2_wb_we_o;`
141			`reg [31:0] s2_wb_dat_o;`
142			`reg s2_wb_cyc_o;`
143			`reg s2_wb_stb_o;`
144
145			`reg m1_wb_ack_o;`
146			`reg [31:0] m1_wb_dat_o;`
147			`reg m2_wb_ack_o;`
148			`reg [31:0] m2_wb_dat_o;`
149
150			`reg m1_wb_err_o;`
151			`reg m2_wb_err_o;`
152
153			`wire m_wb_access_finished;`
154			`wire m1_addressed_s1 = (m1_wb_adr_i >= ETH_BASE) &`
155			`(m1_wb_adr_i < (ETH_BASE + ETH_WIDTH));`
156			`wire m1_addressed_s2 = (m1_wb_adr_i >= MEMORY_BASE) &`
157			`(m1_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));`
158			`wire m2_addressed_s1 = (m2_wb_adr_i >= ETH_BASE) &`
159			`(m2_wb_adr_i < (ETH_BASE + ETH_WIDTH));`
160			`wire m2_addressed_s2 = (m2_wb_adr_i >= MEMORY_BASE) &`
161			`(m2_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));`
162
163			`wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (m1_addressed_s1 \| m1_addressed_s2);`
164			`wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (m2_addressed_s1 \| m2_addressed_s2);`
165
166			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
167			`begin`
168			`if(wb_rst_i)`
169			`begin`
170			`m1_in_progress <= 0;`
171			`m2_in_progress <= 0;`
172			`s1_wb_adr_o <= 0;`
173			`s1_wb_sel_o <= 0;`
174			`s1_wb_we_o <= 0;`
175			`s1_wb_dat_o <= 0;`
176			`s1_wb_cyc_o <= 0;`
177			`s1_wb_stb_o <= 0;`
178			`s2_wb_adr_o <= 0;`
179			`s2_wb_sel_o <= 0;`
180			`s2_wb_we_o <= 0;`
181			`s2_wb_dat_o <= 0;`
182			`s2_wb_cyc_o <= 0;`
183			`s2_wb_stb_o <= 0;`
184			`end`
185			`else`
186			`begin`
187			`case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case`
188			`5'b00_10_0, 5'b00_11_0 :`
189			`begin`
190			`m1_in_progress <= 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m`
191			`if(m1_addressed_s1)`
192			`begin`
193			`s1_wb_adr_o <= m1_wb_adr_i;`
194			`s1_wb_sel_o <= m1_wb_sel_i;`
195			`s1_wb_we_o <= m1_wb_we_i;`
196			`s1_wb_dat_o <= m1_wb_dat_i;`
197			`s1_wb_cyc_o <= 1'b1;`
198			`s1_wb_stb_o <= 1'b1;`
199			`end`
200			`else if(m1_addressed_s2)`
201			`begin`
202			`s2_wb_adr_o <= m1_wb_adr_i;`
203			`s2_wb_sel_o <= m1_wb_sel_i;`
204			`s2_wb_we_o <= m1_wb_we_i;`
205			`s2_wb_dat_o <= m1_wb_dat_i;`
206			`s2_wb_cyc_o <= 1'b1;`
207			`s2_wb_stb_o <= 1'b1;`
208			`end`
209			`else`
210			`$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);`
211			`end`
212			`5'b00_01_0 :`
213			`begin`
214			`m2_in_progress <= 1'b1; // idle: m2 wants access: m2 -> m`
215			`if(m2_addressed_s1)`
216			`begin`
217			`s1_wb_adr_o <= m2_wb_adr_i;`
218			`s1_wb_sel_o <= m2_wb_sel_i;`
219			`s1_wb_we_o <= m2_wb_we_i;`
220			`s1_wb_dat_o <= m2_wb_dat_i;`
221			`s1_wb_cyc_o <= 1'b1;`
222			`s1_wb_stb_o <= 1'b1;`
223			`end`
224			`else if(m2_addressed_s2)`
225			`begin`
226			`s2_wb_adr_o <= m2_wb_adr_i;`
227			`s2_wb_sel_o <= m2_wb_sel_i;`
228			`s2_wb_we_o <= m2_wb_we_i;`
229			`s2_wb_dat_o <= m2_wb_dat_i;`
230			`s2_wb_cyc_o <= 1'b1;`
231			`s2_wb_stb_o <= 1'b1;`
232			`end`
233			`else`
234			`$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);`
235			`end`
236			`5'b10_10_1, 5'b10_11_1 :`
237			`begin`
238			`m1_in_progress <= 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.`
239			`if(m1_addressed_s1)`
240			`begin`
241			`s1_wb_cyc_o <= 1'b0;`
242			`s1_wb_stb_o <= 1'b0;`
243			`end`
244			`else if(m1_addressed_s2)`
245			`begin`
246			`s2_wb_cyc_o <= 1'b0;`
247			`s2_wb_stb_o <= 1'b0;`
248			`end`
249			`end`
250			`5'b01_01_1, 5'b01_11_1 :`
251			`begin`
252			`m2_in_progress <= 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.`
253			`if(m2_addressed_s1)`
254			`begin`
255			`s1_wb_cyc_o <= 1'b0;`
256			`s1_wb_stb_o <= 1'b0;`
257			`end`
258			`else if(m2_addressed_s2)`
259			`begin`
260			`s2_wb_cyc_o <= 1'b0;`
261			`s2_wb_stb_o <= 1'b0;`
262			`end`
263			`end`
264			`endcase`
265			`end`
266			`end`
267
268			`// Generating Ack for master 1`
269			`always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m1_addressed_s1 or m1_addressed_s2)`
270			`begin`
271			`if(m1_in_progress)`
272			`begin`
273			`if(m1_addressed_s1) begin`
274			`m1_wb_ack_o <= s1_wb_ack_i;`
275			`m1_wb_dat_o <= s1_wb_dat_i;`
276			`end`
277			`else if(m1_addressed_s2) begin`
278			`m1_wb_ack_o <= s2_wb_ack_i;`
279			`m1_wb_dat_o <= s2_wb_dat_i;`
280			`end`
281			`end`
282			`else`
283			`m1_wb_ack_o <= 0;`
284			`end`
285
286
287			`// Generating Ack for master 2`
288			`always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m2_addressed_s1 or m2_addressed_s2)`
289			`begin`
290			`if(m2_in_progress)`
291			`begin`
292			`if(m2_addressed_s1) begin`
293			`m2_wb_ack_o <= s1_wb_ack_i;`
294			`m2_wb_dat_o <= s1_wb_dat_i;`
295			`end`
296			`else if(m2_addressed_s2) begin`
297			`m2_wb_ack_o <= s2_wb_ack_i;`
298			`m2_wb_dat_o <= s2_wb_dat_i;`
299			`end`
300			`end`
301			`else`
302			`m2_wb_ack_o <= 0;`
303			`end`
304
305
306			`// Generating Err for master 1`
307			`always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or`
308			`m1_wb_cyc_i or m1_wb_stb_i)`
309			`begin`
310			`if(m1_in_progress) begin`
311			`if(m1_addressed_s1)`
312			`m1_wb_err_o <= s1_wb_err_i;`
313			`else if(m1_addressed_s2)`
314			`m1_wb_err_o <= s2_wb_err_i;`
315			`end`
316			`else if(m1_wb_cyc_i & m1_wb_stb_i & ~m1_addressed_s1 & ~m1_addressed_s2)`
317			`m1_wb_err_o <= 1'b1;`
318			`else`
319			`m1_wb_err_o <= 1'b0;`
320			`end`
321
322
323			`// Generating Err for master 2`
324			`always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or`
325			`m2_wb_cyc_i or m2_wb_stb_i)`
326			`begin`
327			`if(m2_in_progress) begin`
328			`if(m2_addressed_s1)`
329			`m2_wb_err_o <= s1_wb_err_i;`
330			`else if(m2_addressed_s2)`
331			`m2_wb_err_o <= s2_wb_err_i;`
332			`end`
333			`else if(m2_wb_cyc_i & m2_wb_stb_i & ~m2_addressed_s1 & ~m2_addressed_s2)`
334			`m2_wb_err_o <= 1'b1;`
335			`else`
336			`m2_wb_err_o <= 1'b0;`
337			`end`
338
339
340			`assign m_wb_access_finished = m1_wb_ack_o \| m1_wb_err_o \| m2_wb_ack_o \| m2_wb_err_o;`
341
342
343			`// Activity monitor`
344			`integer cnt;`
345			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
346			`begin`
347			`if(wb_rst_i)`
348			`cnt <= 0;`
349			`else`
350			`if(s1_wb_ack_i \| s1_wb_err_i \| s2_wb_ack_i \| s2_wb_err_i)`
351			`cnt <= 0;`
352			`else`
353			`if(s1_wb_cyc_o \| s2_wb_cyc_o)`
354			`cnt <= cnt+1;`
355			`end`
356
357			`always @ (posedge wb_clk_i)`
358			`begin`
359			`if(cnt==1000) begin`
360			`$display("(%0t)(%m) ERROR: WB activity ??? ", $time);`
361			`if(s1_wb_cyc_o) begin`
362			`$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);`
363			`$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);`
364			`$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);`
365			`$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);`
366			`end`
367			`else if(s2_wb_cyc_o) begin`
368			`$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);`
369			`$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);`
370			`$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);`
371			`$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);`
372			`end`
373
374			`$stop;`
375			`end`
376			`end`
377
378
379			`always @ (posedge wb_clk_i)`
380			`begin`
381			`if(s1_wb_err_i & s1_wb_cyc_o) begin`
382			`$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);`
383			`$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);`
384			`$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);`
385			`$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);`
386			`$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);`
387			`$stop;`
388			`end`
389			`if(s2_wb_err_i & s2_wb_cyc_o) begin`
390			`$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);`
391			`$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);`
392			`$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);`
393			`$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);`
394			`$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);`
395			`$stop;`
396			`end`
397			`end`
398
399
400
401			`endmodule`