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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/project,ethmac                     ////
7
////                                                              ////
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////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001, 2002 Authors                             ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44
// Revision 1.28  2004/04/26 15:26:23  igorm
45
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
46
//   previous update of the core.
47
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
48
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
49
//   register. (thanks to Mathias and Torbjorn)
50
// - Multicast reception was fixed. Thanks to Ulrich Gries
51
//
52
// Revision 1.27  2004/04/26 11:42:17  igorm
53
// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
54
//
55
// Revision 1.26  2003/11/12 18:24:59  tadejm
56
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
57
//
58
// Revision 1.25  2003/04/18 16:26:25  mohor
59
// RxBDAddress was updated also when value to r_TxBDNum was written with
60
// greater value than allowed.
61
//
62
// Revision 1.24  2002/11/22 01:57:06  mohor
63
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
64
// synchronized.
65
//
66
// Revision 1.23  2002/11/19 18:13:49  mohor
67
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
68
//
69
// Revision 1.22  2002/11/14 18:37:20  mohor
70
// r_Rst signal does not reset any module any more and is removed from the design.
71
//
72
// Revision 1.21  2002/09/10 10:35:23  mohor
73
// Ethernet debug registers removed.
74
//
75
// Revision 1.20  2002/09/04 18:40:25  mohor
76
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
77
// the control frames connected.
78
//
79
// Revision 1.19  2002/08/19 16:01:40  mohor
80
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
81
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
82
//
83
// Revision 1.18  2002/08/16 22:28:23  mohor
84
// Syntax error fixed.
85
//
86
// Revision 1.17  2002/08/16 22:23:03  mohor
87
// Syntax error fixed.
88
//
89
// Revision 1.16  2002/08/16 22:14:22  mohor
90
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
91
// changed from bit position 10 to 9.
92
//
93
// Revision 1.15  2002/08/14 18:26:37  mohor
94
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
95
//
96
// Revision 1.14  2002/04/22 14:03:44  mohor
97
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
98
// or not.
99
//
100
// Revision 1.13  2002/02/26 16:18:09  mohor
101
// Reset values are passed to registers through parameters
102
//
103
// Revision 1.12  2002/02/17 13:23:42  mohor
104
// Define missmatch fixed.
105
//
106
// Revision 1.11  2002/02/16 14:03:44  mohor
107
// Registered trimmed. Unused registers removed.
108
//
109
// Revision 1.10  2002/02/15 11:08:25  mohor
110
// File format fixed a bit.
111
//
112
// Revision 1.9  2002/02/14 20:19:41  billditt
113
// Modified for Address Checking,
114
// addition of eth_addrcheck.v
115
//
116
// Revision 1.8  2002/02/12 17:01:19  mohor
117
// HASH0 and HASH1 registers added. 
118
 
119
// Revision 1.7  2002/01/23 10:28:16  mohor
120
// Link in the header changed.
121
//
122
// Revision 1.6  2001/12/05 15:00:16  mohor
123
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
124
// instead of the number of RX descriptors).
125
//
126
// Revision 1.5  2001/12/05 10:22:19  mohor
127
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
128
//
129
// Revision 1.4  2001/10/19 08:43:51  mohor
130
// eth_timescale.v changed to timescale.v This is done because of the
131
// simulation of the few cores in a one joined project.
132
//
133
// Revision 1.3  2001/10/18 12:07:11  mohor
134
// Status signals changed, Adress decoding changed, interrupt controller
135
// added.
136
//
137
// Revision 1.2  2001/09/24 15:02:56  mohor
138
// Defines changed (All precede with ETH_). Small changes because some
139
// tools generate warnings when two operands are together. Synchronization
140
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
141
// demands).
142
//
143
// Revision 1.1  2001/08/06 14:44:29  mohor
144
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
145
// Include files fixed to contain no path.
146
// File names and module names changed ta have a eth_ prologue in the name.
147
// File eth_timescale.v is used to define timescale
148
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
149
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
150
// and Mdo_OE. The bidirectional signal must be created on the top level. This
151
// is done due to the ASIC tools.
152
//
153
// Revision 1.2  2001/08/02 09:25:31  mohor
154
// Unconnected signals are now connected.
155
//
156
// Revision 1.1  2001/07/30 21:23:42  mohor
157
// Directory structure changed. Files checked and joind together.
158
//
159
//
160
//
161
//
162
//
163
//
164
 
165
`include "ethmac_defines.v"
166
`include "timescale.v"
167
 
168
 
169
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
170
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
171
                      r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
172
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
173
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
174
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
175
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
176
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
177
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
178
                      LinkFail, r_MAC, r_DMAC, WCtrlDataStart, RStatStart,
179
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
180
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
181
                      dbg_dat,
182
                      StartTxDone, TxClk, RxClk, SetPauseTimer
183
                    );
184
 
185
input [31:0] DataIn;
186
input [7:0] Address;
187
 
188
input Rw;
189
input [3:0] Cs;
190
input Clk;
191
input Reset;
192
 
193
input WCtrlDataStart;
194
input RStatStart;
195
 
196
input UpdateMIIRX_DATAReg;
197
input [15:0] Prsd;
198
 
199
output [31:0] DataOut;
200
reg    [31:0] DataOut;
201
 
202
output r_RecSmall;
203
output r_Pad;
204
output r_HugEn;
205
output r_CrcEn;
206
output r_DlyCrcEn;
207
output r_FullD;
208
output r_ExDfrEn;
209
output r_NoBckof;
210
output r_LoopBck;
211
output r_IFG;
212
output r_Pro;
213
output r_Iam;
214
output r_Bro;
215
output r_NoPre;
216
output r_TxEn;
217
output r_RxEn;
218
output [31:0] r_HASH0;
219
output [31:0] r_HASH1;
220
 
221
input TxB_IRQ;
222
input TxE_IRQ;
223
input RxB_IRQ;
224
input RxE_IRQ;
225
input Busy_IRQ;
226
 
227
output [6:0] r_IPGT;
228
 
229
output [6:0] r_IPGR1;
230
 
231
output [6:0] r_IPGR2;
232
 
233
output [15:0] r_MinFL;
234
output [15:0] r_MaxFL;
235
 
236
output [3:0] r_MaxRet;
237
output [5:0] r_CollValid;
238
 
239
output r_TxFlow;
240
output r_RxFlow;
241
output r_PassAll;
242
 
243
output r_MiiNoPre;
244
output [7:0] r_ClkDiv;
245
 
246
output r_WCtrlData;
247
output r_RStat;
248
output r_ScanStat;
249
 
250
output [4:0] r_RGAD;
251
output [4:0] r_FIAD;
252
 
253
output [15:0]r_CtrlData;
254
 
255
 
256
input NValid_stat;
257
input Busy_stat;
258
input LinkFail;
259
 
260
output [47:0] r_MAC , r_DMAC;
261
output [7:0] r_TxBDNum;
262
output       int_o;
263
output [15:0]r_TxPauseTV;
264
output       r_TxPauseRq;
265
input        RstTxPauseRq;
266
input        TxCtrlEndFrm;
267
input        StartTxDone;
268
input        TxClk;
269
input        RxClk;
270
input        SetPauseTimer;
271
 
272
input [31:0] dbg_dat; // debug data input
273
 
274
reg          irq_txb;
275
reg          irq_txe;
276
reg          irq_rxb;
277
reg          irq_rxe;
278
reg          irq_busy;
279
reg          irq_txc;
280
reg          irq_rxc;
281
 
282
reg SetTxCIrq_txclk;
283
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
284
reg SetTxCIrq;
285
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
286
 
287
reg SetRxCIrq_rxclk;
288
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
289
reg SetRxCIrq;
290
reg ResetRxCIrq_sync1;
291
reg ResetRxCIrq_sync2;
292
reg ResetRxCIrq_sync3;
293
 
294
wire [3:0] Write =   Cs  & {4{Rw}};
295
wire       Read  = (|Cs) &   ~Rw;
296
 
297
wire MODER_Sel      = (Address == `ETH_MODER_ADR       );
298
wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR  );
299
wire INT_MASK_Sel   = (Address == `ETH_INT_MASK_ADR    );
300
wire IPGT_Sel       = (Address == `ETH_IPGT_ADR        );
301
wire IPGR1_Sel      = (Address == `ETH_IPGR1_ADR       );
302
wire IPGR2_Sel      = (Address == `ETH_IPGR2_ADR       );
303
wire PACKETLEN_Sel  = (Address == `ETH_PACKETLEN_ADR   );
304
wire COLLCONF_Sel   = (Address == `ETH_COLLCONF_ADR    );
305
 
306
wire CTRLMODER_Sel  = (Address == `ETH_CTRLMODER_ADR   );
307
wire MIIMODER_Sel   = (Address == `ETH_MIIMODER_ADR    );
308
wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR  );
309
wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR  );
310
wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR  );
311
wire MAC_ADDR0_Sel  = (Address == `ETH_MAC_ADDR0_ADR   );
312
wire MAC_ADDR1_Sel  = (Address == `ETH_MAC_ADDR1_ADR   );
313
wire DMAC_ADDR0_Sel = (Address == `ETH_DMAC_ADDR0_ADR   );
314
wire DMAC_ADDR1_Sel = (Address == `ETH_DMAC_ADDR1_ADR   );
315
wire HASH0_Sel      = (Address == `ETH_HASH0_ADR       );
316
wire HASH1_Sel      = (Address == `ETH_HASH1_ADR       );
317
wire TXCTRL_Sel     = (Address == `ETH_TX_CTRL_ADR     );
318
wire RXCTRL_Sel     = (Address == `ETH_RX_CTRL_ADR     );
319
wire DBG_REG_Sel    = (Address == `ETH_DBG_ADR         );
320
wire TX_BD_NUM_Sel  = (Address == `ETH_TX_BD_NUM_ADR   );
321
wire IPv4_L1_Sel    = (Address == `ETH_IPv4_L1_ADR     );  //add to ethmac_defines.v
322
 
323
wire [2:0] MODER_Wr;
324
wire [0:0] INT_SOURCE_Wr;
325
wire [0:0] INT_MASK_Wr;
326
wire [0:0] IPGT_Wr;
327
wire [0:0] IPGR1_Wr;
328
wire [0:0] IPGR2_Wr;
329
wire [3:0] PACKETLEN_Wr;
330
wire [2:0] COLLCONF_Wr;
331
wire [0:0] CTRLMODER_Wr;
332
wire [1:0] MIIMODER_Wr;
333
wire [0:0] MIICOMMAND_Wr;
334
wire [1:0] MIIADDRESS_Wr;
335
wire [1:0] MIITX_DATA_Wr;
336
wire       MIIRX_DATA_Wr;
337
wire [3:0] MAC_ADDR0_Wr;
338
wire [1:0] MAC_ADDR1_Wr;
339
wire [3:0] DMAC_ADDR0_Wr;
340
wire [1:0] DMAC_ADDR1_Wr;
341
wire [3:0] HASH0_Wr;
342
wire [3:0] HASH1_Wr;
343
wire [2:0] TXCTRL_Wr;
344
wire [0:0] TX_BD_NUM_Wr;
345
wire [3:0] IPv4_L1_Wr;
346
 
347
assign MODER_Wr[0]       = Write[0]  & MODER_Sel;
348
assign MODER_Wr[1]       = Write[1]  & MODER_Sel;
349
assign MODER_Wr[2]       = Write[2]  & MODER_Sel;
350
assign INT_SOURCE_Wr[0]  = Write[0]  & INT_SOURCE_Sel;
351
assign INT_MASK_Wr[0]    = Write[0]  & INT_MASK_Sel;
352
assign IPGT_Wr[0]        = Write[0]  & IPGT_Sel;
353
assign IPGR1_Wr[0]       = Write[0]  & IPGR1_Sel;
354
assign IPGR2_Wr[0]       = Write[0]  & IPGR2_Sel;
355
assign PACKETLEN_Wr[0]   = Write[0]  & PACKETLEN_Sel;
356
assign PACKETLEN_Wr[1]   = Write[1]  & PACKETLEN_Sel;
357
assign PACKETLEN_Wr[2]   = Write[2]  & PACKETLEN_Sel;
358
assign PACKETLEN_Wr[3]   = Write[3]  & PACKETLEN_Sel;
359
assign COLLCONF_Wr[0]    = Write[0]  & COLLCONF_Sel;
360
assign COLLCONF_Wr[1]    = 1'b0;  // Not used
361
assign COLLCONF_Wr[2]    = Write[2]  & COLLCONF_Sel;
362
 
363
assign CTRLMODER_Wr[0]   = Write[0]  & CTRLMODER_Sel;
364
assign MIIMODER_Wr[0]    = Write[0]  & MIIMODER_Sel;
365
assign MIIMODER_Wr[1]    = Write[1]  & MIIMODER_Sel;
366
assign MIICOMMAND_Wr[0]  = Write[0]  & MIICOMMAND_Sel;
367
assign MIIADDRESS_Wr[0]  = Write[0]  & MIIADDRESS_Sel;
368
assign MIIADDRESS_Wr[1]  = Write[1]  & MIIADDRESS_Sel;
369
assign MIITX_DATA_Wr[0]  = Write[0]  & MIITX_DATA_Sel;
370
assign MIITX_DATA_Wr[1]  = Write[1]  & MIITX_DATA_Sel;
371
assign MIIRX_DATA_Wr     = UpdateMIIRX_DATAReg;
372
assign MAC_ADDR0_Wr[0]   = Write[0]  & MAC_ADDR0_Sel;
373
assign MAC_ADDR0_Wr[1]   = Write[1]  & MAC_ADDR0_Sel;
374
assign MAC_ADDR0_Wr[2]   = Write[2]  & MAC_ADDR0_Sel;
375
assign MAC_ADDR0_Wr[3]   = Write[3]  & MAC_ADDR0_Sel;
376
assign MAC_ADDR1_Wr[0]   = Write[0]  & MAC_ADDR1_Sel;
377
assign MAC_ADDR1_Wr[1]   = Write[1]  & MAC_ADDR1_Sel;
378
assign DMAC_ADDR0_Wr[0]  = Write[0]  & DMAC_ADDR0_Sel;
379
assign DMAC_ADDR0_Wr[1]  = Write[1]  & DMAC_ADDR0_Sel;
380
assign DMAC_ADDR0_Wr[2]  = Write[2]  & DMAC_ADDR0_Sel;
381
assign DMAC_ADDR0_Wr[3]  = Write[3]  & DMAC_ADDR0_Sel;
382
assign DMAC_ADDR1_Wr[0]  = Write[0]  & DMAC_ADDR1_Sel;
383
assign DMAC_ADDR1_Wr[1]  = Write[1]  & DMAC_ADDR1_Sel;
384
assign HASH0_Wr[0]       = Write[0]  & HASH0_Sel;
385
assign HASH0_Wr[1]       = Write[1]  & HASH0_Sel;
386
assign HASH0_Wr[2]       = Write[2]  & HASH0_Sel;
387
assign HASH0_Wr[3]       = Write[3]  & HASH0_Sel;
388
assign HASH1_Wr[0]       = Write[0]  & HASH1_Sel;
389
assign HASH1_Wr[1]       = Write[1]  & HASH1_Sel;
390
assign HASH1_Wr[2]       = Write[2]  & HASH1_Sel;
391
assign HASH1_Wr[3]       = Write[3]  & HASH1_Sel;
392
assign TXCTRL_Wr[0]      = Write[0]  & TXCTRL_Sel;
393
assign TXCTRL_Wr[1]      = Write[1]  & TXCTRL_Sel;
394
assign TXCTRL_Wr[2]      = Write[2]  & TXCTRL_Sel;
395
assign TX_BD_NUM_Wr[0]   = Write[0]  & TX_BD_NUM_Sel & (DataIn<='h80);
396
assign IPv4_L1_Wr[0]     = Write[0]  & IPv4_L1_Sel;
397
assign IPv4_L1_Wr[1]     = Write[1]  & IPv4_L1_Sel;
398
assign IPv4_L1_Wr[2]     = Write[2]  & IPv4_L1_Sel;
399
assign IPv4_L1_Wr[3]     = Write[3]  & IPv4_L1_Sel;
400
 
401
wire [31:0] MODEROut;
402
wire [31:0] INT_SOURCEOut;
403
wire [31:0] INT_MASKOut;
404
wire [31:0] IPGTOut;
405
wire [31:0] IPGR1Out;
406
wire [31:0] IPGR2Out;
407
wire [31:0] PACKETLENOut;
408
wire [31:0] COLLCONFOut;
409
wire [31:0] CTRLMODEROut;
410
wire [31:0] MIIMODEROut;
411
wire [31:0] MIICOMMANDOut;
412
wire [31:0] MIIADDRESSOut;
413
wire [31:0] MIITX_DATAOut;
414
wire [31:0] MIIRX_DATAOut;
415
wire [31:0] MIISTATUSOut;
416
wire [31:0] MAC_ADDR0Out;
417
wire [31:0] DMAC_ADDR1Out;
418
wire [31:0] DMAC_ADDR0Out;
419
wire [31:0] MAC_ADDR1Out;
420
wire [31:0] TX_BD_NUMOut;
421
wire [31:0] HASH0Out;
422
wire [31:0] HASH1Out;
423
wire [31:0] TXCTRLOut;
424
wire [31:0] DBGOut;
425
wire [31:0] IPv4_L1_out;
426
// MODER Register
427
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0)        MODER_0
428
  (
429
   .DataIn    (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
430
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
431
   .Write     (MODER_Wr[0]),
432
   .Clk       (Clk),
433
   .Reset     (Reset),
434
   .SyncReset (1'b0)
435
  );
436
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1)        MODER_1
437
  (
438
   .DataIn    (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
439
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
440
   .Write     (MODER_Wr[1]),
441
   .Clk       (Clk),
442
   .Reset     (Reset),
443
   .SyncReset (1'b0)
444
  );
445
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2)        MODER_2
446
  (
447
   .DataIn    (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
448
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
449
   .Write     (MODER_Wr[2]),
450
   .Clk       (Clk),
451
   .Reset     (Reset),
452
   .SyncReset (1'b0)
453
  );
454
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
455
 
456
// INT_MASK Register
457
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0)  INT_MASK_0
458
  (
459
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
460
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
461
   .Write     (INT_MASK_Wr[0]),
462
   .Clk       (Clk),
463
   .Reset     (Reset),
464
   .SyncReset (1'b0)
465
  );
466
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
467
 
468
// IPGT Register
469
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0)          IPGT_0
470
  (
471
   .DataIn    (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
472
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
473
   .Write     (IPGT_Wr[0]),
474
   .Clk       (Clk),
475
   .Reset     (Reset),
476
   .SyncReset (1'b0)
477
  );
478
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
479
 
480
// IPGR1 Register
481
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0)        IPGR1_0
482
  (
483
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
484
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
485
   .Write     (IPGR1_Wr[0]),
486
   .Clk       (Clk),
487
   .Reset     (Reset),
488
   .SyncReset (1'b0)
489
  );
490
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
491
 
492
// IPGR2 Register
493
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0)        IPGR2_0
494
  (
495
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
496
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
497
   .Write     (IPGR2_Wr[0]),
498
   .Clk       (Clk),
499
   .Reset     (Reset),
500
   .SyncReset (1'b0)
501
  );
502
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
503
 
504
// PACKETLEN Register
505
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
506
  (
507
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
508
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
509
   .Write     (PACKETLEN_Wr[0]),
510
   .Clk       (Clk),
511
   .Reset     (Reset),
512
   .SyncReset (1'b0)
513
  );
514
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
515
  (
516
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
517
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
518
   .Write     (PACKETLEN_Wr[1]),
519
   .Clk       (Clk),
520
   .Reset     (Reset),
521
   .SyncReset (1'b0)
522
  );
523
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
524
  (
525
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
526
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
527
   .Write     (PACKETLEN_Wr[2]),
528
   .Clk       (Clk),
529
   .Reset     (Reset),
530
   .SyncReset (1'b0)
531
  );
532
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
533
  (
534
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
535
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
536
   .Write     (PACKETLEN_Wr[3]),
537
   .Clk       (Clk),
538
   .Reset     (Reset),
539
   .SyncReset (1'b0)
540
  );
541
 
542
// COLLCONF Register
543
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0)   COLLCONF_0
544
  (
545
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
546
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
547
   .Write     (COLLCONF_Wr[0]),
548
   .Clk       (Clk),
549
   .Reset     (Reset),
550
   .SyncReset (1'b0)
551
  );
552
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2)   COLLCONF_2
553
  (
554
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
555
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
556
   .Write     (COLLCONF_Wr[2]),
557
   .Clk       (Clk),
558
   .Reset     (Reset),
559
   .SyncReset (1'b0)
560
  );
561
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
562
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
563
 
564
// TX_BD_NUM Register
565
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
566
  (
567
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
568
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
569
   .Write     (TX_BD_NUM_Wr[0]),
570
   .Clk       (Clk),
571
   .Reset     (Reset),
572
   .SyncReset (1'b0)
573
  );
574
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
575
 
576
// CTRLMODER Register
577
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0)  CTRLMODER_0
578
  (
579
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
580
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
581
   .Write     (CTRLMODER_Wr[0]),
582
   .Clk       (Clk),
583
   .Reset     (Reset),
584
   .SyncReset (1'b0)
585
  );
586
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
587
 
588
// MIIMODER Register
589
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0)    MIIMODER_0
590
  (
591
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
592
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
593
   .Write     (MIIMODER_Wr[0]),
594
   .Clk       (Clk),
595
   .Reset     (Reset),
596
   .SyncReset (1'b0)
597
  );
598
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1)    MIIMODER_1
599
  (
600
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
601
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
602
   .Write     (MIIMODER_Wr[1]),
603
   .Clk       (Clk),
604
   .Reset     (Reset),
605
   .SyncReset (1'b0)
606
  );
607
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
608
 
609
// MIICOMMAND Register
610
eth_register #(1, 0)                                      MIICOMMAND0
611
  (
612
   .DataIn    (DataIn[0]),
613
   .DataOut   (MIICOMMANDOut[0]),
614
   .Write     (MIICOMMAND_Wr[0]),
615
   .Clk       (Clk),
616
   .Reset     (Reset),
617
   .SyncReset (1'b0)
618
  );
619
eth_register #(1, 0)                                      MIICOMMAND1
620
  (
621
   .DataIn    (DataIn[1]),
622
   .DataOut   (MIICOMMANDOut[1]),
623
   .Write     (MIICOMMAND_Wr[0]),
624
   .Clk       (Clk),
625
   .Reset     (Reset),
626
   .SyncReset (RStatStart)
627
  );
628
eth_register #(1, 0)                                      MIICOMMAND2
629
  (
630
   .DataIn    (DataIn[2]),
631
   .DataOut   (MIICOMMANDOut[2]),
632
   .Write     (MIICOMMAND_Wr[0]),
633
   .Clk       (Clk),
634
   .Reset     (Reset),
635
   .SyncReset (WCtrlDataStart)
636
  );
637
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
638
 
639
// MIIADDRESSRegister
640
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
641
  (
642
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
643
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
644
   .Write     (MIIADDRESS_Wr[0]),
645
   .Clk       (Clk),
646
   .Reset     (Reset),
647
   .SyncReset (1'b0)
648
  );
649
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
650
  (
651
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
652
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
653
   .Write     (MIIADDRESS_Wr[1]),
654
   .Clk       (Clk),
655
   .Reset     (Reset),
656
   .SyncReset (1'b0)
657
  );
658
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
659
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
660
 
661
// MIITX_DATA Register
662
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
663
  (
664
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
665
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
666
   .Write     (MIITX_DATA_Wr[0]),
667
   .Clk       (Clk),
668
   .Reset     (Reset),
669
   .SyncReset (1'b0)
670
  );
671
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
672
  (
673
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
674
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
675
   .Write     (MIITX_DATA_Wr[1]),
676
   .Clk       (Clk),
677
   .Reset     (Reset),
678
   .SyncReset (1'b0)
679
  );
680
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
681
 
682
// MIIRX_DATA Register
683
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
684
  (
685
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
686
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
687
   .Write     (MIIRX_DATA_Wr), // not written from WB
688
   .Clk       (Clk),
689
   .Reset     (Reset),
690
   .SyncReset (1'b0)
691
  );
692
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
693
 
694
// MAC_ADDR0 Register
695
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0)  MAC_ADDR0_0
696
  (
697
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
698
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
699
   .Write     (MAC_ADDR0_Wr[0]),
700
   .Clk       (Clk),
701
   .Reset     (Reset),
702
   .SyncReset (1'b0)
703
  );
704
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1)  MAC_ADDR0_1
705
  (
706
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
707
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
708
   .Write     (MAC_ADDR0_Wr[1]),
709
   .Clk       (Clk),
710
   .Reset     (Reset),
711
   .SyncReset (1'b0)
712
  );
713
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2)  MAC_ADDR0_2
714
  (
715
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
716
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
717
   .Write     (MAC_ADDR0_Wr[2]),
718
   .Clk       (Clk),
719
   .Reset     (Reset),
720
   .SyncReset (1'b0)
721
  );
722
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3)  MAC_ADDR0_3
723
  (
724
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
725
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
726
   .Write     (MAC_ADDR0_Wr[3]),
727
   .Clk       (Clk),
728
   .Reset     (Reset),
729
   .SyncReset (1'b0)
730
  );
731
 
732
// MAC_ADDR1 Register
733
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0)  MAC_ADDR1_0
734
  (
735
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
736
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
737
   .Write     (MAC_ADDR1_Wr[0]),
738
   .Clk       (Clk),
739
   .Reset     (Reset),
740
   .SyncReset (1'b0)
741
  );
742
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1)  MAC_ADDR1_1
743
  (
744
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
745
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
746
   .Write     (MAC_ADDR1_Wr[1]),
747
   .Clk       (Clk),
748
   .Reset     (Reset),
749
   .SyncReset (1'b0)
750
  );
751
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
752
 
753
// DMAC_ADDR0 Register
754
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0)  DMAC_ADDR0_0
755
  (
756
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
757
   .DataOut   (DMAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
758
   .Write     (DMAC_ADDR0_Wr[0]),
759
   .Clk       (Clk),
760
   .Reset     (Reset),
761
   .SyncReset (1'b0)
762
  );
763
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1)  DMAC_ADDR0_1
764
  (
765
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
766
   .DataOut   (DMAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
767
   .Write     (DMAC_ADDR0_Wr[1]),
768
   .Clk       (Clk),
769
   .Reset     (Reset),
770
   .SyncReset (1'b0)
771
  );
772
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2)  DMAC_ADDR0_2
773
  (
774
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
775
   .DataOut   (DMAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
776
   .Write     (DMAC_ADDR0_Wr[2]),
777
   .Clk       (Clk),
778
   .Reset     (Reset),
779
   .SyncReset (1'b0)
780
  );
781
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3)  DMAC_ADDR0_3
782
  (
783
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
784
   .DataOut   (DMAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
785
   .Write     (DMAC_ADDR0_Wr[3]),
786
   .Clk       (Clk),
787
   .Reset     (Reset),
788
   .SyncReset (1'b0)
789
  );
790
 
791
// DMAC_ADDR1 Register
792
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0)  DMAC_ADDR1_0
793
  (
794
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
795
   .DataOut   (DMAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
796
   .Write     (DMAC_ADDR1_Wr[0]),
797
   .Clk       (Clk),
798
   .Reset     (Reset),
799
   .SyncReset (1'b0)
800
  );
801
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1)  DMAC_ADDR1_1
802
  (
803
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
804
   .DataOut   (DMAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
805
   .Write     (DMAC_ADDR1_Wr[1]),
806
   .Clk       (Clk),
807
   .Reset     (Reset),
808
   .SyncReset (1'b0)
809
  );
810
assign DMAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
811
 
812
 
813
// RXHASH0 Register
814
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0)          RXHASH0_0
815
  (
816
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
817
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
818
   .Write     (HASH0_Wr[0]),
819
   .Clk       (Clk),
820
   .Reset     (Reset),
821
   .SyncReset (1'b0)
822
  );
823
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1)          RXHASH0_1
824
  (
825
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
826
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
827
   .Write     (HASH0_Wr[1]),
828
   .Clk       (Clk),
829
   .Reset     (Reset),
830
   .SyncReset (1'b0)
831
  );
832
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2)          RXHASH0_2
833
  (
834
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
835
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
836
   .Write     (HASH0_Wr[2]),
837
   .Clk       (Clk),
838
   .Reset     (Reset),
839
   .SyncReset (1'b0)
840
  );
841
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3)          RXHASH0_3
842
  (
843
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
844
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
845
   .Write     (HASH0_Wr[3]),
846
   .Clk       (Clk),
847
   .Reset     (Reset),
848
   .SyncReset (1'b0)
849
  );
850
 
851
// RXHASH1 Register
852
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0)          RXHASH1_0
853
  (
854
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
855
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
856
   .Write     (HASH1_Wr[0]),
857
   .Clk       (Clk),
858
   .Reset     (Reset),
859
   .SyncReset (1'b0)
860
  );
861
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1)          RXHASH1_1
862
  (
863
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
864
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
865
   .Write     (HASH1_Wr[1]),
866
   .Clk       (Clk),
867
   .Reset     (Reset),
868
   .SyncReset (1'b0)
869
  );
870
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2)          RXHASH1_2
871
  (
872
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
873
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
874
   .Write     (HASH1_Wr[2]),
875
   .Clk       (Clk),
876
   .Reset     (Reset),
877
   .SyncReset (1'b0)
878
  );
879
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3)          RXHASH1_3
880
  (
881
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
882
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
883
   .Write     (HASH1_Wr[3]),
884
   .Clk       (Clk),
885
   .Reset     (Reset),
886
   .SyncReset (1'b0)
887
  );
888
 
889
// TXCTRL Register
890
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0)  TXCTRL_0
891
  (
892
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
893
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
894
   .Write     (TXCTRL_Wr[0]),
895
   .Clk       (Clk),
896
   .Reset     (Reset),
897
   .SyncReset (1'b0)
898
  );
899
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1)  TXCTRL_1
900
  (
901
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
902
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
903
   .Write     (TXCTRL_Wr[1]),
904
   .Clk       (Clk),
905
   .Reset     (Reset),
906
   .SyncReset (1'b0)
907
  );
908
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2)  TXCTRL_2 // Request bit is synchronously reset
909
  (
910
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
911
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
912
   .Write     (TXCTRL_Wr[2]),
913
   .Clk       (Clk),
914
   .Reset     (Reset),
915
   .SyncReset (RstTxPauseRq)
916
  );
917
 
918
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
919
 
920
eth_register #(`ETH_IPv4_L1_WIDTH_0, `ETH_IPv4_L1_DEF_0)  IPv4_L1_0
921
  (
922
   .DataIn    (DataIn[`ETH_IPv4_L1_WIDTH_0 -1:0]),
923
   .DataOut   (IPv4_L1_out[`ETH_IPv4_L1_WIDTH_0 -1:0]),
924
   .Write     (IPv4_L1_Wr[0]),
925
   .Clk       (Clk),
926
   .Reset     (Reset),
927
   .SyncReset (1'b0)
928
  );
929
eth_register #(`ETH_IPv4_L1_WIDTH_1, `ETH_IPv4_L1_DEF_1)  IPv4_L1_1
930
  (
931
   .DataIn    (DataIn[`ETH_IPv4_L1_WIDTH_1 + 7:8]),
932
   .DataOut   (IPv4_L1_out[`ETH_IPv4_L1_WIDTH_1 + 7:8]),
933
   .Write     (IPv4_L1_Wr[1]),
934
   .Clk       (Clk),
935
   .Reset     (Reset),
936
   .SyncReset (1'b0)
937
  );
938
eth_register #(`ETH_IPv4_L1_WIDTH_2, `ETH_IPv4_L1_DEF_2)  IPv4_L1_2
939
  (
940
   .DataIn    (DataIn[`ETH_IPv4_L1_WIDTH_2 + 15:16]),
941
   .DataOut   (IPv4_L1_out[`ETH_IPv4_L1_WIDTH_2 + 15:16]),
942
   .Write     (IPv4_L1_Wr[2]),
943
   .Clk       (Clk),
944
   .Reset     (Reset),
945
   .SyncReset (1'b0)
946
  );
947
eth_register #(`ETH_IPv4_L1_WIDTH_3, `ETH_IPv4_L1_DEF_3)  IPv4_L1_3
948
  (
949
   .DataIn    (DataIn[`ETH_IPv4_L1_WIDTH_2 + 23:24]),
950
   .DataOut   (IPv4_L1_out[`ETH_IPv4_L1_WIDTH_2 + 23:24]),
951
   .Write     (IPv4_L1_Wr[3]),
952
   .Clk       (Clk),
953
   .Reset     (Reset),
954
   .SyncReset (1'b0)
955
  );
956
 
957
 
958
// Reading data from registers
959
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
960
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
961
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
962
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
963
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
964
          HASH0Out      or HASH1Out       or TXCTRLOut      or IPv4_L1_out
965
         )
966
begin
967
  if(Read)  // read
968
    begin
969
      case(Address)
970
        `ETH_MODER_ADR        :  DataOut=MODEROut;
971
        `ETH_INT_SOURCE_ADR   :  DataOut=INT_SOURCEOut;
972
        `ETH_INT_MASK_ADR     :  DataOut=INT_MASKOut;
973
        `ETH_IPGT_ADR         :  DataOut=IPGTOut;
974
        `ETH_IPGR1_ADR        :  DataOut=IPGR1Out;
975
        `ETH_IPGR2_ADR        :  DataOut=IPGR2Out;
976
        `ETH_PACKETLEN_ADR    :  DataOut=PACKETLENOut;
977
        `ETH_COLLCONF_ADR     :  DataOut=COLLCONFOut;
978
        `ETH_CTRLMODER_ADR    :  DataOut=CTRLMODEROut;
979
        `ETH_MIIMODER_ADR     :  DataOut=MIIMODEROut;
980
        `ETH_MIICOMMAND_ADR   :  DataOut=MIICOMMANDOut;
981
        `ETH_MIIADDRESS_ADR   :  DataOut=MIIADDRESSOut;
982
        `ETH_MIITX_DATA_ADR   :  DataOut=MIITX_DATAOut;
983
        `ETH_MIIRX_DATA_ADR   :  DataOut=MIIRX_DATAOut;
984
        `ETH_MIISTATUS_ADR    :  DataOut=MIISTATUSOut;
985
        `ETH_MAC_ADDR0_ADR    :  DataOut=MAC_ADDR0Out;
986
        `ETH_MAC_ADDR1_ADR    :  DataOut=MAC_ADDR1Out;
987
        `ETH_TX_BD_NUM_ADR    :  DataOut=TX_BD_NUMOut;
988
        `ETH_HASH0_ADR        :  DataOut=HASH0Out;
989
        `ETH_HASH1_ADR        :  DataOut=HASH1Out;
990
        `ETH_TX_CTRL_ADR      :  DataOut=TXCTRLOut;
991
        `ETH_DBG_ADR          :  DataOut=dbg_dat;
992
        `ETH_IPv4_L1_ADR      :  DataOut=IPv4_L1_out;
993
        default:             DataOut=32'h0;
994
      endcase
995
    end
996
  else
997
    DataOut=32'h0;
998
end
999
 
1000
 
1001
assign r_RecSmall         = MODEROut[16];
1002
assign r_Pad              = MODEROut[15];
1003
assign r_HugEn            = MODEROut[14];
1004
assign r_CrcEn            = MODEROut[13];
1005
assign r_DlyCrcEn         = MODEROut[12];
1006
// assign r_Rst           = MODEROut[11];   This signal is not used any more
1007
assign r_FullD            = MODEROut[10];
1008
assign r_ExDfrEn          = MODEROut[9];
1009
assign r_NoBckof          = MODEROut[8];
1010
assign r_LoopBck          = MODEROut[7];
1011
assign r_IFG              = MODEROut[6];
1012
assign r_Pro              = MODEROut[5];
1013
assign r_Iam              = MODEROut[4];
1014
assign r_Bro              = MODEROut[3];
1015
assign r_NoPre            = MODEROut[2];
1016
assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.
1017
assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.
1018
 
1019
assign r_IPGT[6:0]        = IPGTOut[6:0];
1020
 
1021
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
1022
 
1023
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
1024
 
1025
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
1026
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
1027
 
1028
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
1029
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
1030
 
1031
assign r_TxFlow           = CTRLMODEROut[2];
1032
assign r_RxFlow           = CTRLMODEROut[1];
1033
assign r_PassAll          = CTRLMODEROut[0];
1034
 
1035
assign r_MiiNoPre         = MIIMODEROut[8];
1036
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
1037
 
1038
assign r_WCtrlData        = MIICOMMANDOut[2];
1039
assign r_RStat            = MIICOMMANDOut[1];
1040
assign r_ScanStat         = MIICOMMANDOut[0];
1041
 
1042
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
1043
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
1044
 
1045
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
1046
 
1047
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
1048
assign MIISTATUSOut[2]    = NValid_stat         ;
1049
assign MIISTATUSOut[1]    = Busy_stat           ;
1050
assign MIISTATUSOut[0]    = LinkFail            ;
1051
 
1052
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
1053
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
1054
assign r_DMAC[31:0]       = DMAC_ADDR0Out[31:0];
1055
assign r_DMAC[47:32]      = DMAC_ADDR1Out[15:0];
1056
 
1057
assign r_HASH1[31:0]      = HASH1Out;
1058
assign r_HASH0[31:0]      = HASH0Out;
1059
 
1060
assign r_TxBDNum[7:0]     = TX_BD_NUMOut[7:0];
1061
 
1062
assign r_TxPauseTV[15:0]  = TXCTRLOut[15:0];
1063
assign r_TxPauseRq        = TXCTRLOut[16];
1064
 
1065
 
1066
// Synchronizing TxC Interrupt
1067
always @ (posedge TxClk or posedge Reset)
1068
begin
1069
  if(Reset)
1070
    SetTxCIrq_txclk <= 1'b0;
1071
  else
1072
  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
1073
    SetTxCIrq_txclk <= 1'b1;
1074
  else
1075
  if(ResetTxCIrq_sync2)
1076
    SetTxCIrq_txclk <= 1'b0;
1077
end
1078
 
1079
 
1080
always @ (posedge Clk or posedge Reset)
1081
begin
1082
  if(Reset)
1083
    SetTxCIrq_sync1 <= 1'b0;
1084
  else
1085
    SetTxCIrq_sync1 <= SetTxCIrq_txclk;
1086
end
1087
 
1088
always @ (posedge Clk or posedge Reset)
1089
begin
1090
  if(Reset)
1091
    SetTxCIrq_sync2 <= 1'b0;
1092
  else
1093
    SetTxCIrq_sync2 <= SetTxCIrq_sync1;
1094
end
1095
 
1096
always @ (posedge Clk or posedge Reset)
1097
begin
1098
  if(Reset)
1099
    SetTxCIrq_sync3 <= 1'b0;
1100
  else
1101
    SetTxCIrq_sync3 <= SetTxCIrq_sync2;
1102
end
1103
 
1104
always @ (posedge Clk or posedge Reset)
1105
begin
1106
  if(Reset)
1107
    SetTxCIrq <= 1'b0;
1108
  else
1109
    SetTxCIrq <= SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
1110
end
1111
 
1112
always @ (posedge TxClk or posedge Reset)
1113
begin
1114
  if(Reset)
1115
    ResetTxCIrq_sync1 <= 1'b0;
1116
  else
1117
    ResetTxCIrq_sync1 <= SetTxCIrq_sync2;
1118
end
1119
 
1120
always @ (posedge TxClk or posedge Reset)
1121
begin
1122
  if(Reset)
1123
    ResetTxCIrq_sync2 <= 1'b0;
1124
  else
1125
    ResetTxCIrq_sync2 <= SetTxCIrq_sync1;
1126
end
1127
 
1128
 
1129
// Synchronizing RxC Interrupt
1130
always @ (posedge RxClk or posedge Reset)
1131
begin
1132
  if(Reset)
1133
    SetRxCIrq_rxclk <= 1'b0;
1134
  else
1135
  if(SetPauseTimer & r_RxFlow)
1136
    SetRxCIrq_rxclk <= 1'b1;
1137
  else
1138
  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
1139
    SetRxCIrq_rxclk <= 1'b0;
1140
end
1141
 
1142
 
1143
always @ (posedge Clk or posedge Reset)
1144
begin
1145
  if(Reset)
1146
    SetRxCIrq_sync1 <= 1'b0;
1147
  else
1148
    SetRxCIrq_sync1 <= SetRxCIrq_rxclk;
1149
end
1150
 
1151
always @ (posedge Clk or posedge Reset)
1152
begin
1153
  if(Reset)
1154
    SetRxCIrq_sync2 <= 1'b0;
1155
  else
1156
    SetRxCIrq_sync2 <= SetRxCIrq_sync1;
1157
end
1158
 
1159
always @ (posedge Clk or posedge Reset)
1160
begin
1161
  if(Reset)
1162
    SetRxCIrq_sync3 <= 1'b0;
1163
  else
1164
    SetRxCIrq_sync3 <= SetRxCIrq_sync2;
1165
end
1166
 
1167
always @ (posedge Clk or posedge Reset)
1168
begin
1169
  if(Reset)
1170
    SetRxCIrq <= 1'b0;
1171
  else
1172
    SetRxCIrq <= SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
1173
end
1174
 
1175
always @ (posedge RxClk or posedge Reset)
1176
begin
1177
  if(Reset)
1178
    ResetRxCIrq_sync1 <= 1'b0;
1179
  else
1180
    ResetRxCIrq_sync1 <= SetRxCIrq_sync2;
1181
end
1182
 
1183
always @ (posedge RxClk or posedge Reset)
1184
begin
1185
  if(Reset)
1186
    ResetRxCIrq_sync2 <= 1'b0;
1187
  else
1188
    ResetRxCIrq_sync2 <= ResetRxCIrq_sync1;
1189
end
1190
 
1191
always @ (posedge RxClk or posedge Reset)
1192
begin
1193
  if(Reset)
1194
    ResetRxCIrq_sync3 <= 1'b0;
1195
  else
1196
    ResetRxCIrq_sync3 <= ResetRxCIrq_sync2;
1197
end
1198
 
1199
 
1200
 
1201
// Interrupt generation
1202
always @ (posedge Clk or posedge Reset)
1203
begin
1204
  if(Reset)
1205
    irq_txb <= 1'b0;
1206
  else
1207
  if(TxB_IRQ)
1208
    irq_txb <=  1'b1;
1209
  else
1210
  if(INT_SOURCE_Wr[0] & DataIn[0])
1211
    irq_txb <=  1'b0;
1212
end
1213
 
1214
always @ (posedge Clk or posedge Reset)
1215
begin
1216
  if(Reset)
1217
    irq_txe <= 1'b0;
1218
  else
1219
  if(TxE_IRQ)
1220
    irq_txe <=  1'b1;
1221
  else
1222
  if(INT_SOURCE_Wr[0] & DataIn[1])
1223
    irq_txe <=  1'b0;
1224
end
1225
 
1226
always @ (posedge Clk or posedge Reset)
1227
begin
1228
  if(Reset)
1229
    irq_rxb <= 1'b0;
1230
  else
1231
  if(RxB_IRQ)
1232
    irq_rxb <=  1'b1;
1233
  else
1234
  if(INT_SOURCE_Wr[0] & DataIn[2])
1235
    irq_rxb <=  1'b0;
1236
end
1237
 
1238
always @ (posedge Clk or posedge Reset)
1239
begin
1240
  if(Reset)
1241
    irq_rxe <= 1'b0;
1242
  else
1243
  if(RxE_IRQ)
1244
    irq_rxe <=  1'b1;
1245
  else
1246
  if(INT_SOURCE_Wr[0] & DataIn[3])
1247
    irq_rxe <=  1'b0;
1248
end
1249
 
1250
always @ (posedge Clk or posedge Reset)
1251
begin
1252
  if(Reset)
1253
    irq_busy <= 1'b0;
1254
  else
1255
  if(Busy_IRQ)
1256
    irq_busy <=  1'b1;
1257
  else
1258
  if(INT_SOURCE_Wr[0] & DataIn[4])
1259
    irq_busy <=  1'b0;
1260
end
1261
 
1262
always @ (posedge Clk or posedge Reset)
1263
begin
1264
  if(Reset)
1265
    irq_txc <= 1'b0;
1266
  else
1267
  if(SetTxCIrq)
1268
    irq_txc <=  1'b1;
1269
  else
1270
  if(INT_SOURCE_Wr[0] & DataIn[5])
1271
    irq_txc <=  1'b0;
1272
end
1273
 
1274
always @ (posedge Clk or posedge Reset)
1275
begin
1276
  if(Reset)
1277
    irq_rxc <= 1'b0;
1278
  else
1279
  if(SetRxCIrq)
1280
    irq_rxc <=  1'b1;
1281
  else
1282
  if(INT_SOURCE_Wr[0] & DataIn[6])
1283
    irq_rxc <=  1'b0;
1284
end
1285
 
1286
// Generating interrupt signal
1287
assign int_o = irq_txb  & INT_MASKOut[0] |
1288
               irq_txe  & INT_MASKOut[1] |
1289
               irq_rxb  & INT_MASKOut[2] |
1290
               irq_rxe  & INT_MASKOut[3] |
1291
               irq_busy & INT_MASKOut[4] |
1292
               irq_txc  & INT_MASKOut[5] |
1293
               irq_rxc  & INT_MASKOut[6] ;
1294
 
1295
// For reading interrupt status
1296
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
1297
 
1298
 
1299
 
1300
endmodule

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