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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [eth_rxethmac.v] - Blame information for rev 2

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1 2 ranm11
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_rxethmac.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/project,ethmac                     ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////      - Olof Kindgren (olof@opencores.org                     ////
13
////                                                              ////
14
////  All additional information is avaliable in the Readme.txt   ////
15
////  file.                                                       ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2001, 2011 Authors                             ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// 2011-07-06 Olof Kindgren <olof@opencores.org>
45
// Add ByteCntEq0 to rxaddrcheck
46
//
47
// CVS Revision History
48
//
49
//
50
// $Log: not supported by cvs2svn $
51
// Revision 1.12  2004/04/26 15:26:23  igorm
52
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
53
//   previous update of the core.
54
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
55
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
56
//   register. (thanks to Mathias and Torbjorn)
57
// - Multicast reception was fixed. Thanks to Ulrich Gries
58
//
59
// Revision 1.11  2004/03/17 09:32:15  igorm
60
// Multicast detection fixed. Only the LSB of the first byte is checked.
61
//
62
// Revision 1.10  2002/11/22 01:57:06  mohor
63
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
64
// synchronized.
65
//
66
// Revision 1.9  2002/11/19 17:35:35  mohor
67
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
68
// that a frame was received because of the promiscous mode.
69
//
70
// Revision 1.8  2002/02/16 07:15:27  mohor
71
// Testbench fixed, code simplified, unused signals removed.
72
//
73
// Revision 1.7  2002/02/15 13:44:28  mohor
74
// RxAbort is an output. No need to have is declared as wire.
75
//
76
// Revision 1.6  2002/02/15 11:17:48  mohor
77
// File format changed.
78
//
79
// Revision 1.5  2002/02/14 20:48:43  billditt
80
// Addition  of new module eth_addrcheck.v
81
//
82
// Revision 1.4  2002/01/23 10:28:16  mohor
83
// Link in the header changed.
84
//
85
// Revision 1.3  2001/10/19 08:43:51  mohor
86
// eth_timescale.v changed to timescale.v This is done because of the
87
// simulation of the few cores in a one joined project.
88
//
89
// Revision 1.2  2001/09/11 14:17:00  mohor
90
// Few little NCSIM warnings fixed.
91
//
92
// Revision 1.1  2001/08/06 14:44:29  mohor
93
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
94
// Include files fixed to contain no path.
95
// File names and module names changed ta have a eth_ prologue in the name.
96
// File eth_timescale.v is used to define timescale
97
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
98
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
99
// and Mdo_OE. The bidirectional signal must be created on the top level. This
100
// is done due to the ASIC tools.
101
//
102
// Revision 1.1  2001/07/30 21:23:42  mohor
103
// Directory structure changed. Files checked and joind together.
104
//
105
// Revision 1.1  2001/06/27 21:26:19  mohor
106
// Initial release of the RxEthMAC module.
107
//
108
//
109
//
110
//
111
//
112
 
113
`include "timescale.v"
114
//`include "eth_l3_checksum.v"
115
 
116
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,
117
                     HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,
118
                     ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
119
                     CrcError, StateIdle, StatePreamble, StateSFD, StateData,
120
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,
121
                     PassAll, ControlFrmAddressOK
122
                    );
123
 
124
input         MRxClk;
125
input         MRxDV;
126
input   [3:0] MRxD;
127
input         Transmitting;
128
input         HugEn;
129
input         DlyCrcEn;
130
input  [15:0] MaxFL;
131
input         r_IFG;
132
input         Reset;
133
input  [47:0] MAC;     //  Station Address  
134
input         r_Bro;   //  broadcast disable
135
input         r_Pro;   //  promiscuous enable 
136
input [31:0]  r_HASH0; //  lower 4 bytes Hash Table
137
input [31:0]  r_HASH1; //  upper 4 bytes Hash Table
138
input         PassAll;
139
input         ControlFrmAddressOK;
140
 
141
output  [7:0] RxData;
142
output        RxValid;
143
output        RxStartFrm;
144
output        RxEndFrm;
145
output [15:0] ByteCnt;
146
output        ByteCntEq0;
147
output        ByteCntGreat2;
148
output        ByteCntMaxFrame;
149
output        CrcError;
150
output        StateIdle;
151
output        StatePreamble;
152
output        StateSFD;
153
output  [1:0] StateData;
154
output        RxAbort;
155
output        AddressMiss;
156
 
157
reg     [7:0] RxData;
158
reg           RxValid;
159
reg           RxStartFrm;
160
reg           RxEndFrm;
161
reg           Broadcast;
162
reg           Multicast;
163
reg     [5:0] CrcHash;
164
reg           CrcHashGood;
165
reg           DelayData;
166
reg     [7:0] LatchedByte;
167
reg     [7:0] RxData_d;
168
reg           RxValid_d;
169
reg           RxStartFrm_d;
170
reg           RxEndFrm_d;
171
 
172
wire          MRxDEqD;
173
wire          MRxDEq5;
174
wire          StateDrop;
175
wire          ByteCntEq1;
176
wire          ByteCntEq2;
177
wire          ByteCntEq3;
178
wire          ByteCntEq4;
179
wire          ByteCntEq5;
180
wire          ByteCntEq6;
181
wire          ByteCntEq7;
182
wire          ByteCntSmall7;
183
wire   [31:0] Crc;
184
wire          Enable_Crc;
185
wire          Initialize_Crc;
186
wire    [3:0] Data_Crc;
187
wire          GenerateRxValid;
188
wire          GenerateRxStartFrm;
189
wire          GenerateRxEndFrm;
190
wire          DribbleRxEndFrm;
191
wire    [3:0] DlyCrcCnt;
192
wire          IFGCounterEq24;
193
wire    [15:0] CheckSum;
194
wire           CSready;
195
assign MRxDEqD = MRxD == 4'hd;
196
assign MRxDEq5 = MRxD == 4'h5;
197
 
198
  initial begin
199
       RxData=0;
200
       RxData_d=0;
201
       RxStartFrm=0;
202
       RxEndFrm=0;
203
       RxStartFrm_d=0;
204
       RxEndFrm_d=0;
205
       end
206
// Rx State Machine module
207
eth_rxstatem rxstatem1
208
  (.MRxClk(MRxClk),
209
   .Reset(Reset),
210
   .MRxDV(MRxDV),
211
   .ByteCntEq0(ByteCntEq0),
212
   .ByteCntGreat2(ByteCntGreat2),
213
   .Transmitting(Transmitting),
214
   .MRxDEq5(MRxDEq5),
215
   .MRxDEqD(MRxDEqD),
216
   .IFGCounterEq24(IFGCounterEq24),
217
   .ByteCntMaxFrame(ByteCntMaxFrame),
218
   .StateData(StateData),
219
   .StateIdle(StateIdle),
220
   .StatePreamble(StatePreamble),
221
   .StateSFD(StateSFD),
222
   .StateDrop(StateDrop)
223
   );
224
 
225
 
226
// Rx Counters module
227
eth_rxcounters rxcounters1
228
  (.MRxClk(MRxClk),
229
   .Reset(Reset),
230
   .MRxDV(MRxDV),
231
   .StateIdle(StateIdle),
232
   .StateSFD(StateSFD),
233
   .StateData(StateData),
234
   .StateDrop(StateDrop),
235
   .StatePreamble(StatePreamble),
236
   .MRxDEqD(MRxDEqD),
237
   .DlyCrcEn(DlyCrcEn),
238
   .DlyCrcCnt(DlyCrcCnt),
239
   .Transmitting(Transmitting),
240
   .MaxFL(MaxFL),
241
   .r_IFG(r_IFG),
242
   .HugEn(HugEn),
243
   .IFGCounterEq24(IFGCounterEq24),
244
   .ByteCntEq0(ByteCntEq0),
245
   .ByteCntEq1(ByteCntEq1),
246
   .ByteCntEq2(ByteCntEq2),
247
   .ByteCntEq3(ByteCntEq3),
248
   .ByteCntEq4(ByteCntEq4),
249
   .ByteCntEq5(ByteCntEq5),
250
   .ByteCntEq6(ByteCntEq6),
251
   .ByteCntEq7(ByteCntEq7),
252
   .ByteCntGreat2(ByteCntGreat2),
253
   .ByteCntSmall7(ByteCntSmall7),
254
   .ByteCntMaxFrame(ByteCntMaxFrame),
255
   .ByteCntOut(ByteCnt)
256
   );
257
 
258
// Rx Address Check
259
 
260
eth_rxaddrcheck rxaddrcheck1
261
  (.MRxClk(MRxClk),
262
   .Reset( Reset),
263
   .RxData(RxData),
264
   .Broadcast (Broadcast),
265
   .r_Bro (r_Bro),
266
   .r_Pro(r_Pro),
267
   .ByteCntEq6(ByteCntEq6),
268
   .ByteCntEq7(ByteCntEq7),
269
   .ByteCntEq2(ByteCntEq2),
270
   .ByteCntEq3(ByteCntEq3),
271
   .ByteCntEq4(ByteCntEq4),
272
   .ByteCntEq5(ByteCntEq5),
273
   .HASH0(r_HASH0),
274
   .HASH1(r_HASH1),
275
   .ByteCntEq0(ByteCntEq0),
276
   .CrcHash(CrcHash),
277
   .CrcHashGood(CrcHashGood),
278
   .StateData(StateData),
279
   .Multicast(Multicast),
280
   .MAC(MAC),
281
   .RxAbort(RxAbort),
282
   .RxEndFrm(RxEndFrm),
283
   .AddressMiss(AddressMiss),
284
   .PassAll(PassAll),
285
   .ControlFrmAddressOK(ControlFrmAddressOK)
286
   );
287
 
288
 
289
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
290
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
291
                        DlyCrcCnt[3:0] < 4'h9;
292
 
293
assign Data_Crc[0] = MRxD[3];
294
assign Data_Crc[1] = MRxD[2];
295
assign Data_Crc[2] = MRxD[1];
296
assign Data_Crc[3] = MRxD[0];
297
 
298
 
299
// Connecting module Crc
300
eth_crc crcrx
301
  (.Clk(MRxClk),
302
   .Reset(Reset),
303
   .Data(Data_Crc),
304
   .Enable(Enable_Crc),
305
   .Initialize(Initialize_Crc),
306
   .Crc(Crc),
307
   .CrcError(CrcError)
308
   );
309
 
310
 eth_l3_checksum checkSumcalc
311
 (
312
   .MRxClk(MRxClk),
313
   .Reset(Reset),
314
   .RxData(RxData),
315
   .ByteCnt(ByteCnt),
316
   .CheckSum(CheckSum),
317
   .CSready(CSready)
318
 );
319
 
320
// Latching CRC for use in the hash table
321
always @ (posedge MRxClk)
322
begin
323
  CrcHashGood <=  StateData[0] & ByteCntEq6;
324
end
325
 
326
always @ (posedge MRxClk)
327
begin
328
  if(Reset | StateIdle)
329
    CrcHash[5:0] <=  6'h0;
330
  else
331
  if(StateData[0] & ByteCntEq6)
332
    CrcHash[5:0] <=  Crc[31:26];
333
end
334
 
335
// Output byte stream
336
always @ (posedge MRxClk or posedge Reset)
337
begin
338
  if(Reset)
339
    begin
340
      RxData_d[7:0]      <=  8'h0;
341
      DelayData          <=  1'b0;
342
      LatchedByte[7:0]   <=  8'h0;
343
      RxData[7:0]        <=  8'h0;
344
    end
345
  else
346
    begin
347
      // Latched byte
348
      LatchedByte[7:0]   <=  {MRxD[3:0], LatchedByte[7:4]};
349
      DelayData          <=  StateData[0];
350
 
351
      if(GenerateRxValid)
352
        // Data goes through only in data state 
353
        RxData_d[7:0] <=  LatchedByte[7:0] & {8{|StateData}};
354
      else
355
      if(~DelayData)
356
        // Delaying data to be valid for two cycles.
357
        // Zero when not active.
358
        RxData_d[7:0] <=  8'h0;
359
 
360
      RxData[7:0] <=  RxData_d[7:0];          // Output data byte
361
    end
362
end
363
 
364
 
365
 
366
always @ (posedge MRxClk or posedge Reset)
367
begin
368
  if(Reset)
369
    Broadcast <=  1'b0;
370
  else
371
    begin
372
      if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
373
        Broadcast <=  1'b0;
374
      else
375
      if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
376
        Broadcast <=  1'b1;
377
      else
378
      if(RxAbort | RxEndFrm)
379
        Broadcast <=  1'b0;
380
    end
381
end
382
 
383
 
384
always @ (posedge MRxClk or posedge Reset)
385
begin
386
  if(Reset)
387
    Multicast <=  1'b0;
388
  else
389
    begin
390
      if(StateData[0] & ByteCntEq1 & LatchedByte[0])
391
        Multicast <=  1'b1;
392
      else if(RxAbort | RxEndFrm)
393
      Multicast <=  1'b0;
394
    end
395
end
396
 
397
 
398
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
399
 
400
always @ (posedge MRxClk or posedge Reset)
401
begin
402
  if(Reset)
403
    begin
404
      RxValid_d <=  1'b0;
405
      RxValid   <=  1'b0;
406
    end
407
  else
408
    begin
409
      RxValid_d <=  GenerateRxValid;
410
      RxValid   <=  RxValid_d;
411
    end
412
end
413
 
414
 
415
assign GenerateRxStartFrm = StateData[0] &
416
                            ((ByteCntEq1 & ~DlyCrcEn) |
417
                            ((DlyCrcCnt == 4'h3) & DlyCrcEn));
418
 
419
always @ (posedge MRxClk or posedge Reset)
420
begin
421
  if(Reset)
422
    begin
423
      RxStartFrm_d <=  1'b0;
424
      RxStartFrm   <=  1'b0;
425
    end
426
  else
427
    begin
428
      RxStartFrm_d <=  GenerateRxStartFrm;
429
      RxStartFrm   <=  RxStartFrm_d;
430
    end
431
end
432
 
433
 
434
assign GenerateRxEndFrm = StateData[0] &
435
                          (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
436
assign DribbleRxEndFrm  = StateData[1] &  ~MRxDV & ByteCntGreat2;
437
 
438
 
439
always @ (posedge MRxClk or posedge Reset)
440
begin
441
  if(Reset)
442
    begin
443
      RxEndFrm_d <=  1'b0;
444
      RxEndFrm   <=  1'b0;
445
    end
446
  else
447
    begin
448
      RxEndFrm_d <=  GenerateRxEndFrm;
449
      RxEndFrm   <=  RxEndFrm_d | DribbleRxEndFrm;
450
    end
451
end
452
 
453
 
454
endmodule
455
 
456
 
457
 module eth_l3_checksum
458
   (
459
     MRxClk ,Reset, RxData , ByteCnt, CheckSum ,CSready
460
   );
461
 
462
input    MRxClk;
463
input    Reset;
464
input [7:0] RxData;
465
input [15:0] ByteCnt;
466
output [15:0] CheckSum;
467
output        CSready;
468
 
469
reg   [15:0]   CheckSum;
470
reg   [31:0]   Sum;
471
reg            CSready;
472
reg   [1:0]    StartCalc;
473
reg            Divided_2_clk ;
474
reg            Divided_4_clk ;
475
reg [7:0] prev_latched_Rx;
476
reg [7:0] prev_latched_Rx1;
477
 
478
 initial Divided_2_clk=0;
479
 initial Divided_4_clk=0;
480
 
481
always @ (posedge MRxClk)
482
    begin
483
       Divided_2_clk <=  MRxClk^Divided_2_clk;
484
       if (ByteCnt[15:0] >= 16'h17 & ByteCnt[15:0] < (16'h17+16'd20))
485
           begin
486
           prev_latched_Rx[7:0] <= RxData[7:0];
487
           prev_latched_Rx1[7:0] <= prev_latched_Rx[7:0];
488
           end
489
 
490
    end
491
 
492
always @ (posedge Divided_2_clk)
493
      Divided_4_clk <= Divided_4_clk ^ Divided_2_clk;
494
 
495
 
496
always @ (posedge  Divided_2_clk or posedge Reset )
497
begin
498
    if (Reset)
499
        begin
500
        CheckSum[15:0] <= 16'd0;
501
        CSready <= 1'd0;
502
        end
503
    else
504
       if (ByteCnt[15:0]==16'h15)
505
           StartCalc[0] <= (RxData[7:0] == 8'h8);
506
       else
507
       if (ByteCnt[15:0]==16'h16)
508
           begin
509
           StartCalc[0] <= (RxData[7:0] == 8'h0) & StartCalc[0] ;
510
           CheckSum[15:0] <= 16'h0;
511
           Sum[31:0] <= 32'h0;
512
           CSready <= 1'b0;
513
           end
514
       else
515
       if (ByteCnt[15:0] >= 16'h17 & ByteCnt[15:0] < (16'h17+16'd20))
516
           begin
517
           StartCalc[1]<= (ByteCnt[15:0] > 16'h17) & StartCalc[0] ;
518
           end
519
       else
520
         StartCalc[1:0] <= 2'h0;
521
 
522
   if (ByteCnt[15:0]-16'h17== 16'd20)
523
       begin
524
         CSready <= 1'b1;
525
         CheckSum[15:0] <= ~(Sum[15:0]+Sum[31:16]);
526
       end
527
 
528
   end
529
 
530
 always @ (negedge Divided_4_clk)
531
 begin
532
      if (&StartCalc)
533
        Sum[31:0]<= Sum[31:0] + {prev_latched_Rx1[7:0] , RxData[7:0]};
534
 
535
  end
536
 
537
 
538
 
539
endmodule
540
 
541
 

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