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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [eth_transmitcontrol.v] - Blame information for rev 2

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1 2 ranm11
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_transmitcontrol.v                                       ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/project,ethmac                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44
// Revision 1.5  2002/11/19 17:37:32  mohor
45
// When control frame (PAUSE) was sent, status was written in the
46
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
47
// Only TXC interrupt is set.
48
//
49
// Revision 1.4  2002/01/23 10:28:16  mohor
50
// Link in the header changed.
51
//
52
// Revision 1.3  2001/10/19 08:43:51  mohor
53
// eth_timescale.v changed to timescale.v This is done because of the
54
// simulation of the few cores in a one joined project.
55
//
56
// Revision 1.2  2001/09/11 14:17:00  mohor
57
// Few little NCSIM warnings fixed.
58
//
59
// Revision 1.1  2001/08/06 14:44:29  mohor
60
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
61
// Include files fixed to contain no path.
62
// File names and module names changed ta have a eth_ prologue in the name.
63
// File eth_timescale.v is used to define timescale
64
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
65
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
66
// and Mdo_OE. The bidirectional signal must be created on the top level. This
67
// is done due to the ASIC tools.
68
//
69
// Revision 1.1  2001/07/30 21:23:42  mohor
70
// Directory structure changed. Files checked and joind together.
71
//
72
// Revision 1.1  2001/07/03 12:51:54  mohor
73
// Initial release of the MAC Control module.
74
//
75
//
76
//
77
//
78
//
79
//
80
 
81
 
82
`include "timescale.v"
83
 
84
 
85
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
86
                            TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
87
                            TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
88
                            ControlData, WillSendControlFrame, BlockTxDone
89
                           );
90
 
91
 
92
input         MTxClk;
93
input         TxReset;
94
input         TxUsedDataIn;
95
input         TxUsedDataOut;
96
input         TxDoneIn;
97
input         TxAbortIn;
98
input         TxStartFrmIn;
99
input         TPauseRq;
100
input         TxUsedDataOutDetected;
101
input         TxFlow;
102
input         DlyCrcEn;
103
input  [15:0] TxPauseTV;
104
input  [47:0] MAC;
105
 
106
output        TxCtrlStartFrm;
107
output        TxCtrlEndFrm;
108
output        SendingCtrlFrm;
109
output        CtrlMux;
110
output [7:0]  ControlData;
111
output        WillSendControlFrame;
112
output        BlockTxDone;
113
 
114
reg           SendingCtrlFrm;
115
reg           CtrlMux;
116
reg           WillSendControlFrame;
117
reg    [3:0]  DlyCrcCnt;
118
reg    [5:0]  ByteCnt;
119
reg           ControlEnd_q;
120
reg    [7:0]  MuxedCtrlData;
121
reg           TxCtrlStartFrm;
122
reg           TxCtrlStartFrm_q;
123
reg           TxCtrlEndFrm;
124
reg    [7:0]  ControlData;
125
reg           TxUsedDataIn_q;
126
reg           BlockTxDone;
127
 
128
wire          IncrementDlyCrcCnt;
129
wire          ResetByteCnt;
130
wire          IncrementByteCnt;
131
wire          ControlEnd;
132
wire          IncrementByteCntBy2;
133
wire          EnableCnt;
134
 
135
 
136
// A command for Sending the control frame is active (latched)
137
always @ (posedge MTxClk or posedge TxReset)
138
begin
139
  if(TxReset)
140
    WillSendControlFrame <=  1'b0;
141
  else
142
  if(TxCtrlEndFrm & CtrlMux)
143
    WillSendControlFrame <=  1'b0;
144
  else
145
  if(TPauseRq & TxFlow)
146
    WillSendControlFrame <=  1'b1;
147
end
148
 
149
 
150
// Generation of the transmit control packet start frame
151
always @ (posedge MTxClk or posedge TxReset)
152
begin
153
  if(TxReset)
154
    TxCtrlStartFrm <=  1'b0;
155
  else
156
  if(TxUsedDataIn_q & CtrlMux)
157
    TxCtrlStartFrm <=  1'b0;
158
  else
159
  if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
160
    TxCtrlStartFrm <=  1'b1;
161
end
162
 
163
 
164
 
165
// Generation of the transmit control packet end frame
166
always @ (posedge MTxClk or posedge TxReset)
167
begin
168
  if(TxReset)
169
    TxCtrlEndFrm <=  1'b0;
170
  else
171
  if(ControlEnd | ControlEnd_q)
172
    TxCtrlEndFrm <=  1'b1;
173
  else
174
    TxCtrlEndFrm <=  1'b0;
175
end
176
 
177
 
178
// Generation of the multiplexer signal (controls muxes for switching between
179
// normal and control packets)
180
always @ (posedge MTxClk or posedge TxReset)
181
begin
182
  if(TxReset)
183
    CtrlMux <=  1'b0;
184
  else
185
  if(WillSendControlFrame & ~TxUsedDataOut)
186
    CtrlMux <=  1'b1;
187
  else
188
  if(TxDoneIn)
189
    CtrlMux <=  1'b0;
190
end
191
 
192
 
193
 
194
// Generation of the Sending Control Frame signal (enables padding and CRC)
195
always @ (posedge MTxClk or posedge TxReset)
196
begin
197
  if(TxReset)
198
    SendingCtrlFrm <=  1'b0;
199
  else
200
  if(WillSendControlFrame & TxCtrlStartFrm)
201
    SendingCtrlFrm <=  1'b1;
202
  else
203
  if(TxDoneIn)
204
    SendingCtrlFrm <=  1'b0;
205
end
206
 
207
 
208
always @ (posedge MTxClk or posedge TxReset)
209
begin
210
  if(TxReset)
211
    TxUsedDataIn_q <=  1'b0;
212
  else
213
    TxUsedDataIn_q <=  TxUsedDataIn;
214
end
215
 
216
 
217
 
218
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
219
// While sending the control frame
220
always @ (posedge MTxClk or posedge TxReset)
221
begin
222
  if(TxReset)
223
    BlockTxDone <=  1'b0;
224
  else
225
  if(TxCtrlStartFrm)
226
    BlockTxDone <=  1'b1;
227
  else
228
  if(TxStartFrmIn)
229
    BlockTxDone <=  1'b0;
230
end
231
 
232
 
233
always @ (posedge MTxClk)
234
begin
235
  ControlEnd_q     <=  ControlEnd;
236
  TxCtrlStartFrm_q <=  TxCtrlStartFrm;
237
end
238
 
239
 
240
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn &  ~DlyCrcCnt[2];
241
 
242
 
243
// Delayed CRC counter
244
always @ (posedge MTxClk or posedge TxReset)
245
begin
246
  if(TxReset)
247
    DlyCrcCnt <=  4'h0;
248
  else
249
  if(ResetByteCnt)
250
    DlyCrcCnt <=  4'h0;
251
  else
252
  if(IncrementDlyCrcCnt)
253
    DlyCrcCnt <=  DlyCrcCnt + 4'd1;
254
end
255
 
256
 
257
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
258
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
259
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn;     // When TxUsedDataIn and CtrlMux are set at the same time
260
 
261
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
262
// Byte counter
263
always @ (posedge MTxClk or posedge TxReset)
264
begin
265
  if(TxReset)
266
    ByteCnt <=  6'h0;
267
  else
268
  if(ResetByteCnt)
269
    ByteCnt <=  6'h0;
270
  else
271
  if(IncrementByteCntBy2 & EnableCnt)
272
    ByteCnt <=  (ByteCnt[5:0] ) + 6'd2;
273
  else
274
  if(IncrementByteCnt & EnableCnt)
275
    ByteCnt <=  (ByteCnt[5:0] ) + 6'd1;
276
end
277
 
278
 
279
assign ControlEnd = ByteCnt[5:0] == 6'h22;
280
 
281
 
282
// Control data generation (goes to the TxEthMAC module)
283
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
284
begin
285
  case(ByteCnt)
286
    6'h0:    if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
287
               MuxedCtrlData[7:0] = 8'h01;                   // Reserved Multicast Address
288
             else
289
                                                         MuxedCtrlData[7:0] = 8'h0;
290
    6'h2:      MuxedCtrlData[7:0] = 8'h80;
291
    6'h4:      MuxedCtrlData[7:0] = 8'hC2;
292
    6'h6:      MuxedCtrlData[7:0] = 8'h00;
293
    6'h8:      MuxedCtrlData[7:0] = 8'h00;
294
    6'hA:      MuxedCtrlData[7:0] = 8'h01;
295
    6'hC:      MuxedCtrlData[7:0] = MAC[47:40];
296
    6'hE:      MuxedCtrlData[7:0] = MAC[39:32];
297
    6'h10:     MuxedCtrlData[7:0] = MAC[31:24];
298
    6'h12:     MuxedCtrlData[7:0] = MAC[23:16];
299
    6'h14:     MuxedCtrlData[7:0] = MAC[15:8];
300
    6'h16:     MuxedCtrlData[7:0] = MAC[7:0];
301
    6'h18:     MuxedCtrlData[7:0] = 8'h88;                   // Type/Length
302
    6'h1A:     MuxedCtrlData[7:0] = 8'h08;
303
    6'h1C:     MuxedCtrlData[7:0] = 8'h00;                   // Opcode
304
    6'h1E:     MuxedCtrlData[7:0] = 8'h01;
305
    6'h20:     MuxedCtrlData[7:0] = TxPauseTV[15:8];         // Pause timer value
306
    6'h22:     MuxedCtrlData[7:0] = TxPauseTV[7:0];
307
    default:   MuxedCtrlData[7:0] = 8'h0;
308
  endcase
309
end
310
// Latched Control data
311
always @ (posedge MTxClk or posedge TxReset)
312
begin
313
  if(TxReset)
314
    ControlData[7:0] <=  8'h0;
315
  else
316
  if(~ByteCnt[0])
317
    ControlData[7:0] <=  MuxedCtrlData[7:0];
318
end
319
 
320
 
321
 
322
endmodule
323
 
324
 
325
module eth_L2_Uc_Wrapper  (MTxClk, TxReset, TxDataIn, MAC, DMAC, TxData_wrapped_out, TxAbortIn,
326
                            TxStartFrmIn, TxEndFrmOut_uc  ,TxEndFrmIn
327
                           );
328
 
329
 
330
input          MTxClk;
331
input          TxReset;
332
input   [7:0]  TxDataIn;
333
input          TxStartFrmIn;
334
input  [47:0]  MAC ,DMAC;
335
input          TxAbortIn;
336
input          TxEndFrmIn;
337
output         TxEndFrmOut_uc;
338
output  [7:0]  TxData_wrapped_out;
339
 
340
wire     [7:0]  TxData_wrapped_out_wire;
341
reg     [7:0]  TxData_wrapped_out;
342
reg     [7:0]  ByteCnt;
343
//reg     [47:0] DMAC;
344
//reg            TxEndFrmOut_uc;
345
reg            Divided_2_clk ;
346
reg            write_fifo;
347
reg            read_fifo;
348
reg            clear;
349
reg      [8:0] PreNib15State;
350
wire            TxBufferFull;
351
wire            TxBufferAlmostFull;
352
wire            TxBufferAlmostEmpty;
353
wire            TxBufferEmpty;
354
wire    [4:0]  txfifo_cnt;
355
reg            StateCount , StateLeftinQ;
356
initial begin
357
 //DMAC[47:0] = 48'hFFCCBB440011;
358
 StateCount = 1'b0;
359
 read_fifo = 1'b0;
360
 StateLeftinQ = 1'b0;
361
 PreNib15State = 1'b0;
362
 Divided_2_clk=0;
363
 end
364
 assign  TxEndFrmOut_uc = TxBufferEmpty & StateLeftinQ;
365
 
366
   always @(posedge TxStartFrmIn)
367
    begin
368
          Divided_2_clk=1;
369
        end
370
   always@ (posedge MTxClk)
371
   begin
372
       Divided_2_clk <=  MTxClk^Divided_2_clk;
373
       //inputs: startFrm,EndFrm,bufferempty
374
  // TxData_wrapped_out <=  TxDataIn;
375
  // 0. ZeroState - state zero - before startfrm after staeleft in Q  -  StateCount=0    StateLeftinQ=0    PreNib15State=0
376
  // 1. PreNib15State - TxStartFrm started and not finished - set the sfd in this case  StateCount=0    StateLeftinQ=0      PreNib15State=1
377
  // 2. StateCount - between start - end frame - statecount    StateCount=1    StateLeftinQ=0       PreNib15State=0
378
  // 3. StateLeftinQ - left data in queue - between end frame and que empty  StateCount=0    StateLeftinQ=1   PreNib15State=0
379
   case ({TxStartFrmIn,TxEndFrmIn})
380
       2'b10: if (StateCount==0) StateCount<=1;
381
       2'b01: if (StateCount==1) StateCount<=0;
382
   endcase
383
 
384
   case ({TxEndFrmIn,TxBufferEmpty})
385
       2'b10:  if (StateLeftinQ==0) StateLeftinQ<=1;
386
       2'b01:  if (StateLeftinQ==1) StateLeftinQ<=0;
387
   endcase
388
 
389
  //  TxEndFrmOut_uc <= TxBufferEmpty & StateLeftinQ;
390
 
391
      end // always
392
 
393
      always@ (negedge Divided_2_clk)
394
            begin
395
            if (StateCount | StateLeftinQ | TxStartFrmIn)
396
             begin
397
               case (ByteCnt)
398
                 //  7'h:  begin    TxData_wrapped_out[7:0] <= TxDataIn; read_fifo<=0;     end
399
                 //  7'h0:  begin    TxData_wrapped_out[7:0] <= TxDataIn; read_fifo<=0;     end
400
                 //  7'h:  begin    TxData_wrapped_out[7:0] <= TxDataIn;   read_fifo<=0;     end
401
                   7'h0:  begin    TxData_wrapped_out[7:0] <= DMAC[47:40]; read_fifo<=0;     end
402
                   7'h1:  begin    TxData_wrapped_out[7:0] <= DMAC[39:32]; read_fifo<=0;     end
403
                   7'h2:  begin    TxData_wrapped_out[7:0] <= DMAC[31:24]; read_fifo<=0;     end
404
                   7'h3:  begin    TxData_wrapped_out[7:0] <= DMAC[23:16]; read_fifo<=0;     end
405
                   7'h4:  begin    TxData_wrapped_out[7:0] <= DMAC[15:8];  read_fifo<=0;     end
406
                   7'h5:  begin    TxData_wrapped_out[7:0] <= DMAC[7:0];   read_fifo<=0;     end
407
                   7'h6:  begin    TxData_wrapped_out[7:0] <= MAC[47:40];  read_fifo<=0;     end
408
                   7'h7:  begin    TxData_wrapped_out[7:0] <= MAC[39:32];  read_fifo<=0;     end
409
                   7'h8:  begin    TxData_wrapped_out[7:0] <= MAC[31:24];  read_fifo<=0;     end
410
                   7'h9:  begin    TxData_wrapped_out[7:0] <= MAC[23:16];  read_fifo<=0;     end
411
                   7'ha:  begin    TxData_wrapped_out[7:0] <= MAC[15:8];   read_fifo<=0;     end
412
                   7'hb:  begin    TxData_wrapped_out[7:0] <= MAC[7:0];    read_fifo<=0;     end
413
                   default: begin
414
                          read_fifo<=1;               //deque      read_fifo & not empty
415
                          TxData_wrapped_out<=TxData_wrapped_out_wire;
416
                           end
417
                endcase
418
             end
419
             else begin
420
                          ByteCnt <=0;
421
                          read_fifo<=0;               //deque      read_fifo & not empty
422
                          TxData_wrapped_out<=8'h0;
423
                          PreNib15State <= 9'h0;
424
                   end
425
 
426
             if (StateCount)
427
                 begin
428
                  PreNib15State <=  PreNib15State + 1;
429
                 end
430
             if (StateCount & PreNib15State >= 8)
431
                   begin
432
                   ByteCnt = ByteCnt+1;
433
                   write_fifo <= 1;
434
                   end
435
                else   begin
436
                   write_fifo<=0;
437
             end
438
 
439
         end //divided clk always
440
 
441
      eth_fifo #(
442
           .DATA_WIDTH(8),
443
           .DEPTH(32),
444
           .CNT_WIDTH(5))
445
 L2_fifo (
446
         .clk            (Divided_2_clk),
447
         .reset          (TxReset),
448
         // Inputs
449
         .data_in        (TxDataIn),
450
         .write          (write_fifo),
451
         .read           (read_fifo),
452
         .clear          (TxFifoClear),
453
         // Outputs
454
         .data_out       (TxData_wrapped_out_wire),
455
         .full           (TxBufferFull),
456
         .almost_full    (TxBufferAlmostFull),
457
         .almost_empty   (TxBufferAlmostEmpty),
458
         .empty          (TxBufferEmpty),
459
         .cnt            (txfifo_cnt)
460
        );
461
 
462
 
463
 
464
 
465
endmodule
466
 
467
 

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