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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 2

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2
`include "ethmac_defines.v"
3
`include "timescale.v"
4
 
5
 
6
module eth_wishbone
7
  (
8
 
9
   // WISHBONE common
10
   WB_CLK_I, WB_DAT_I, WB_DAT_O,
11
 
12
   // WISHBONE slave
13
   WB_ADR_I, WB_WE_I, WB_ACK_O,
14
   BDCs,
15
 
16
   Reset,
17
 
18
   // WISHBONE master
19
   m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
20
   m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
21
   m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
22
 
23
`ifdef ETH_WISHBONE_B3
24
   m_wb_cti_o, m_wb_bte_o,
25
`endif
26
 
27
   //TX
28
   MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
29
   TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
30
   PerPacketPad,
31
 
32
   //RX
33
   MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
34
   RxStatusWriteLatched_sync2,
35
 
36
   // Register
37
   r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
38
 
39
   // Interrupts
40
   TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
41
 
42
   // Rx Status
43
   InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
44
   ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
45
   AddressMiss,
46
   ReceivedPauseFrm,
47
 
48
   // Tx Status
49
   RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched,
50
   CarrierSenseLost
51
 
52
   // Bist
53
`ifdef ETH_BIST
54
   ,
55
   // debug chain signals
56
   mbist_si_i,       // bist scan serial in
57
   mbist_so_o,       // bist scan serial out
58
   mbist_ctrl_i        // bist chain shift control
59
`endif
60
 
61
`ifdef WISHBONE_DEBUG
62
   ,
63
   dbg_dat0
64
`endif
65
 
66
 
67
   );
68
 
69
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
70
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
71
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
72
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
73
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
74
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
75
 
76
// WISHBONE common
77
input           WB_CLK_I;       // WISHBONE clock
78
input  [31:0]   WB_DAT_I;       // WISHBONE data input
79
output [31:0]   WB_DAT_O;       // WISHBONE data output
80
 
81
// WISHBONE slave
82
input   [9:2]   WB_ADR_I;       // WISHBONE address input
83
input           WB_WE_I;        // WISHBONE write enable input
84
input   [3:0]   BDCs;           // Buffer descriptors are selected
85
output          WB_ACK_O;       // WISHBONE acknowledge output
86
 
87
// WISHBONE master
88
output  [29:0]  m_wb_adr_o;     // 
89
output   [3:0]  m_wb_sel_o;     // 
90
output          m_wb_we_o;      // 
91
output  [31:0]  m_wb_dat_o;     // 
92
output          m_wb_cyc_o;     // 
93
output          m_wb_stb_o;     // 
94
input   [31:0]  m_wb_dat_i;     // 
95
input           m_wb_ack_i;     // 
96
input           m_wb_err_i;     // 
97
 
98
`ifdef ETH_WISHBONE_B3
99
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
100
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
101
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
102
`endif
103
 
104
input           Reset;       // Reset signal
105
 
106
// Rx Status signals
107
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
108
input           LatchedCrcError;  // CRC error
109
input           RxLateCollision;  // Late collision occured while receiving frame
110
input           ShortFrame;       // Frame shorter then the minimum size
111
                                  // (r_MinFL) was received while small
112
                                  // packets are enabled (r_RecSmall)
113
input           DribbleNibble;    // Extra nibble received
114
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
115
input    [15:0] RxLength;         // Length of the incoming frame
116
input           LoadRxStatus;     // Rx status was loaded
117
input           ReceivedPacketGood;  // Received packet's length and CRC are
118
                                     // good
119
input           AddressMiss;      // When a packet is received AddressMiss
120
                                  // status is written to the Rx BD
121
input           r_RxFlow;
122
input           r_PassAll;
123
input           ReceivedPauseFrm;
124
 
125
// Tx Status signals
126
input     [3:0] RetryCntLatched;  // Latched Retry Counter
127
input           RetryLimit;       // Retry limit reached (Retry Max value +1
128
                                  // attempts were made)
129
input           LateCollLatched;  // Late collision occured
130
input           DeferLatched;     // Defer indication (Frame was defered
131
                                  // before sucessfully sent)
132
output          RstDeferLatched;
133
input           CarrierSenseLost; // Carrier Sense was lost during the
134
                                  // frame transmission
135
 
136
// Tx
137
input           MTxClk;         // Transmit clock (from PHY)
138
input           TxUsedData;     // Transmit packet used data
139
input           TxRetry;        // Transmit packet retry
140
input           TxAbort;        // Transmit packet abort
141
input           TxDone;         // Transmission ended
142
output          TxStartFrm;     // Transmit packet start frame
143
output          TxEndFrm;       // Transmit packet end frame
144
output  [7:0]   TxData;         // Transmit packet data byte
145
output          TxUnderRun;     // Transmit packet under-run
146
output          PerPacketCrcEn; // Per packet crc enable
147
output          PerPacketPad;   // Per packet pading
148
 
149
// Rx
150
input           MRxClk;         // Receive clock (from PHY)
151
input   [7:0]   RxData;         // Received data byte (from PHY)
152
input           RxValid;        // 
153
input           RxStartFrm;     // 
154
input           RxEndFrm;       // 
155
input           RxAbort;        // This signal is set when address doesn't
156
                                // match.
157
output          RxStatusWriteLatched_sync2;
158
 
159
//Register
160
input           r_TxEn;         // Transmit enable
161
input           r_RxEn;         // Receive enable
162
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
163
 
164
// Interrupts
165
output TxB_IRQ;
166
output TxE_IRQ;
167
output RxB_IRQ;
168
output RxE_IRQ;
169
output Busy_IRQ;
170
 
171
 
172
// Bist
173
`ifdef ETH_BIST
174
input   mbist_si_i;       // bist scan serial in
175
output  mbist_so_o;       // bist scan serial out
176
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
177
`endif
178
 
179
`ifdef WISHBONE_DEBUG
180
   output [31:0]                        dbg_dat0;
181
`endif
182
 
183
 
184
reg TxB_IRQ;
185
reg TxE_IRQ;
186
reg RxB_IRQ;
187
reg RxE_IRQ;
188
 
189
reg             TxStartFrm;
190
reg             TxEndFrm;
191
reg     [7:0]   TxData;
192
 
193
reg             TxUnderRun;
194
reg             TxUnderRun_wb;
195
 
196
reg             TxBDRead;
197
wire            TxStatusWrite;
198
 
199
reg     [1:0]   TxValidBytesLatched;
200
 
201
reg    [15:0]   TxLength;
202
reg    [15:0]   LatchedTxLength;
203
reg   [14:11]   TxStatus;
204
 
205
reg   [14:13]   RxStatus;
206
 
207
reg             TxStartFrm_wb;
208
reg             TxRetry_wb;
209
reg             TxAbort_wb;
210
reg             TxDone_wb;
211
 
212
reg             TxDone_wb_q;
213
reg             TxAbort_wb_q;
214
reg             TxRetry_wb_q;
215
reg             TxRetryPacket;
216
reg             TxRetryPacket_NotCleared;
217
reg             TxDonePacket;
218
reg             TxDonePacket_NotCleared;
219
reg             TxAbortPacket;
220
reg             TxAbortPacket_NotCleared;
221
reg             RxBDReady;
222
reg             RxReady;
223
reg             TxBDReady;
224
 
225
reg             RxBDRead;
226
 
227
reg    [31:0]   TxDataLatched;
228
reg     [1:0]   TxByteCnt;
229
reg             LastWord;
230
reg             ReadTxDataFromFifo_tck;
231
 
232
reg             BlockingTxStatusWrite;
233
reg             BlockingTxBDRead;
234
 
235
reg             Flop;
236
 
237
reg     [7:1]   TxBDAddress;
238
reg     [7:1]   RxBDAddress;
239
 
240
reg             TxRetrySync1;
241
reg             TxAbortSync1;
242
reg             TxDoneSync1;
243
 
244
reg             TxAbort_q;
245
reg             TxRetry_q;
246
reg             TxUsedData_q;
247
 
248
reg    [31:0]   RxDataLatched2;
249
 
250
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
251
 
252
reg     [1:0]   RxValidBytes;
253
reg     [1:0]   RxByteCnt;
254
reg             LastByteIn;
255
reg             ShiftWillEnd;
256
 
257
reg             WriteRxDataToFifo;
258
reg    [15:0]   LatchedRxLength;
259
reg             RxAbortLatched;
260
 
261
reg             ShiftEnded;
262
reg             RxOverrun;
263
 
264
reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side
265
reg             BDRead;                     // BD Read access from WISHBONE side
266
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
267
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
268
 
269
reg             TxEndFrm_wb;
270
 
271
wire            TxRetryPulse;
272
wire            TxDonePulse;
273
wire            TxAbortPulse;
274
 
275
wire            StartRxBDRead;
276
 
277
wire            StartTxBDRead;
278
 
279
wire            TxIRQEn;
280
wire            WrapTxStatusBit;
281
 
282
wire            RxIRQEn;
283
wire            WrapRxStatusBit;
284
 
285
wire    [1:0]   TxValidBytes;
286
 
287
wire    [7:1]   TempTxBDAddress;
288
wire    [7:1]   TempRxBDAddress;
289
 
290
wire            RxStatusWrite;
291
wire            RxBufferFull;
292
wire            RxBufferAlmostEmpty;
293
wire            RxBufferEmpty;
294
 
295
reg             WB_ACK_O;
296
 
297
wire    [8:0]   RxStatusIn;
298
reg     [8:0]   RxStatusInLatched;
299
 
300
reg WbEn, WbEn_q;
301
reg RxEn, RxEn_q;
302
reg TxEn, TxEn_q;
303
reg r_TxEn_q;
304
reg r_RxEn_q;
305
 
306
wire ram_ce;
307
wire [3:0]  ram_we;
308
wire ram_oe;
309
reg [7:0]   ram_addr;
310
reg [31:0]  ram_di;
311
wire [31:0] ram_do;
312
 
313
wire StartTxPointerRead;
314
reg TxPointerRead;
315
reg TxEn_needed;
316
reg RxEn_needed;
317
 
318
wire StartRxPointerRead;
319
reg RxPointerRead;
320
 
321
// RX shift ending signals
322
reg ShiftEnded_rck;
323
reg ShiftEndedSync1;
324
reg ShiftEndedSync2;
325
reg ShiftEndedSync3;
326
reg ShiftEndedSync_c1;
327
reg ShiftEndedSync_c2;
328
 
329
wire StartShiftWillEnd;
330
 
331
reg StartOccured;
332
reg TxStartFrm_sync1;
333
reg TxStartFrm_sync2;
334
reg TxStartFrm_syncb1;
335
reg TxStartFrm_syncb2;
336
 
337
wire TxFifoClear;
338
wire TxBufferAlmostFull;
339
wire TxBufferFull;
340
wire TxBufferEmpty;
341
wire TxBufferAlmostEmpty;
342
wire SetReadTxDataFromMemory;
343
reg BlockReadTxDataFromMemory;
344
 
345
reg tx_burst_en;
346
reg rx_burst_en;
347
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
348
 
349
wire ReadTxDataFromMemory_2;
350
wire tx_burst;
351
 
352
wire [31:0] TxData_wb;
353
wire ReadTxDataFromFifo_wb;
354
 
355
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
356
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
357
 
358
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
359
 
360
wire rx_burst;
361
wire enough_data_in_rxfifo_for_burst;
362
wire enough_data_in_rxfifo_for_burst_plus1;
363
 
364
reg ReadTxDataFromMemory;
365
wire WriteRxDataToMemory;
366
 
367
reg MasterWbTX;
368
reg MasterWbRX;
369
 
370
reg [29:0] m_wb_adr_o;
371
reg        m_wb_cyc_o;
372
reg  [3:0] m_wb_sel_o;
373
reg        m_wb_we_o;
374
 
375
wire TxLengthEq0;
376
wire TxLengthLt4;
377
 
378
reg BlockingIncrementTxPointer;
379
reg [31:2] TxPointerMSB;
380
reg [1:0]  TxPointerLSB;
381
reg [1:0]  TxPointerLSB_rst;
382
reg [31:2] RxPointerMSB;
383
reg [1:0]  RxPointerLSB_rst;
384
 
385
wire RxBurstAcc;
386
wire RxWordAcc;
387
wire RxHalfAcc;
388
wire RxByteAcc;
389
 
390
wire ResetTxBDReady;
391
reg BlockingTxStatusWrite_sync1;
392
reg BlockingTxStatusWrite_sync2;
393
reg BlockingTxStatusWrite_sync3;
394
 
395
reg cyc_cleared;
396
reg IncrTxPointer;
397
 
398
reg  [3:0] RxByteSel;
399
wire MasterAccessFinished;
400
 
401
reg LatchValidBytes;
402
reg LatchValidBytes_q;
403
 
404
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
405
reg ReadTxDataFromFifo_sync1;
406
reg ReadTxDataFromFifo_sync2;
407
reg ReadTxDataFromFifo_sync3;
408
reg ReadTxDataFromFifo_syncb1;
409
reg ReadTxDataFromFifo_syncb2;
410
reg ReadTxDataFromFifo_syncb3;
411
 
412
reg RxAbortSync1;
413
reg RxAbortSync2;
414
reg RxAbortSync3;
415
reg RxAbortSync4;
416
reg RxAbortSyncb1;
417
reg RxAbortSyncb2;
418
 
419
reg RxEnableWindow;
420
 
421
wire SetWriteRxDataToFifo;
422
 
423
reg WriteRxDataToFifoSync1;
424
reg WriteRxDataToFifoSync2;
425
reg WriteRxDataToFifoSync3;
426
 
427
wire WriteRxDataToFifo_wb;
428
 
429
reg LatchedRxStartFrm;
430
reg SyncRxStartFrm;
431
reg SyncRxStartFrm_q;
432
reg SyncRxStartFrm_q2;
433
wire RxFifoReset;
434
 
435
wire TxError;
436
wire RxError;
437
 
438
reg RxStatusWriteLatched;
439
reg RxStatusWriteLatched_sync1;
440
reg RxStatusWriteLatched_sync2;
441
reg RxStatusWriteLatched_syncb1;
442
reg RxStatusWriteLatched_syncb2;
443
 
444
`ifdef ETH_WISHBONE_B3
445
assign m_wb_bte_o = 2'b00;    // Linear burst
446
`endif
447
 
448
assign m_wb_stb_o = m_wb_cyc_o;
449
 
450
always @ (posedge WB_CLK_I)
451
begin
452
  WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
453
end
454
 
455
assign WB_DAT_O = ram_do;
456
 
457
// Generic synchronous single-port RAM interface
458
eth_spram_256x32
459
     bd_ram
460
     (
461
      .clk     (WB_CLK_I),
462
      .rst     (Reset),
463
      .ce      (ram_ce),
464
      .we      (ram_we),
465
      .oe      (ram_oe),
466
      .addr    (ram_addr),
467
      .di      (ram_di),
468
      .dato    (ram_do)
469
`ifdef ETH_BIST
470
      ,
471
      .mbist_si_i       (mbist_si_i),
472
      .mbist_so_o       (mbist_so_o),
473
      .mbist_ctrl_i       (mbist_ctrl_i)
474
`endif
475
      );
476
 
477
assign ram_ce = 1'b1;
478
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) |
479
                {4{(TxStatusWrite | RxStatusWrite)}};
480
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q &
481
                (TxBDRead | TxPointerRead) | RxEn & RxEn_q &
482
                (RxBDRead | RxPointerRead);
483
 
484
 
485
always @ (posedge WB_CLK_I or posedge Reset)
486
begin
487
  if(Reset)
488
    TxEn_needed <= 1'b0;
489
  else
490
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
491
    TxEn_needed <= 1'b1;
492
  else
493
  if(TxPointerRead & TxEn & TxEn_q)
494
    TxEn_needed <= 1'b0;
495
end
496
 
497
// Enabling access to the RAM for three devices.
498
always @ (posedge WB_CLK_I or posedge Reset)
499
begin
500
  if(Reset)
501
    begin
502
      WbEn <= 1'b1;
503
      RxEn <= 1'b0;
504
      TxEn <= 1'b0;
505
      ram_addr <= 8'h0;
506
      ram_di <= 32'h0;
507
      BDRead <= 1'b0;
508
      BDWrite <= 0;
509
    end
510
  else
511
    begin
512
      // Switching between three stages depends on enable signals
513
     /* verilator lint_off CASEINCOMPLETE */ // JB
514
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
515
        5'b100_10, 5'b100_11 :
516
          begin
517
            WbEn <= 1'b0;
518
            RxEn <= 1'b1;  // wb access stage and r_RxEn is enabled
519
            TxEn <= 1'b0;
520
            ram_addr <= {RxBDAddress, RxPointerRead};
521
            ram_di <= RxBDDataIn;
522
          end
523
        5'b100_01 :
524
          begin
525
            WbEn <= 1'b0;
526
            RxEn <= 1'b0;
527
            TxEn <= 1'b1;  // wb access stage, r_RxEn is disabled but
528
                           // r_TxEn is enabled
529
            ram_addr <= {TxBDAddress, TxPointerRead};
530
            ram_di <= TxBDDataIn;
531
          end
532
        5'b010_00, 5'b010_10 :
533
          begin
534
            WbEn <= 1'b1;  // RxEn access stage and r_TxEn is disabled
535
            RxEn <= 1'b0;
536
            TxEn <= 1'b0;
537
            ram_addr <= WB_ADR_I[9:2];
538
            ram_di <= WB_DAT_I;
539
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
540
            BDRead <= (|BDCs) & ~WB_WE_I;
541
          end
542
        5'b010_01, 5'b010_11 :
543
          begin
544
            WbEn <= 1'b0;
545
            RxEn <= 1'b0;
546
            TxEn <= 1'b1;  // RxEn access stage and r_TxEn is enabled
547
            ram_addr <= {TxBDAddress, TxPointerRead};
548
            ram_di <= TxBDDataIn;
549
          end
550
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
551
          begin
552
            WbEn <= 1'b1;  // TxEn access stage (we always go to wb
553
                           // access stage)
554
            RxEn <= 1'b0;
555
            TxEn <= 1'b0;
556
            ram_addr <= WB_ADR_I[9:2];
557
            ram_di <= WB_DAT_I;
558
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
559
            BDRead <= (|BDCs) & ~WB_WE_I;
560
          end
561
        5'b100_00 :
562
          begin
563
            WbEn <= 1'b0;  // WbEn access stage and there is no need
564
                           // for other stages. WbEn needs to be
565
                           // switched off for a bit
566
          end
567
        5'b000_00 :
568
          begin
569
            WbEn <= 1'b1;  // Idle state. We go to WbEn access stage.
570
            RxEn <= 1'b0;
571
            TxEn <= 1'b0;
572
            ram_addr <= WB_ADR_I[9:2];
573
            ram_di <= WB_DAT_I;
574
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
575
            BDRead <= (|BDCs) & ~WB_WE_I;
576
          end
577
      endcase
578
      /* verilator lint_on CASEINCOMPLETE */
579
    end
580
end
581
 
582
 
583
// Delayed stage signals
584
always @ (posedge WB_CLK_I or posedge Reset)
585
begin
586
  if(Reset)
587
    begin
588
      WbEn_q <= 1'b0;
589
      RxEn_q <= 1'b0;
590
      TxEn_q <= 1'b0;
591
      r_TxEn_q <= 1'b0;
592
      r_RxEn_q <= 1'b0;
593
    end
594
  else
595
    begin
596
      WbEn_q <= WbEn;
597
      RxEn_q <= RxEn;
598
      TxEn_q <= TxEn;
599
      r_TxEn_q <= r_TxEn;
600
      r_RxEn_q <= r_RxEn;
601
    end
602
end
603
 
604
// Changes for tx occur every second clock. Flop is used for this manner.
605
always @ (posedge MTxClk or posedge Reset)
606
begin
607
  if(Reset)
608
    Flop <= 1'b0;
609
  else
610
  if(TxDone | TxAbort | TxRetry_q)
611
    Flop <= 1'b0;
612
  else
613
  if(TxUsedData)
614
    Flop <= ~Flop;
615
end
616
 
617
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
618
 
619
// Latching READY status of the Tx buffer descriptor
620
always @ (posedge WB_CLK_I or posedge Reset)
621
begin
622
  if(Reset)
623
    TxBDReady <= 1'b0;
624
  else
625
  if(TxEn & TxEn_q & TxBDRead)
626
    // TxBDReady is sampled only once at the beginning.
627
    TxBDReady <= ram_do[15] & (ram_do[31:16] > 4);
628
  else
629
  // Only packets larger then 4 bytes are transmitted.
630
  if(ResetTxBDReady)
631
    TxBDReady <= 1'b0;
632
end
633
 
634
// Reading the Tx buffer descriptor
635
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
636
                       ~BlockingTxBDRead & ~TxBDReady;
637
 
638
always @ (posedge WB_CLK_I or posedge Reset)
639
begin
640
  if(Reset)
641
    TxBDRead <= 1'b1;
642
  else
643
  if(StartTxBDRead)
644
    TxBDRead <= 1'b1;
645
  else
646
  if(TxBDReady)
647
    TxBDRead <= 1'b0;
648
end
649
 
650
// Reading Tx BD pointer
651
assign StartTxPointerRead = TxBDRead & TxBDReady;
652
 
653
// Reading Tx BD Pointer
654
always @ (posedge WB_CLK_I or posedge Reset)
655
begin
656
  if(Reset)
657
    TxPointerRead <= 1'b0;
658
  else
659
  if(StartTxPointerRead)
660
    TxPointerRead <= 1'b1;
661
  else
662
  if(TxEn_q)
663
    TxPointerRead <= 1'b0;
664
end
665
 
666
 
667
// Writing status back to the Tx buffer descriptor
668
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) &
669
                       TxEn & TxEn_q & ~BlockingTxStatusWrite;
670
 
671
 
672
// Status writing must occur only once. Meanwhile it is blocked.
673
always @ (posedge WB_CLK_I or posedge Reset)
674
begin
675
  if(Reset)
676
    BlockingTxStatusWrite <= 1'b0;
677
  else
678
  if(~TxDone_wb & ~TxAbort_wb)
679
    BlockingTxStatusWrite <= 1'b0;
680
  else
681
  if(TxStatusWrite)
682
    BlockingTxStatusWrite <= 1'b1;
683
end
684
 
685
 
686
// Synchronizing BlockingTxStatusWrite to MTxClk
687
always @ (posedge MTxClk or posedge Reset)
688
begin
689
  if(Reset)
690
    BlockingTxStatusWrite_sync1 <= 1'b0;
691
  else
692
    BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite;
693
end
694
 
695
// Synchronizing BlockingTxStatusWrite to MTxClk
696
always @ (posedge MTxClk or posedge Reset)
697
begin
698
  if(Reset)
699
    BlockingTxStatusWrite_sync2 <= 1'b0;
700
  else
701
    BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1;
702
end
703
 
704
// Synchronizing BlockingTxStatusWrite to MTxClk
705
always @ (posedge MTxClk or posedge Reset)
706
begin
707
  if(Reset)
708
    BlockingTxStatusWrite_sync3 <= 1'b0;
709
  else
710
    BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
711
end
712
 
713
assign RstDeferLatched = BlockingTxStatusWrite_sync2 &
714
                         ~BlockingTxStatusWrite_sync3;
715
 
716
// TxBDRead state is activated only once. 
717
always @ (posedge WB_CLK_I or posedge Reset)
718
begin
719
  if(Reset)
720
    BlockingTxBDRead <= 1'b0;
721
  else
722
  if(StartTxBDRead)
723
    BlockingTxBDRead <= 1'b1;
724
  else
725
  if(~StartTxBDRead & ~TxBDReady)
726
    BlockingTxBDRead <= 1'b0;
727
end
728
 
729
 
730
// Latching status from the tx buffer descriptor
731
// Data is avaliable one cycle after the access is started (at that time
732
// signal TxEn is not active)
733
always @ (posedge WB_CLK_I or posedge Reset)
734
begin
735
  if(Reset)
736
    TxStatus <= 4'h0;
737
  else
738
  if(TxEn & TxEn_q & TxBDRead)
739
    TxStatus <= ram_do[14:11];
740
end
741
 
742
 
743
 
744
//Latching length from the buffer descriptor;
745
always @ (posedge WB_CLK_I or posedge Reset)
746
begin
747
  if(Reset)
748
    TxLength <= 16'h0;
749
  else
750
  if(TxEn & TxEn_q & TxBDRead)
751
    TxLength <= ram_do[31:16];
752
  else
753
  if(MasterWbTX & m_wb_ack_i)
754
    begin
755
      if(TxLengthLt4)
756
        TxLength <= 16'h0;
757
      else if(TxPointerLSB_rst==2'h0)
758
        TxLength <= TxLength - 16'd4;    // Length is subtracted at
759
                                        // the data request
760
      else if(TxPointerLSB_rst==2'h1)
761
        TxLength <= TxLength - 16'd3;    // Length is subtracted
762
                                         // at the data request
763
      else if(TxPointerLSB_rst==2'h2)
764
        TxLength <= TxLength - 16'd2;    // Length is subtracted
765
                                         // at the data request
766
      else if(TxPointerLSB_rst==2'h3)
767
        TxLength <= TxLength - 16'd1;    // Length is subtracted
768
                                         // at the data request
769
    end
770
end
771
 
772
//Latching length from the buffer descriptor;
773
always @ (posedge WB_CLK_I or posedge Reset)
774
begin
775
  if(Reset)
776
    LatchedTxLength <= 16'h0;
777
  else
778
  if(TxEn & TxEn_q & TxBDRead)
779
    LatchedTxLength <= ram_do[31:16];
780
end
781
 
782
assign TxLengthEq0 = TxLength == 0;
783
assign TxLengthLt4 = TxLength < 4;
784
 
785
 
786
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
787
// latched because TxPointerMSB is only used for word-aligned accesses.
788
always @ (posedge WB_CLK_I or posedge Reset)
789
begin
790
  if(Reset)
791
    TxPointerMSB <= 30'h0;
792
  else
793
  if(TxEn & TxEn_q & TxPointerRead)
794
    TxPointerMSB <= ram_do[31:2];
795
  else
796
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
797
      // TxPointer is word-aligned
798
    TxPointerMSB <= TxPointerMSB + 1'b1;
799
end
800
 
801
 
802
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are
803
// performed, valid data does not necesserly start at byte 0 (could be byte
804
// 0, 1, 2 or 3). This signals are used for proper selection of the start
805
// byte (TxData and TxByteCnt) are set by this two bits.
806
always @ (posedge WB_CLK_I or posedge Reset)
807
begin
808
  if(Reset)
809
    TxPointerLSB[1:0] <= 0;
810
  else
811
  if(TxEn & TxEn_q & TxPointerRead)
812
    TxPointerLSB[1:0] <= ram_do[1:0];
813
end
814
 
815
 
816
// Latching 2 MSB bits of the buffer descriptor. 
817
// After the read access, TxLength needs to be decremented for the number of
818
// the valid bytes (1 to 4 bytes are valid in the first word). After the
819
// first read all bytes are valid so this two bits are reset to zero. 
820
always @ (posedge WB_CLK_I or posedge Reset)
821
begin
822
  if(Reset)
823
    TxPointerLSB_rst[1:0] <= 0;
824
  else
825
  if(TxEn & TxEn_q & TxPointerRead)
826
    TxPointerLSB_rst[1:0] <= ram_do[1:0];
827
  else
828
// After first access pointer is word alligned
829
  if(MasterWbTX & m_wb_ack_i)
830
    TxPointerLSB_rst[1:0] <= 0;
831
end
832
 
833
 
834
always @ (posedge WB_CLK_I or posedge Reset)
835
begin
836
  if(Reset)
837
    BlockingIncrementTxPointer <= 0;
838
  else
839
  if(MasterAccessFinished)
840
    BlockingIncrementTxPointer <= 0;
841
  else
842
  if(IncrTxPointer)
843
    BlockingIncrementTxPointer <= 1'b1;
844
end
845
 
846
 
847
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
848
 
849
always @ (posedge WB_CLK_I or posedge Reset)
850
begin
851
  if(Reset)
852
    ReadTxDataFromMemory <= 1'b0;
853
  else
854
  if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
855
    ReadTxDataFromMemory <= 1'b0;
856
  else
857
  if(SetReadTxDataFromMemory)
858
    ReadTxDataFromMemory <= 1'b1;
859
end
860
 
861
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
862
                                ~BlockReadTxDataFromMemory;
863
 
864
assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
865
 
866
always @ (posedge WB_CLK_I or posedge Reset)
867
begin
868
  if(Reset)
869
    BlockReadTxDataFromMemory <= 1'b0;
870
  else
871
  if((TxBufferAlmostFull | TxLength <= 4) & MasterWbTX & (~cyc_cleared) &
872
     (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
873
    BlockReadTxDataFromMemory <= 1'b1;
874
  else
875
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
876
    BlockReadTxDataFromMemory <= 1'b0;
877
end
878
 
879
 
880
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
881
 
882
// Enabling master wishbone access to the memory for two devices TX and RX.
883
always @ (posedge WB_CLK_I or posedge Reset)
884
begin
885
  if(Reset)
886
    begin
887
      MasterWbTX <= 1'b0;
888
      MasterWbRX <= 1'b0;
889
      m_wb_adr_o <= 30'h0;
890
      m_wb_cyc_o <= 1'b0;
891
      m_wb_we_o  <= 1'b0;
892
      m_wb_sel_o <= 4'h0;
893
      cyc_cleared<= 1'b0;
894
      tx_burst_cnt<= 0;
895
      rx_burst_cnt<= 0;
896
      IncrTxPointer<= 1'b0;
897
      tx_burst_en<= 1'b1;
898
      rx_burst_en<= 1'b0;
899
`ifdef ETH_WISHBONE_B3
900
      m_wb_cti_o <= 3'b0;
901
`endif
902
    end
903
  else
904
    begin
905
      // Switching between two stages depends on enable signals
906
      casez ({MasterWbTX,
907
             MasterWbRX,
908
             ReadTxDataFromMemory_2,
909
             WriteRxDataToMemory,
910
             MasterAccessFinished,
911
             cyc_cleared,
912
             tx_burst,
913
             rx_burst})  // synopsys parallel_case
914
 
915
        8'b00_10_00_10, // Idle and MRB needed
916
        8'b10_1?_10_1?, // MRB continues
917
        8'b10_10_01_10, // Clear (previously MR) and MRB needed
918
        8'b01_1?_01_1?: // Clear (previously MW) and MRB needed
919
          begin
920
            MasterWbTX <= 1'b1;  // tx burst
921
            MasterWbRX <= 1'b0;
922
            m_wb_cyc_o <= 1'b1;
923
            m_wb_we_o  <= 1'b0;
924
            m_wb_sel_o <= 4'hf;
925
            cyc_cleared<= 1'b0;
926
            IncrTxPointer<= 1'b1;
927
            tx_burst_cnt <= tx_burst_cnt+3'h1;
928
            if(tx_burst_cnt==0)
929
              m_wb_adr_o <= TxPointerMSB;
930
            else
931
              m_wb_adr_o <= m_wb_adr_o + 1'b1;
932
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
933
              begin
934
                tx_burst_en<= 1'b0;
935
`ifdef ETH_WISHBONE_B3
936
                m_wb_cti_o <= 3'b111;
937
`endif
938
              end
939
            else
940
              begin
941
`ifdef ETH_WISHBONE_B3
942
                m_wb_cti_o <= 3'b010;
943
`endif
944
              end
945
          end
946
        8'b00_?1_00_?1,             // Idle and MWB needed
947
        8'b01_?1_10_?1,             // MWB continues
948
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
949
        8'b10_?1_01_?1 :            // Clear (previously MR) and MWB needed
950
          begin
951
            MasterWbTX <= 1'b0;  // rx burst
952
            MasterWbRX <= 1'b1;
953
            m_wb_cyc_o <= 1'b1;
954
            m_wb_we_o  <= 1'b1;
955
            m_wb_sel_o <= RxByteSel;
956
            IncrTxPointer<= 1'b0;
957
            cyc_cleared<= 1'b0;
958
            rx_burst_cnt <= rx_burst_cnt+3'h1;
959
 
960
            if(rx_burst_cnt==0)
961
              m_wb_adr_o <= RxPointerMSB;
962
            else
963
              m_wb_adr_o <= m_wb_adr_o+1'b1;
964
 
965
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
966
              begin
967
                rx_burst_en<= 1'b0;
968
 `ifdef ETH_WISHBONE_B3
969
                m_wb_cti_o <= 3'b111;
970
 `endif
971
              end
972
            else
973
              begin
974
 `ifdef ETH_WISHBONE_B3
975
                m_wb_cti_o <= 3'b010;
976
 `endif
977
              end
978
          end
979
        8'b00_?1_00_?0 :// idle and MW is needed (data write to rx buffer)
980
          begin
981
            MasterWbTX <= 1'b0;
982
            MasterWbRX <= 1'b1;
983
            m_wb_adr_o <= RxPointerMSB;
984
            m_wb_cyc_o <= 1'b1;
985
            m_wb_we_o  <= 1'b1;
986
            m_wb_sel_o <= RxByteSel;
987
            IncrTxPointer<= 1'b0;
988
          end
989
        8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
990
          begin
991
            MasterWbTX <= 1'b1;
992
            MasterWbRX <= 1'b0;
993
            m_wb_adr_o <= TxPointerMSB;
994
            m_wb_cyc_o <= 1'b1;
995
            m_wb_we_o  <= 1'b0;
996
            m_wb_sel_o <= 4'hf;
997
            IncrTxPointer<= 1'b1;
998
          end
999
        8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
1000
        8'b01_1?_01_0?  :// MW and MR is needed (data read from tx buffer)
1001
          begin
1002
            MasterWbTX <= 1'b1;
1003
            MasterWbRX <= 1'b0;
1004
            m_wb_adr_o <= TxPointerMSB;
1005
            m_wb_cyc_o <= 1'b1;
1006
            m_wb_we_o  <= 1'b0;
1007
            m_wb_sel_o <= 4'hf;
1008
            cyc_cleared<= 1'b0;
1009
            IncrTxPointer<= 1'b1;
1010
          end
1011
        8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
1012
        8'b10_?1_01_?0 :// MR and MW is needed (data write to rx buffer)
1013
          begin
1014
            MasterWbTX <= 1'b0;
1015
            MasterWbRX <= 1'b1;
1016
            m_wb_adr_o <= RxPointerMSB;
1017
            m_wb_cyc_o <= 1'b1;
1018
            m_wb_we_o  <= 1'b1;
1019
            m_wb_sel_o <= RxByteSel;
1020
            cyc_cleared<= 1'b0;
1021
            IncrTxPointer<= 1'b0;
1022
          end
1023
        8'b01_01_10_00,// MW and MW needed (cycle is cleared between
1024
                      // previous and next access)
1025
        8'b01_1?_10_?0,// MW and MW or MR or MRB needed (cycle is
1026
                    // cleared between previous and next access)
1027
        8'b10_10_10_00,// MR and MR needed (cycle is cleared between
1028
                       // previous and next access)
1029
        8'b10_?1_10_0? :// MR and MR or MW or MWB (cycle is cleared
1030
                       // between previous and next access)
1031
          begin
1032
            m_wb_cyc_o <= 1'b0;// whatever and master read or write is
1033
                               // needed. We need to clear m_wb_cyc_o
1034
                               // before next access is started
1035
            cyc_cleared<= 1'b1;
1036
            IncrTxPointer<= 1'b0;
1037
            tx_burst_cnt<= 0;
1038
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1039
            rx_burst_cnt<= 0;
1040
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1041
`ifdef ETH_WISHBONE_B3
1042
              m_wb_cti_o <= 3'b0;
1043
`endif
1044
          end
1045
        8'b??_00_10_00,// whatever and no master read or write is needed
1046
                       // (ack or err comes finishing previous access)
1047
        8'b??_00_01_00 : // Between cyc_cleared request was cleared
1048
          begin
1049
            MasterWbTX <= 1'b0;
1050
            MasterWbRX <= 1'b0;
1051
            m_wb_cyc_o <= 1'b0;
1052
            cyc_cleared<= 1'b0;
1053
            IncrTxPointer<= 1'b0;
1054
            rx_burst_cnt<= 0;
1055
            // Counter is not decremented, yet, so plus1 is used.
1056
            rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 :
1057
                                       enough_data_in_rxfifo_for_burst;
1058
`ifdef ETH_WISHBONE_B3
1059
            m_wb_cti_o <= 3'b0;
1060
`endif
1061
          end
1062
        8'b00_00_00_00:  // whatever and no master read or write is needed
1063
                         // (ack or err comes finishing previous access)
1064
          begin
1065
            tx_burst_cnt<= 0;
1066
            tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1067
          end
1068
        default:                    // Don't touch
1069
          begin
1070
            MasterWbTX <= MasterWbTX;
1071
            MasterWbRX <= MasterWbRX;
1072
            m_wb_cyc_o <= m_wb_cyc_o;
1073
            m_wb_sel_o <= m_wb_sel_o;
1074
            IncrTxPointer<= IncrTxPointer;
1075
          end
1076
      endcase
1077
    end
1078
end
1079
 
1080
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1081
 
1082
eth_fifo
1083
     #(
1084
       .DATA_WIDTH(TX_FIFO_DATA_WIDTH),
1085
       .DEPTH(TX_FIFO_DEPTH),
1086
       .CNT_WIDTH(TX_FIFO_CNT_WIDTH))
1087
tx_fifo (
1088
       .data_in(m_wb_dat_i),
1089
       .data_out(TxData_wb),
1090
       .clk(WB_CLK_I),
1091
       .reset(Reset),
1092
       .write(MasterWbTX & m_wb_ack_i),
1093
       .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1094
       .clear(TxFifoClear),
1095
       .full(TxBufferFull),
1096
       .almost_full(TxBufferAlmostFull),
1097
       .almost_empty(TxBufferAlmostEmpty),
1098
       .empty(TxBufferEmpty),
1099
       .cnt(txfifo_cnt)
1100
       );
1101
 
1102
// Start: Generation of the TxStartFrm_wb which is then synchronized to the
1103
// MTxClk
1104
always @ (posedge WB_CLK_I or posedge Reset)
1105
begin
1106
  if(Reset)
1107
    TxStartFrm_wb <= 1'b0;
1108
  else
1109
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1110
    TxStartFrm_wb <= 1'b1;
1111
  else
1112
  if(TxStartFrm_syncb2)
1113
    TxStartFrm_wb <= 1'b0;
1114
end
1115
 
1116
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's
1117
// blocked.
1118
always @ (posedge WB_CLK_I or posedge Reset)
1119
begin
1120
  if(Reset)
1121
    StartOccured <= 1'b0;
1122
  else
1123
  if(TxStartFrm_wb)
1124
    StartOccured <= 1'b1;
1125
  else
1126
  if(ResetTxBDReady)
1127
    StartOccured <= 1'b0;
1128
end
1129
 
1130
// Synchronizing TxStartFrm_wb to MTxClk
1131
always @ (posedge MTxClk or posedge Reset)
1132
begin
1133
  if(Reset)
1134
    TxStartFrm_sync1 <= 1'b0;
1135
  else
1136
    TxStartFrm_sync1 <= TxStartFrm_wb;
1137
end
1138
 
1139
always @ (posedge MTxClk or posedge Reset)
1140
begin
1141
  if(Reset)
1142
    TxStartFrm_sync2 <= 1'b0;
1143
  else
1144
    TxStartFrm_sync2 <= TxStartFrm_sync1;
1145
end
1146
 
1147
always @ (posedge WB_CLK_I or posedge Reset)
1148
begin
1149
  if(Reset)
1150
    TxStartFrm_syncb1 <= 1'b0;
1151
  else
1152
    TxStartFrm_syncb1 <= TxStartFrm_sync2;
1153
end
1154
 
1155
always @ (posedge WB_CLK_I or posedge Reset)
1156
begin
1157
  if(Reset)
1158
    TxStartFrm_syncb2 <= 1'b0;
1159
  else
1160
    TxStartFrm_syncb2 <= TxStartFrm_syncb1;
1161
end
1162
 
1163
always @ (posedge MTxClk or posedge Reset)
1164
begin
1165
  if(Reset)
1166
    TxStartFrm <= 1'b0;
1167
  else
1168
  if(TxStartFrm_sync2)
1169
    TxStartFrm <= 1'b1;
1170
  else
1171
  if(TxUsedData_q | ~TxStartFrm_sync2 &
1172
     (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
1173
    TxStartFrm <= 1'b0;
1174
end
1175
// End: Generation of the TxStartFrm_wb which is then synchronized to the
1176
// MTxClk
1177
 
1178
 
1179
// TxEndFrm_wb: indicator of the end of frame
1180
always @ (posedge WB_CLK_I or posedge Reset)
1181
begin
1182
  if(Reset)
1183
    TxEndFrm_wb <= 1'b0;
1184
  else
1185
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1186
    TxEndFrm_wb <= 1'b1;
1187
  else
1188
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1189
    TxEndFrm_wb <= 1'b0;
1190
end
1191
 
1192
// Marks which bytes are valid within the word.
1193
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1194
 
1195
 
1196
always @ (posedge WB_CLK_I or posedge Reset)
1197
begin
1198
  if(Reset)
1199
    LatchValidBytes <= 1'b0;
1200
  else
1201
  if(TxLengthLt4 & TxBDReady)
1202
    LatchValidBytes <= 1'b1;
1203
  else
1204
    LatchValidBytes <= 1'b0;
1205
end
1206
 
1207
always @ (posedge WB_CLK_I or posedge Reset)
1208
begin
1209
  if(Reset)
1210
    LatchValidBytes_q <= 1'b0;
1211
  else
1212
    LatchValidBytes_q <= LatchValidBytes;
1213
end
1214
 
1215
 
1216
// Latching valid bytes
1217
always @ (posedge WB_CLK_I or posedge Reset)
1218
begin
1219
  if(Reset)
1220
    TxValidBytesLatched <= 2'h0;
1221
  else
1222
  if(LatchValidBytes & ~LatchValidBytes_q)
1223
    TxValidBytesLatched <= TxValidBytes;
1224
  else
1225
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1226
    TxValidBytesLatched <= 2'h0;
1227
end
1228
 
1229
 
1230
assign TxIRQEn          = TxStatus[14];
1231
assign WrapTxStatusBit  = TxStatus[13];
1232
assign PerPacketPad     = TxStatus[12];
1233
assign PerPacketCrcEn   = TxStatus[11];
1234
 
1235
 
1236
assign RxIRQEn         = RxStatus[14];
1237
assign WrapRxStatusBit = RxStatus[13];
1238
 
1239
 
1240
// Temporary Tx and Rx buffer descriptor address
1241
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite  & ~WrapTxStatusBit}} &
1242
                              (TxBDAddress + 1'b1); // Tx BD increment or wrap
1243
                                                    // (last BD)
1244
 
1245
assign TempRxBDAddress[7:1] =
1246
  {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
1247
  {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1); // Using next Rx BD
1248
                                                // (increment address)
1249
 
1250
// Latching Tx buffer descriptor address
1251
always @ (posedge WB_CLK_I or posedge Reset)
1252
begin
1253
  if(Reset)
1254
    TxBDAddress <= 7'h0;
1255
  else if (r_TxEn & (~r_TxEn_q))
1256
    TxBDAddress <= 7'h0;
1257
  else if (TxStatusWrite)
1258
    TxBDAddress <= TempTxBDAddress;
1259
end
1260
 
1261
// Latching Rx buffer descriptor address
1262
always @ (posedge WB_CLK_I or posedge Reset)
1263
begin
1264
  if(Reset)
1265
    RxBDAddress <= 7'h0;
1266
  else if(r_RxEn & (~r_RxEn_q))
1267
    RxBDAddress <= r_TxBDNum[6:0];
1268
  else if(RxStatusWrite)
1269
    RxBDAddress <= TempRxBDAddress;
1270
end
1271
 
1272
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0],
1273
                                RetryLimit, LateCollLatched, DeferLatched,
1274
                                CarrierSenseLost};
1275
 
1276
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1277
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1278
 
1279
 
1280
// Signals used for various purposes
1281
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1282
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1283
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1284
 
1285
 
1286
// Generating delayed signals
1287
always @ (posedge MTxClk or posedge Reset)
1288
begin
1289
  if(Reset)
1290
    begin
1291
      TxAbort_q      <= 1'b0;
1292
      TxRetry_q      <= 1'b0;
1293
      TxUsedData_q   <= 1'b0;
1294
    end
1295
  else
1296
    begin
1297
      TxAbort_q      <= TxAbort;
1298
      TxRetry_q      <= TxRetry;
1299
      TxUsedData_q   <= TxUsedData;
1300
    end
1301
end
1302
 
1303
// Generating delayed signals
1304
always @ (posedge WB_CLK_I or posedge Reset)
1305
begin
1306
  if(Reset)
1307
    begin
1308
      TxDone_wb_q   <= 1'b0;
1309
      TxAbort_wb_q  <= 1'b0;
1310
      TxRetry_wb_q  <= 1'b0;
1311
    end
1312
  else
1313
    begin
1314
      TxDone_wb_q   <= TxDone_wb;
1315
      TxAbort_wb_q  <= TxAbort_wb;
1316
      TxRetry_wb_q  <= TxRetry_wb;
1317
    end
1318
end
1319
 
1320
 
1321
reg TxAbortPacketBlocked;
1322
always @ (posedge WB_CLK_I or posedge Reset)
1323
begin
1324
  if(Reset)
1325
    TxAbortPacket <= 1'b0;
1326
  else
1327
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
1328
    (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
1329
    (~TxAbortPacketBlocked))
1330
    TxAbortPacket <= 1'b1;
1331
  else
1332
    TxAbortPacket <= 1'b0;
1333
end
1334
 
1335
 
1336
always @ (posedge WB_CLK_I or posedge Reset)
1337
begin
1338
  if(Reset)
1339
    TxAbortPacket_NotCleared <= 1'b0;
1340
  else
1341
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
1342
    TxAbortPacket_NotCleared <= 1'b0;
1343
  else
1344
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
1345
     (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
1346
     (~TxAbortPacketBlocked))
1347
    TxAbortPacket_NotCleared <= 1'b1;
1348
end
1349
 
1350
 
1351
always @ (posedge WB_CLK_I or posedge Reset)
1352
begin
1353
  if(Reset)
1354
    TxAbortPacketBlocked <= 1'b0;
1355
  else
1356
  if(!TxAbort_wb & TxAbort_wb_q)
1357
    TxAbortPacketBlocked <= 1'b0;
1358
  else
1359
  if(TxAbortPacket)
1360
    TxAbortPacketBlocked <= 1'b1;
1361
end
1362
 
1363
 
1364
reg TxRetryPacketBlocked;
1365
always @ (posedge WB_CLK_I or posedge Reset)
1366
begin
1367
  if(Reset)
1368
    TxRetryPacket <= 1'b0;
1369
  else
1370
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1371
     !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1372
    TxRetryPacket <= 1'b1;
1373
  else
1374
    TxRetryPacket <= 1'b0;
1375
end
1376
 
1377
 
1378
always @ (posedge WB_CLK_I or posedge Reset)
1379
begin
1380
  if(Reset)
1381
    TxRetryPacket_NotCleared <= 1'b0;
1382
  else
1383
  if(StartTxBDRead)
1384
    TxRetryPacket_NotCleared <= 1'b0;
1385
  else
1386
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1387
     !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1388
    TxRetryPacket_NotCleared <= 1'b1;
1389
end
1390
 
1391
 
1392
always @ (posedge WB_CLK_I or posedge Reset)
1393
begin
1394
  if(Reset)
1395
    TxRetryPacketBlocked <= 1'b0;
1396
  else
1397
  if(!TxRetry_wb & TxRetry_wb_q)
1398
    TxRetryPacketBlocked <= 1'b0;
1399
  else
1400
  if(TxRetryPacket)
1401
    TxRetryPacketBlocked <= 1'b1;
1402
end
1403
 
1404
 
1405
reg TxDonePacketBlocked;
1406
always @ (posedge WB_CLK_I or posedge Reset)
1407
begin
1408
  if(Reset)
1409
    TxDonePacket <= 1'b0;
1410
  else
1411
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1412
     !TxDonePacketBlocked | TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1413
    TxDonePacket <= 1'b1;
1414
  else
1415
    TxDonePacket <= 1'b0;
1416
end
1417
 
1418
 
1419
always @ (posedge WB_CLK_I or posedge Reset)
1420
begin
1421
  if(Reset)
1422
    TxDonePacket_NotCleared <= 1'b0;
1423
  else
1424
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
1425
    TxDonePacket_NotCleared <= 1'b0;
1426
  else
1427
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
1428
     (~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
1429
    TxDonePacket_NotCleared <= 1'b1;
1430
end
1431
 
1432
 
1433
always @ (posedge WB_CLK_I or posedge Reset)
1434
begin
1435
  if(Reset)
1436
    TxDonePacketBlocked <= 1'b0;
1437
  else
1438
  if(!TxDone_wb & TxDone_wb_q)
1439
    TxDonePacketBlocked <= 1'b0;
1440
  else
1441
  if(TxDonePacket)
1442
    TxDonePacketBlocked <= 1'b1;
1443
end
1444
 
1445
 
1446
// Indication of the last word
1447
always @ (posedge MTxClk or posedge Reset)
1448
begin
1449
  if(Reset)
1450
    LastWord <= 1'b0;
1451
  else
1452
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1453
    LastWord <= 1'b0;
1454
  else
1455
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1456
    LastWord <= TxEndFrm_wb;
1457
end
1458
 
1459
 
1460
// Tx end frame generation
1461
always @ (posedge MTxClk or posedge Reset)
1462
begin
1463
  if(Reset)
1464
    TxEndFrm <= 1'b0;
1465
  else
1466
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1467
    TxEndFrm <= 1'b0;
1468
  else
1469
  if(Flop & LastWord)
1470
    begin
1471
      case (TxValidBytesLatched)  // synopsys parallel_case
1472
        1 : TxEndFrm <= TxByteCnt == 2'h0;
1473
        2 : TxEndFrm <= TxByteCnt == 2'h1;
1474
        3 : TxEndFrm <= TxByteCnt == 2'h2;
1475
 
1476
        default : TxEndFrm <= 1'b0;
1477
      endcase
1478
    end
1479
end
1480
 
1481
 
1482
// Tx data selection (latching)
1483
always @ (posedge MTxClk or posedge Reset)
1484
begin
1485
  if(Reset)
1486
    TxData <= 0;
1487
  else
1488
  if(TxStartFrm_sync2 & ~TxStartFrm)
1489
    case(TxPointerLSB)  // synopsys parallel_case
1490
      2'h0 : TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
1491
      2'h1 : TxData <= TxData_wb[23:16];// Big Endian Byte Ordering
1492
      2'h2 : TxData <= TxData_wb[15:08];// Big Endian Byte Ordering
1493
      2'h3 : TxData <= TxData_wb[07:00];// Big Endian Byte Ordering
1494
    endcase
1495
  else
1496
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1497
    TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
1498
  else
1499
  if(TxUsedData & Flop)
1500
    begin
1501
      case(TxByteCnt)  // synopsys parallel_case
1502
 
1503
        1 : TxData <= TxDataLatched[23:16];
1504
        2 : TxData <= TxDataLatched[15:8];
1505
        3 : TxData <= TxDataLatched[7:0];
1506
      endcase
1507
    end
1508
end
1509
 
1510
 
1511
// Latching tx data
1512
always @ (posedge MTxClk or posedge Reset)
1513
begin
1514
  if(Reset)
1515
    TxDataLatched[31:0] <= 32'h0;
1516
  else
1517
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 |
1518
     TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1519
    TxDataLatched[31:0] <= TxData_wb[31:0];
1520
end
1521
 
1522
 
1523
// Tx under run
1524
always @ (posedge WB_CLK_I or posedge Reset)
1525
begin
1526
  if(Reset)
1527
    TxUnderRun_wb <= 1'b0;
1528
  else
1529
  if(TxAbortPulse)
1530
    TxUnderRun_wb <= 1'b0;
1531
  else
1532
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1533
    TxUnderRun_wb <= 1'b1;
1534
end
1535
 
1536
 
1537
reg TxUnderRun_sync1;
1538
 
1539
// Tx under run
1540
always @ (posedge MTxClk or posedge Reset)
1541
begin
1542
  if(Reset)
1543
    TxUnderRun_sync1 <= 1'b0;
1544
  else
1545
  if(TxUnderRun_wb)
1546
    TxUnderRun_sync1 <= 1'b1;
1547
  else
1548
  if(BlockingTxStatusWrite_sync2)
1549
    TxUnderRun_sync1 <= 1'b0;
1550
end
1551
 
1552
// Tx under run
1553
always @ (posedge MTxClk or posedge Reset)
1554
begin
1555
  if(Reset)
1556
    TxUnderRun <= 1'b0;
1557
  else
1558
  if(BlockingTxStatusWrite_sync2)
1559
    TxUnderRun <= 1'b0;
1560
  else
1561
  if(TxUnderRun_sync1)
1562
    TxUnderRun <= 1'b1;
1563
end
1564
 
1565
 
1566
// Tx Byte counter
1567
always @ (posedge MTxClk or posedge Reset)
1568
begin
1569
  if(Reset)
1570
    TxByteCnt <= 2'h0;
1571
  else
1572
  if(TxAbort_q | TxRetry_q)
1573
    TxByteCnt <= 2'h0;
1574
  else
1575
  if(TxStartFrm & ~TxUsedData)
1576
    case(TxPointerLSB)  // synopsys parallel_case
1577
      2'h0 : TxByteCnt <= 2'h1;
1578
      2'h1 : TxByteCnt <= 2'h2;
1579
      2'h2 : TxByteCnt <= 2'h3;
1580
      2'h3 : TxByteCnt <= 2'h0;
1581
    endcase
1582
  else
1583
  if(TxUsedData & Flop)
1584
    TxByteCnt <= TxByteCnt + 1'b1;
1585
end
1586
 
1587
 
1588
always @ (posedge MTxClk or posedge Reset)
1589
begin
1590
  if(Reset)
1591
    ReadTxDataFromFifo_tck <= 1'b0;
1592
  else
1593
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 &
1594
     ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1595
     ReadTxDataFromFifo_tck <= 1'b1;
1596
  else
1597
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1598
    ReadTxDataFromFifo_tck <= 1'b0;
1599
end
1600
 
1601
// Synchronizing TxStartFrm_wb to MTxClk
1602
always @ (posedge WB_CLK_I or posedge Reset)
1603
begin
1604
  if(Reset)
1605
    ReadTxDataFromFifo_sync1 <= 1'b0;
1606
  else
1607
    ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck;
1608
end
1609
 
1610
always @ (posedge WB_CLK_I or posedge Reset)
1611
begin
1612
  if(Reset)
1613
    ReadTxDataFromFifo_sync2 <= 1'b0;
1614
  else
1615
    ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1;
1616
end
1617
 
1618
always @ (posedge MTxClk or posedge Reset)
1619
begin
1620
  if(Reset)
1621
    ReadTxDataFromFifo_syncb1 <= 1'b0;
1622
  else
1623
    ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2;
1624
end
1625
 
1626
always @ (posedge MTxClk or posedge Reset)
1627
begin
1628
  if(Reset)
1629
    ReadTxDataFromFifo_syncb2 <= 1'b0;
1630
  else
1631
    ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1;
1632
end
1633
 
1634
always @ (posedge MTxClk or posedge Reset)
1635
begin
1636
  if(Reset)
1637
    ReadTxDataFromFifo_syncb3 <= 1'b0;
1638
  else
1639
    ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2;
1640
end
1641
 
1642
always @ (posedge WB_CLK_I or posedge Reset)
1643
begin
1644
  if(Reset)
1645
    ReadTxDataFromFifo_sync3 <= 1'b0;
1646
  else
1647
    ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
1648
end
1649
 
1650
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 &
1651
                               ~ReadTxDataFromFifo_sync3;
1652
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization
1653
// to the WB_CLK_I
1654
 
1655
 
1656
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1657
always @ (posedge WB_CLK_I or posedge Reset)
1658
begin
1659
  if(Reset)
1660
    TxRetrySync1 <= 1'b0;
1661
  else
1662
    TxRetrySync1 <= TxRetry;
1663
end
1664
 
1665
always @ (posedge WB_CLK_I or posedge Reset)
1666
begin
1667
  if(Reset)
1668
    TxRetry_wb <= 1'b0;
1669
  else
1670
    TxRetry_wb <= TxRetrySync1;
1671
end
1672
 
1673
 
1674
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1675
always @ (posedge WB_CLK_I or posedge Reset)
1676
begin
1677
  if(Reset)
1678
    TxDoneSync1 <= 1'b0;
1679
  else
1680
    TxDoneSync1 <= TxDone;
1681
end
1682
 
1683
always @ (posedge WB_CLK_I or posedge Reset)
1684
begin
1685
  if(Reset)
1686
    TxDone_wb <= 1'b0;
1687
  else
1688
    TxDone_wb <= TxDoneSync1;
1689
end
1690
 
1691
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1692
always @ (posedge WB_CLK_I or posedge Reset)
1693
begin
1694
  if(Reset)
1695
    TxAbortSync1 <= 1'b0;
1696
  else
1697
    TxAbortSync1 <= TxAbort;
1698
end
1699
 
1700
always @ (posedge WB_CLK_I or posedge Reset)
1701
begin
1702
  if(Reset)
1703
    TxAbort_wb <= 1'b0;
1704
  else
1705
    TxAbort_wb <= TxAbortSync1;
1706
end
1707
 
1708
 
1709
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
1710
                       r_RxEn & ~r_RxEn_q;
1711
 
1712
// Reading the Rx buffer descriptor
1713
always @ (posedge WB_CLK_I or posedge Reset)
1714
begin
1715
  if(Reset)
1716
    RxBDRead <= 1'b0;
1717
  else
1718
  if(StartRxBDRead & ~RxReady)
1719
    RxBDRead <= 1'b1;
1720
  else
1721
  if(RxBDReady)
1722
    RxBDRead <= 1'b0;
1723
end
1724
 
1725
 
1726
// Reading of the next receive buffer descriptor starts after reception status
1727
// is written to the previous one.
1728
 
1729
// Latching READY status of the Rx buffer descriptor
1730
always @ (posedge WB_CLK_I or posedge Reset)
1731
begin
1732
  if(Reset)
1733
    RxBDReady <= 1'b0;
1734
  else
1735
  if(RxPointerRead)
1736
    RxBDReady <= 1'b0;
1737
  else
1738
  if(RxEn & RxEn_q & RxBDRead)
1739
    RxBDReady <= ram_do[15];// RxBDReady is sampled only once at the beginning
1740
end
1741
 
1742
// Latching Rx buffer descriptor status
1743
// Data is avaliable one cycle after the access is started (at that time
1744
// signal RxEn is not active)
1745
always @ (posedge WB_CLK_I or posedge Reset)
1746
begin
1747
  if(Reset)
1748
    RxStatus <= 2'h0;
1749
  else
1750
  if(RxEn & RxEn_q & RxBDRead)
1751
    RxStatus <= ram_do[14:13];
1752
end
1753
 
1754
 
1755
// RxReady generation
1756
always @ (posedge WB_CLK_I or posedge Reset)
1757
begin
1758
  if(Reset)
1759
    RxReady <= 1'b0;
1760
  else if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
1761
    RxReady <= 1'b0;
1762
  else if(RxEn & RxEn_q & RxPointerRead)
1763
    RxReady <= 1'b1;
1764
end
1765
 
1766
 
1767
// Reading Rx BD pointer
1768
assign StartRxPointerRead = RxBDRead & RxBDReady;
1769
 
1770
// Reading Tx BD Pointer
1771
always @ (posedge WB_CLK_I or posedge Reset)
1772
begin
1773
  if(Reset)
1774
    RxPointerRead <= 1'b0;
1775
  else
1776
  if(StartRxPointerRead)
1777
    RxPointerRead <= 1'b1;
1778
  else
1779
  if(RxEn & RxEn_q)
1780
    RxPointerRead <= 1'b0;
1781
end
1782
 
1783
 
1784
//Latching Rx buffer pointer from buffer descriptor;
1785
always @ (posedge WB_CLK_I or posedge Reset)
1786
begin
1787
  if(Reset)
1788
    RxPointerMSB <= 30'h0;
1789
  else
1790
  if(RxEn & RxEn_q & RxPointerRead)
1791
    RxPointerMSB <= ram_do[31:2];
1792
  else
1793
  if(MasterWbRX & m_wb_ack_i)
1794
      RxPointerMSB <= RxPointerMSB + 1'b1; // Word access (always word access.
1795
                                           // m_wb_sel_o are used for
1796
                                           // selecting bytes)
1797
end
1798
 
1799
 
1800
//Latching last addresses from buffer descriptor (used as byte-half-word
1801
//indicator);
1802
always @ (posedge WB_CLK_I or posedge Reset)
1803
begin
1804
  if(Reset)
1805
    RxPointerLSB_rst[1:0] <= 0;
1806
  else
1807
  if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
1808
    RxPointerLSB_rst[1:0] <= 0;
1809
  else
1810
  if(RxEn & RxEn_q & RxPointerRead)
1811
    RxPointerLSB_rst[1:0] <= ram_do[1:0];
1812
end
1813
 
1814
 
1815
always @ (RxPointerLSB_rst)
1816
begin
1817
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1818
    2'h0 : RxByteSel[3:0] = 4'hf;
1819
    2'h1 : RxByteSel[3:0] = 4'h7;
1820
    2'h2 : RxByteSel[3:0] = 4'h3;
1821
    2'h3 : RxByteSel[3:0] = 4'h1;
1822
  endcase
1823
end
1824
 
1825
 
1826
always @ (posedge WB_CLK_I or posedge Reset)
1827
begin
1828
  if(Reset)
1829
    RxEn_needed <= 1'b0;
1830
  else if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1831
    RxEn_needed <= 1'b1;
1832
  else if(RxPointerRead & RxEn & RxEn_q)
1833
    RxEn_needed <= 1'b0;
1834
end
1835
 
1836
 
1837
// Reception status is written back to the buffer descriptor after the end
1838
// of frame is detected.
1839
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1840
 
1841
 
1842
// Indicating that last byte is being reveived
1843
always @ (posedge MRxClk or posedge Reset)
1844
begin
1845
  if(Reset)
1846
    LastByteIn <= 1'b0;
1847
  else
1848
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1849
    LastByteIn <= 1'b0;
1850
  else
1851
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1852
    LastByteIn <= 1'b1;
1853
end
1854
 
1855
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) &
1856
                           RxEnableWindow;
1857
 
1858
// Indicating that data reception will end
1859
always @ (posedge MRxClk or posedge Reset)
1860
begin
1861
  if(Reset)
1862
    ShiftWillEnd <= 1'b0;
1863
  else
1864
  if(ShiftEnded_rck | RxAbort)
1865
    ShiftWillEnd <= 1'b0;
1866
  else
1867
  if(StartShiftWillEnd)
1868
    ShiftWillEnd <= 1'b1;
1869
end
1870
 
1871
 
1872
// Receive byte counter
1873
always @ (posedge MRxClk or posedge Reset)
1874
begin
1875
  if(Reset)
1876
    RxByteCnt <= 2'h0;
1877
  else
1878
  if(ShiftEnded_rck | RxAbort)
1879
    RxByteCnt <= 2'h0;
1880
  else
1881
  if(RxValid & RxStartFrm & RxReady)
1882
    case(RxPointerLSB_rst)  // synopsys parallel_case
1883
      2'h0 : RxByteCnt <= 2'h1;
1884
      2'h1 : RxByteCnt <= 2'h2;
1885
      2'h2 : RxByteCnt <= 2'h3;
1886
      2'h3 : RxByteCnt <= 2'h0;
1887
    endcase
1888
  else
1889
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
1890
    RxByteCnt <= RxByteCnt + 1'b1;
1891
end
1892
 
1893
 
1894
// Indicates how many bytes are valid within the last word
1895
always @ (posedge MRxClk or posedge Reset)
1896
begin
1897
  if(Reset)
1898
    RxValidBytes <= 2'h1;
1899
  else
1900
  if(RxValid & RxStartFrm)
1901
    case(RxPointerLSB_rst)  // synopsys parallel_case
1902
      2'h0 : RxValidBytes <= 2'h1;
1903
      2'h1 : RxValidBytes <= 2'h2;
1904
      2'h2 : RxValidBytes <= 2'h3;
1905
      2'h3 : RxValidBytes <= 2'h0;
1906
    endcase
1907
  else
1908
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
1909
    RxValidBytes <= RxValidBytes + 1'b1;
1910
end
1911
 
1912
 
1913
always @ (posedge MRxClk or posedge Reset)
1914
begin
1915
  if(Reset)
1916
    RxDataLatched1       <= 24'h0;
1917
  else
1918
  if(RxValid & RxReady & ~LastByteIn)
1919
    if(RxStartFrm)
1920
    begin
1921
      case(RxPointerLSB_rst)     // synopsys parallel_case
1922
        // Big Endian Byte Ordering
1923
        2'h0:        RxDataLatched1[31:24] <= RxData;
1924
        2'h1:        RxDataLatched1[23:16] <= RxData;
1925
        2'h2:        RxDataLatched1[15:8]  <= RxData;
1926
        2'h3:        RxDataLatched1        <= RxDataLatched1;
1927
      endcase
1928
    end
1929
    else if (RxEnableWindow)
1930
    begin
1931
      case(RxByteCnt)     // synopsys parallel_case
1932
        // Big Endian Byte Ordering
1933
        2'h0:        RxDataLatched1[31:24] <= RxData;
1934
        2'h1:        RxDataLatched1[23:16] <= RxData;
1935
        2'h2:        RxDataLatched1[15:8]  <= RxData;
1936
        2'h3:        RxDataLatched1        <= RxDataLatched1;
1937
      endcase
1938
    end
1939
end
1940
 
1941
// Assembling data that will be written to the rx_fifo
1942
always @ (posedge MRxClk or posedge Reset)
1943
begin
1944
  if(Reset)
1945
    RxDataLatched2 <= 32'h0;
1946
  else
1947
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
1948
    // Big Endian Byte Ordering
1949
    RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
1950
  else
1951
  if(SetWriteRxDataToFifo & ShiftWillEnd)
1952
    case(RxValidBytes)  // synopsys parallel_case
1953
      // Big Endian Byte Ordering
1954
 
1955
      1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
1956
      2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
1957
      3 : RxDataLatched2 <= {RxDataLatched1[31:8],   8'h0};
1958
    endcase
1959
end
1960
 
1961
 
1962
// Indicating start of the reception process
1963
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm &
1964
                              RxEnableWindow & (&RxByteCnt))
1965
                              |(RxValid & RxReady &  RxStartFrm &
1966
                              (&RxPointerLSB_rst))
1967
                              |(ShiftWillEnd & LastByteIn & (&RxByteCnt));
1968
 
1969
always @ (posedge MRxClk or posedge Reset)
1970
begin
1971
  if(Reset)
1972
    WriteRxDataToFifo <= 1'b0;
1973
  else
1974
  if(SetWriteRxDataToFifo & ~RxAbort)
1975
    WriteRxDataToFifo <= 1'b1;
1976
  else
1977
  if(WriteRxDataToFifoSync2 | RxAbort)
1978
    WriteRxDataToFifo <= 1'b0;
1979
end
1980
 
1981
 
1982
always @ (posedge WB_CLK_I or posedge Reset)
1983
begin
1984
  if(Reset)
1985
    WriteRxDataToFifoSync1 <= 1'b0;
1986
  else
1987
  if(WriteRxDataToFifo)
1988
    WriteRxDataToFifoSync1 <= 1'b1;
1989
  else
1990
    WriteRxDataToFifoSync1 <= 1'b0;
1991
end
1992
 
1993
always @ (posedge WB_CLK_I or posedge Reset)
1994
begin
1995
  if(Reset)
1996
    WriteRxDataToFifoSync2 <= 1'b0;
1997
  else
1998
    WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1;
1999
end
2000
 
2001
always @ (posedge WB_CLK_I or posedge Reset)
2002
begin
2003
  if(Reset)
2004
    WriteRxDataToFifoSync3 <= 1'b0;
2005
  else
2006
    WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
2007
end
2008
 
2009
 
2010
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
2011
                              ~WriteRxDataToFifoSync3;
2012
 
2013
 
2014
always @ (posedge MRxClk or posedge Reset)
2015
begin
2016
  if(Reset)
2017
    LatchedRxStartFrm <= 0;
2018
  else
2019
  if(RxStartFrm & ~SyncRxStartFrm_q)
2020
    LatchedRxStartFrm <= 1;
2021
  else
2022
  if(SyncRxStartFrm_q)
2023
    LatchedRxStartFrm <= 0;
2024
end
2025
 
2026
 
2027
always @ (posedge WB_CLK_I or posedge Reset)
2028
begin
2029
  if(Reset)
2030
    SyncRxStartFrm <= 0;
2031
  else
2032
  if(LatchedRxStartFrm)
2033
    SyncRxStartFrm <= 1;
2034
  else
2035
    SyncRxStartFrm <= 0;
2036
end
2037
 
2038
 
2039
always @ (posedge WB_CLK_I or posedge Reset)
2040
begin
2041
  if(Reset)
2042
    SyncRxStartFrm_q <= 0;
2043
  else
2044
    SyncRxStartFrm_q <= SyncRxStartFrm;
2045
end
2046
 
2047
always @ (posedge WB_CLK_I or posedge Reset)
2048
begin
2049
  if(Reset)
2050
    SyncRxStartFrm_q2 <= 0;
2051
  else
2052
    SyncRxStartFrm_q2 <= SyncRxStartFrm_q;
2053
end
2054
 
2055
 
2056
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2057
 
2058
eth_fifo #(
2059
           .DATA_WIDTH(RX_FIFO_DATA_WIDTH),
2060
           .DEPTH(RX_FIFO_DEPTH),
2061
           .CNT_WIDTH(RX_FIFO_CNT_WIDTH))
2062
rx_fifo (
2063
         .clk            (WB_CLK_I),
2064
         .reset          (Reset),
2065
         // Inputs
2066
         .data_in        (RxDataLatched2),
2067
         .write          (WriteRxDataToFifo_wb & ~RxBufferFull),
2068
         .read           (MasterWbRX & m_wb_ack_i),
2069
         .clear          (RxFifoReset),
2070
         // Outputs
2071
         .data_out       (m_wb_dat_o),
2072
         .full           (RxBufferFull),
2073
         .almost_full    (),
2074
         .almost_empty   (RxBufferAlmostEmpty),
2075
         .empty          (RxBufferEmpty),
2076
         .cnt            (rxfifo_cnt)
2077
        );
2078
 
2079
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2080
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2081
assign WriteRxDataToMemory = ~RxBufferEmpty;
2082
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2083
 
2084
 
2085
// Generation of the end-of-frame signal
2086
always @ (posedge MRxClk or posedge Reset)
2087
begin
2088
  if(Reset)
2089
    ShiftEnded_rck <= 1'b0;
2090
  else
2091
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2092
    ShiftEnded_rck <= 1'b1;
2093
  else
2094
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2095
    ShiftEnded_rck <= 1'b0;
2096
end
2097
 
2098
always @ (posedge WB_CLK_I or posedge Reset)
2099
begin
2100
  if(Reset)
2101
    ShiftEndedSync1 <= 1'b0;
2102
  else
2103
    ShiftEndedSync1 <= ShiftEnded_rck;
2104
end
2105
 
2106
always @ (posedge WB_CLK_I or posedge Reset)
2107
begin
2108
  if(Reset)
2109
    ShiftEndedSync2 <= 1'b0;
2110
  else
2111
    ShiftEndedSync2 <= ShiftEndedSync1;
2112
end
2113
 
2114
always @ (posedge WB_CLK_I or posedge Reset)
2115
begin
2116
  if(Reset)
2117
    ShiftEndedSync3 <= 1'b0;
2118
  else
2119
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2120
    ShiftEndedSync3 <= 1'b1;
2121
  else
2122
  if(ShiftEnded)
2123
    ShiftEndedSync3 <= 1'b0;
2124
end
2125
 
2126
// Generation of the end-of-frame signal
2127
always @ (posedge WB_CLK_I or posedge Reset)
2128
begin
2129
  if(Reset)
2130
    ShiftEnded <= 1'b0;
2131
  else
2132
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2133
    ShiftEnded <= 1'b1;
2134
  else
2135
  if(RxStatusWrite)
2136
    ShiftEnded <= 1'b0;
2137
end
2138
 
2139
always @ (posedge MRxClk or posedge Reset)
2140
begin
2141
  if(Reset)
2142
    ShiftEndedSync_c1 <= 1'b0;
2143
  else
2144
    ShiftEndedSync_c1 <= ShiftEndedSync2;
2145
end
2146
 
2147
always @ (posedge MRxClk or posedge Reset)
2148
begin
2149
  if(Reset)
2150
    ShiftEndedSync_c2 <= 1'b0;
2151
  else
2152
    ShiftEndedSync_c2 <= ShiftEndedSync_c1;
2153
end
2154
 
2155
// Generation of the end-of-frame signal
2156
always @ (posedge MRxClk or posedge Reset)
2157
begin
2158
  if(Reset)
2159
    RxEnableWindow <= 1'b0;
2160
  else if(RxStartFrm)
2161
    RxEnableWindow <= 1'b1;
2162
  else if(RxEndFrm | RxAbort)
2163
    RxEnableWindow <= 1'b0;
2164
end
2165
 
2166
 
2167
always @ (posedge WB_CLK_I or posedge Reset)
2168
begin
2169
  if(Reset)
2170
    RxAbortSync1 <= 1'b0;
2171
  else
2172
    RxAbortSync1 <= RxAbortLatched;
2173
end
2174
 
2175
always @ (posedge WB_CLK_I or posedge Reset)
2176
begin
2177
  if(Reset)
2178
    RxAbortSync2 <= 1'b0;
2179
  else
2180
    RxAbortSync2 <= RxAbortSync1;
2181
end
2182
 
2183
always @ (posedge WB_CLK_I or posedge Reset)
2184
begin
2185
  if(Reset)
2186
    RxAbortSync3 <= 1'b0;
2187
  else
2188
    RxAbortSync3 <= RxAbortSync2;
2189
end
2190
 
2191
always @ (posedge WB_CLK_I or posedge Reset)
2192
begin
2193
  if(Reset)
2194
    RxAbortSync4 <= 1'b0;
2195
  else
2196
    RxAbortSync4 <= RxAbortSync3;
2197
end
2198
 
2199
always @ (posedge MRxClk or posedge Reset)
2200
begin
2201
  if(Reset)
2202
    RxAbortSyncb1 <= 1'b0;
2203
  else
2204
    RxAbortSyncb1 <= RxAbortSync2;
2205
end
2206
 
2207
always @ (posedge MRxClk or posedge Reset)
2208
begin
2209
  if(Reset)
2210
    RxAbortSyncb2 <= 1'b0;
2211
  else
2212
    RxAbortSyncb2 <= RxAbortSyncb1;
2213
end
2214
 
2215
 
2216
always @ (posedge MRxClk or posedge Reset)
2217
begin
2218
  if(Reset)
2219
    RxAbortLatched <= 1'b0;
2220
  else
2221
  if(RxAbortSyncb2)
2222
    RxAbortLatched <= 1'b0;
2223
  else
2224
  if(RxAbort)
2225
    RxAbortLatched <= 1'b1;
2226
end
2227
 
2228
 
2229
always @ (posedge MRxClk or posedge Reset)
2230
begin
2231
  if(Reset)
2232
    LatchedRxLength[15:0] <= 16'h0;
2233
  else
2234
  if(LoadRxStatus)
2235
    LatchedRxLength[15:0] <= RxLength[15:0];
2236
end
2237
 
2238
 
2239
assign RxStatusIn = {ReceivedPauseFrm,
2240
                     AddressMiss,
2241
                     RxOverrun,
2242
                     InvalidSymbol,
2243
                     DribbleNibble,
2244
                     ReceivedPacketTooBig,
2245
                     ShortFrame,
2246
                     LatchedCrcError,
2247
                     RxLateCollision};
2248
 
2249
always @ (posedge MRxClk or posedge Reset)
2250
begin
2251
  if(Reset)
2252
    RxStatusInLatched <= 'h0;
2253
  else
2254
  if(LoadRxStatus)
2255
    RxStatusInLatched <= RxStatusIn;
2256
end
2257
 
2258
 
2259
// Rx overrun
2260
always @ (posedge WB_CLK_I or posedge Reset)
2261
begin
2262
  if(Reset)
2263
    RxOverrun <= 1'b0;
2264
  else if(RxStatusWrite)
2265
    RxOverrun <= 1'b0;
2266
  else if(RxBufferFull & WriteRxDataToFifo_wb)
2267
    RxOverrun <= 1'b1;
2268
end
2269
 
2270
 
2271
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2272
 
2273
 
2274
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2275
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2276
// AddressMiss is identifying that a frame was received because of the
2277
// promiscous mode and is not an error
2278
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2279
 
2280
 
2281
// Latching and synchronizing RxStatusWrite signal. This signal is used for
2282
// clearing the ReceivedPauseFrm signal
2283
always @ (posedge WB_CLK_I or posedge Reset)
2284
begin
2285
  if(Reset)
2286
    RxStatusWriteLatched <= 1'b0;
2287
  else
2288
  if(RxStatusWriteLatched_syncb2)
2289
    RxStatusWriteLatched <= 1'b0;
2290
  else
2291
  if(RxStatusWrite)
2292
    RxStatusWriteLatched <= 1'b1;
2293
end
2294
 
2295
 
2296
always @ (posedge MRxClk or posedge Reset)
2297
begin
2298
  if(Reset)
2299
    begin
2300
      RxStatusWriteLatched_sync1 <= 1'b0;
2301
      RxStatusWriteLatched_sync2 <= 1'b0;
2302
    end
2303
  else
2304
    begin
2305
      RxStatusWriteLatched_sync1 <= RxStatusWriteLatched;
2306
      RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1;
2307
    end
2308
end
2309
 
2310
 
2311
always @ (posedge WB_CLK_I or posedge Reset)
2312
begin
2313
  if(Reset)
2314
    begin
2315
      RxStatusWriteLatched_syncb1 <= 1'b0;
2316
      RxStatusWriteLatched_syncb2 <= 1'b0;
2317
    end
2318
  else
2319
    begin
2320
      RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2;
2321
      RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1;
2322
    end
2323
end
2324
 
2325
 
2326
// Tx Done Interrupt
2327
always @ (posedge WB_CLK_I or posedge Reset)
2328
begin
2329
  if(Reset)
2330
    TxB_IRQ <= 1'b0;
2331
  else
2332
  if(TxStatusWrite & TxIRQEn)
2333
    TxB_IRQ <= ~TxError;
2334
  else
2335
    TxB_IRQ <= 1'b0;
2336
end
2337
 
2338
 
2339
// Tx Error Interrupt
2340
always @ (posedge WB_CLK_I or posedge Reset)
2341
begin
2342
  if(Reset)
2343
    TxE_IRQ <= 1'b0;
2344
  else
2345
  if(TxStatusWrite & TxIRQEn)
2346
    TxE_IRQ <= TxError;
2347
  else
2348
    TxE_IRQ <= 1'b0;
2349
end
2350
 
2351
 
2352
// Rx Done Interrupt
2353
always @ (posedge WB_CLK_I or posedge Reset)
2354
begin
2355
  if(Reset)
2356
    RxB_IRQ <= 1'b0;
2357
  else
2358
  if(RxStatusWrite & RxIRQEn & ReceivedPacketGood &
2359
     (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2360
    RxB_IRQ <= (~RxError);
2361
  else
2362
    RxB_IRQ <= 1'b0;
2363
end
2364
 
2365
 
2366
// Rx Error Interrupt
2367
always @ (posedge WB_CLK_I or posedge Reset)
2368
begin
2369
  if(Reset)
2370
    RxE_IRQ <= 1'b0;
2371
  else
2372
  if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm
2373
     & r_PassAll & (~r_RxFlow)))
2374
    RxE_IRQ <= RxError;
2375
  else
2376
    RxE_IRQ <= 1'b0;
2377
end
2378
 
2379
 
2380
// Busy Interrupt
2381
 
2382
reg Busy_IRQ_rck;
2383
reg Busy_IRQ_sync1;
2384
reg Busy_IRQ_sync2;
2385
reg Busy_IRQ_sync3;
2386
reg Busy_IRQ_syncb1;
2387
reg Busy_IRQ_syncb2;
2388
 
2389
 
2390
always @ (posedge MRxClk or posedge Reset)
2391
begin
2392
  if(Reset)
2393
    Busy_IRQ_rck <= 1'b0;
2394
  else
2395
  if(RxValid & RxStartFrm & ~RxReady)
2396
    Busy_IRQ_rck <= 1'b1;
2397
  else
2398
  if(Busy_IRQ_syncb2)
2399
    Busy_IRQ_rck <= 1'b0;
2400
end
2401
 
2402
always @ (posedge WB_CLK_I)
2403
begin
2404
    Busy_IRQ_sync1 <= Busy_IRQ_rck;
2405
    Busy_IRQ_sync2 <= Busy_IRQ_sync1;
2406
    Busy_IRQ_sync3 <= Busy_IRQ_sync2;
2407
end
2408
 
2409
always @ (posedge MRxClk)
2410
begin
2411
    Busy_IRQ_syncb1 <= Busy_IRQ_sync2;
2412
    Busy_IRQ_syncb2 <= Busy_IRQ_syncb1;
2413
end
2414
 
2415
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2416
 
2417
 
2418
// Assign the debug output
2419
`ifdef WISHBONE_DEBUG
2420
// Top byte, burst progress counters
2421
assign dbg_dat0[31] = 0;
2422
assign dbg_dat0[30:28] = rx_burst_cnt;
2423
assign dbg_dat0[27] = 0;
2424
assign dbg_dat0[26:24] = tx_burst_cnt;
2425
// Third byte
2426
assign dbg_dat0[23] = 0; //rx_ethside_fifo_sel;
2427
assign dbg_dat0[22] = 0; //rx_wbside_fifo_sel;
2428
assign dbg_dat0[21] = 0; //rx_fifo0_empty;
2429
assign dbg_dat0[20] = 0; //rx_fifo1_empty;
2430
assign dbg_dat0[19] = 0; //overflow_bug_reset;
2431
assign dbg_dat0[18] = 0; //RxBDOK;
2432
assign dbg_dat0[17] = 0; //write_rx_data_to_memory_go;
2433
assign dbg_dat0[16] = 0; //rx_wb_last_writes;
2434
// Second byte - TxBDAddress - or TX BD address pointer
2435
assign dbg_dat0[15:8] = { BlockingTxBDRead , TxBDAddress};
2436
// Bottom byte - FSM controlling vector
2437
assign dbg_dat0[7:0] = {MasterWbTX,
2438
                       MasterWbRX,
2439
                       ReadTxDataFromMemory_2,
2440
                       WriteRxDataToMemory,
2441
                       MasterAccessFinished,
2442
                       cyc_cleared,
2443
                       tx_burst,
2444
                       rx_burst};
2445
`else
2446
assign dbg_dat0 = 0;
2447
`endif
2448
 
2449
 
2450
endmodule

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