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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [iba_modules.v] - Blame information for rev 2

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/*****************************************************************************/
// Id ..........iba_modules.v                                                 //
// Author.......Ran Minerbi                                                   //
//                                                                            //
//   Unit Description   :                                                     //
//    iba collect  frames from physical layer.                                //
//    Keeps payload of frames that received                                   //
//    And haven't been sent yet.                                              //
//    Iba save a copy of the payload and send                                 //
//    Packet descriptors to dcp unit.                                         //
//    Iba send frames to XBar upon receiving                                  //
//    READY signal from dpq module.                                           //
//                                                                            //                                                                        //
//                                                                            //
/*****************************************************************************/
 
 
module mem_units(reset,clk,Dw1_iba_i,mem_u_o1,headers_o1,start_length1,StartFrm1,EndFrm1,transmit_done1,adr_valid1,
                           Dw2_iba_i,mem_u_o2,headers_o2,start_length2,StartFrm2,EndFrm2,transmit_done2,adr_valid2,
                           Dw3_iba_i,mem_u_o3,headers_o3,start_length3,StartFrm3,EndFrm3,transmit_done3,adr_valid3,
                           Dw4_iba_i,mem_u_o4,headers_o4,start_length4,StartFrm4,EndFrm4,transmit_done4,adr_valid4,
                           Dw5_iba_i,mem_u_o5,headers_o5,start_length5,StartFrm5,EndFrm5,transmit_done5,adr_valid5,
                           Dw6_iba_i,mem_u_o6,headers_o6,start_length6,StartFrm6,EndFrm6,transmit_done6,adr_valid6
 
                 );
 
   input reset, clk,StartFrm1,EndFrm1,
                    StartFrm2,EndFrm2,
                    StartFrm3,EndFrm3,
                    StartFrm4,EndFrm4,
                    StartFrm5,EndFrm5,
                    StartFrm6,EndFrm6;
            output  transmit_done1,
                    transmit_done2,
                    transmit_done3,
                    transmit_done4,
                    transmit_done5,
                    transmit_done6;
   input [31:0] Dw1_iba_i,Dw2_iba_i,Dw3_iba_i,Dw4_iba_i,Dw5_iba_i,Dw6_iba_i;
   output [31:0] mem_u_o1,mem_u_o2,mem_u_o3,mem_u_o4,mem_u_o5,mem_u_o6;
   output [31:0] headers_o1,headers_o2,headers_o3,headers_o4,headers_o5,headers_o6;
   input [15:0] start_length1,start_length2,start_length3,start_length4,start_length5,start_length6;//from DPQ
   input adr_valid1,adr_valid2,adr_valid3,adr_valid4,adr_valid5,adr_valid6;
   mem_basic_unit basic_mem1(.reset(reset),.clk(clk),.Dw_iba_i(Dw1_iba_i),.ram_do(mem_u_o1),.StartFrm(StartFrm1),.EndFrm(EndFrm1),.header_to_dcp(headers_o1),.start_length(start_length1),.transmit_done(transmit_done1),.adr_valid(adr_valid1));
   mem_basic_unit basic_mem2(.reset(reset),.clk(clk),.Dw_iba_i(Dw2_iba_i),.ram_do(mem_u_o2),.StartFrm(StartFrm2),.EndFrm(EndFrm2),.header_to_dcp(headers_o2),.start_length(start_length2),.transmit_done(transmit_done2),.adr_valid(adr_valid2));
   mem_basic_unit basic_mem3(.reset(reset),.clk(clk),.Dw_iba_i(Dw3_iba_i),.ram_do(mem_u_o3),.StartFrm(StartFrm3),.EndFrm(EndFrm3),.header_to_dcp(headers_o3),.start_length(start_length3),.transmit_done(transmit_done3),.adr_valid(adr_valid3));
   mem_basic_unit basic_mem4(.reset(reset),.clk(clk),.Dw_iba_i(Dw4_iba_i),.ram_do(mem_u_o4),.StartFrm(StartFrm4),.EndFrm(EndFrm4),.header_to_dcp(headers_o4),.start_length(start_length4),.transmit_done(transmit_done4),.adr_valid(adr_valid4));
   mem_basic_unit basic_mem5(.reset(reset),.clk(clk),.Dw_iba_i(Dw5_iba_i),.ram_do(mem_u_o5),.StartFrm(StartFrm5),.EndFrm(EndFrm5),.header_to_dcp(headers_o5),.start_length(start_length5),.transmit_done(transmit_done5),.adr_valid(adr_valid5));
   mem_basic_unit basic_mem6(.reset(reset),.clk(clk),.Dw_iba_i(Dw6_iba_i),.ram_do(mem_u_o6),.StartFrm(StartFrm6),.EndFrm(EndFrm6),.header_to_dcp(headers_o6),.start_length(start_length6),.transmit_done(transmit_done6),.adr_valid(adr_valid6));
 
endmodule
 
module Complete_on_write(reset , clk , Dw_iba_i,ram_oe,ram_we,Completed_ram_do,same_DW_read,complete_Ack);
 
     input reset, clk, ram_oe, ram_we;
     input [31:0] Dw_iba_i;
     output [31:0] Completed_ram_do;
     output complete_Ack;
     input  [2:0] same_DW_read;
     reg [31:0] Completed_ram_do  ;
     reg [31:0] delay_data_unit_1 , delay_data_unit_2;
      initial  delay_data_unit_1 = 32'h0;
      initial  delay_data_unit_2 = 32'h0;
 
     assign complete_Ack = 1;
 
    // fsm replacement trial version
       reg xor_data;
       always @ (posedge clk)
       begin
 
            delay_data_unit_1<=Dw_iba_i;
            delay_data_unit_2<=delay_data_unit_1;
            xor_data <= |(delay_data_unit_1^Dw_iba_i);
 
           end
 
            reg [3:0] fsm_cycle;
       initial fsm_cycle =0 ;
       always @ (posedge clk)
       begin
           case (fsm_cycle)
               3'h0: begin
                  Completed_ram_do <= delay_data_unit_1;
                  if (ram_we==1)
                     begin
                       fsm_cycle = 1;
                     end
                  end
               3'h1: begin
                        fsm_cycle = 2;
                        Completed_ram_do <= delay_data_unit_2;
                        end
               3'h2: begin fsm_cycle = 3; end
               3'h3: begin fsm_cycle = 4; end
               3'h4: begin fsm_cycle = 5; end
               3'h5: begin fsm_cycle = 6; end
               3'h6: begin fsm_cycle = 7; end
               3'h7: begin fsm_cycle = 0; end
           endcase
       end
 
endmodule
   /* this unit should return
      1. full packets by DPQ request - ram_do________________________________________
      2. header only to dcp - header_out   |___ 32 bit_-Dmac | length|start addr|
      3. how to distinct in start addrs ?   every time it toggle ??
       start_length   {length 8bit  , start_adrr 8bit }
      */
      module mem_basic_unit(reset , clk , Dw_iba_i , ram_do,StartFrm,EndFrm , header_to_dcp,start_length, transmit_done,adr_valid);   //add done from iba to dpq
 
        input StartFrm,EndFrm;
        input reset, clk;
        input [31:0] Dw_iba_i;
        input [15:0] start_length;
        input adr_valid;         // from dpq - request to release that addr
        output transmit_done;    // tell DPQ transmission completed for last request
        output [31:0] ram_do,header_to_dcp;
       wire  ram_ce , complete_Ack;
       reg   ram_oe , tst_reg;
       reg  ram_we, ram_we_pre,ram_oe_pre , headers_2_dcp_en , dmac_en;
       reg [7:0]   ram_addr ,w_ram_addr ;
       reg [31:0] Dmac_header,Dmac_header1 , header_to_dcp;
       wire [31:0] ram_do1 ;
       reg [7:0] header_out_length , header_out_start_addr, input_length , counter_length ;
       reg [2:0] same_DW_read_cnt , same_DW_free_cnt ;
       reg [3:0] fsm_state, counter_modulu8_fsm;
       reg transmit_done, increment_same_DW;
       reg read_arguments_valid, read_valid , div_2_clk,div_4_clk;
       reg ipg_out_mem;   // this bit indicate when we can start read again from mem.
       assign ram_ce = 1;
       //  assign  ram_do = Dw1_iba_i;
        initial begin
           ram_addr =0;
           w_ram_addr=0;
           header_out_length=0;
           counter_length=0;
           header_out_start_addr=0;
           dmac_en=1;
           transmit_done=0;
           read_arguments_valid=0;
           div_2_clk =0;
            div_4_clk =0;
            same_DW_read_cnt=0;
            ram_oe=0;
            increment_same_DW=0;
            same_DW_free_cnt = 0;
            ipg_out_mem = 0;
            fsm_state = 0;
            read_valid=0;
            counter_modulu8_fsm=0;
         end
        reg [31:0] prev_input, xor_data ;
       always @ (posedge clk)
       begin
         div_2_clk = clk^div_2_clk;
         prev_input <= Dw_iba_i;
 
         ram_we <= |(prev_input^Dw_iba_i); //ram_we pulse every word change
         ram_oe <= (~|(prev_input^Dw_iba_i));
 
 
         end
 
       always @(posedge StartFrm)
       begin
          headers_2_dcp_en = 0;
          header_out_length = 0;
        end
        always @ (negedge ram_we)
        begin
           header_out_length=header_out_length+1;
        end
        always @ (posedge EndFrm)
        begin
           headers_2_dcp_en=1;
           dmac_en=1;
        end
     //complete mem output upon write to mem interupts  
     Complete_on_write complete_on_write1(.reset(reset),.clk(clk),.Dw_iba_i(ram_do1),.ram_oe(ram_oe),.ram_we(ram_we),.Completed_ram_do(ram_do),.complete_Ack(complete_Ack),.same_DW_read(same_DW_read_cnt));
     //   | 32bit dmac | 16 bit dmac | 8 bit length| 8 bit start addr|
       //Go into write interval 
       always @ (posedge ram_we)    //write interval
        begin
            w_ram_addr = w_ram_addr +1;              //need better management on free mem when can write?
            ram_addr = w_ram_addr;
            if (header_out_length==0)
                begin
                    header_out_start_addr=ram_addr; //mark start_addr for dcp
                    Dmac_header=Dw_iba_i;           //take dmac for header to dcp
                 end
            if (header_out_length==1)
                begin
                    Dmac_header1=Dw_iba_i;        //take dmac for header to dcp
                 end
            if (headers_2_dcp_en==1 && dmac_en==1)
                begin
                 header_to_dcp=Dmac_header;
                 dmac_en=0;
                end
                else if(headers_2_dcp_en==1 && dmac_en==0)
                    begin
                      header_to_dcp={Dmac_header1[31:16],header_out_length,header_out_start_addr};
                       headers_2_dcp_en=0;
                        dmac_en=1;
                     end    else  header_to_dcp=0;
        end
 
        // when ram_we go down we move back to read cycle.
        always @ (negedge   ram_we)
        begin
 
             if (  adr_valid ==1)
                 begin
                   ram_addr =  start_length[7:0] + counter_length;
                  end
                  else
                  begin
                      ram_addr = 8'hzz;
                  end
         end
 
 
 
 
 
            //arguments are valid from DPQ . can start with reading from iba
        always @ (posedge adr_valid)
          begin
               counter_modulu8_fsm=0 ;
            end
 
        always @( posedge clk)
         begin
 
             same_DW_free_cnt <= same_DW_free_cnt + 1;
             if ( ram_oe == 1 && adr_valid ==1)
               begin
                     same_DW_read_cnt = same_DW_read_cnt + 1;
                     if (same_DW_read_cnt == 1 )
                         begin
                          increment_same_DW=1;
                          ipg_out_mem = 1;
                         end
               end
 
        end
 
        always @(posedge clk)
         begin
             case (counter_modulu8_fsm)
                 3'h0: begin
                     if (read_arguments_valid == 1)
                         begin
                              counter_modulu8_fsm = 1;
                            //  counter_length <= counter_length + 1;
                          end
                     end
 
                  3'h1: begin
                     if (read_arguments_valid == 1)
                           counter_length = counter_length + 1;
                         begin
                              counter_modulu8_fsm = 2;
                              ram_addr =  start_length[7:0] + counter_length -1;
                          end
                     end
 
                3'h2: begin
                    if (read_arguments_valid == 1)
                        begin
                             counter_modulu8_fsm = 3;
                         end
                    end
 
                 3'h3: begin
                    if (read_arguments_valid == 1)
                        begin
                             counter_modulu8_fsm = 4;
                         end
                    end
                   3'h4: begin
                      if (read_arguments_valid == 1)
                          begin
                               counter_modulu8_fsm = 5;
                           end
                      end
 
                 3'h5: begin
                     if (read_arguments_valid == 1)
                         begin
                              counter_modulu8_fsm = 6;
                          end
                     end
 
                  3'h6: begin
                     if (read_arguments_valid == 1)
                         begin
                              counter_modulu8_fsm = 7;
                          end
                     end
 
                   3'h7: begin
                     if (read_arguments_valid == 1)
                         begin
                              counter_modulu8_fsm = 0;
                          end
                     end
 
             endcase
         end
 
        //fsm new
        always @(posedge clk)
        begin
          case (fsm_state)
              3'h0: begin            //  not started
                     transmit_done = 0;
                     counter_length = 0;
                    if (adr_valid == 1)
                        begin
                            fsm_state = 1;
 
                            read_arguments_valid =1;
                        end
                  end
              3'h1: begin            //  transmitting
                    transmit_done = 0;
 
                     if (same_DW_free_cnt == 0)
                         begin
 
                         end
                    if (ram_addr ==start_length[15:8]+start_length[7:0] )
                       begin
                          read_arguments_valid =0;
                          increment_same_DW=0;
                          fsm_state = 2;
                        end
                    end
              3'h2: begin            //  pending1
                      transmit_done = 1;
                      fsm_state = 3;
                    end
               3'h3: begin            //  pending2
                      transmit_done = 1;
                      fsm_state = 4;
                    end
 
              3'h4: begin            //  pending3
                      transmit_done = 1;
                      fsm_state = 0;
 
                   //     end
                    end
 
          endcase
        end
 
 
 
        eth_spram_256x32
             mem1
             (
              .clk     (~clk),
              .rst     (reset),
              .ce      (ram_ce),                                                                                         // Chip enable input, active high   
              .we      ({ram_we & complete_Ack,ram_we & complete_Ack,ram_we & complete_Ack,ram_we & complete_Ack}),      // Write enable input, active high  
              .oe      (ram_oe),                                                                                         // Output enable input, active high 
              .addr    (ram_addr),                                                                                       // address bus inputs               
              .di      (Dw_iba_i),                                                                                      // input data bus                   
              .dato    (ram_do1)                                                                                        // output data bus                
        `ifdef ETH_BIST
              ,
              .mbist_si_i       (0),
              .mbist_so_o       (0),
              .mbist_ctrl_i       (0)
        `endif
              );
 
 
 
endmodule

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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [iba_modules.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ranm11
2			`/*****************************************************************************/`
3			`// Id ..........iba_modules.v //`
4			`// Author.......Ran Minerbi //`
5			`// //`
6			`// Unit Description : //`
7			`// iba collect frames from physical layer. //`
8			`// Keeps payload of frames that received //`
9			`// And haven't been sent yet. //`
10			`// Iba save a copy of the payload and send //`
11			`// Packet descriptors to dcp unit. //`
12			`// Iba send frames to XBar upon receiving //`
13			`// READY signal from dpq module. //`
14			`// // //`
15			`// //`
16			`/*****************************************************************************/`
17
18
19			`module mem_units(reset,clk,Dw1_iba_i,mem_u_o1,headers_o1,start_length1,StartFrm1,EndFrm1,transmit_done1,adr_valid1,`
20			`Dw2_iba_i,mem_u_o2,headers_o2,start_length2,StartFrm2,EndFrm2,transmit_done2,adr_valid2,`
21			`Dw3_iba_i,mem_u_o3,headers_o3,start_length3,StartFrm3,EndFrm3,transmit_done3,adr_valid3,`
22			`Dw4_iba_i,mem_u_o4,headers_o4,start_length4,StartFrm4,EndFrm4,transmit_done4,adr_valid4,`
23			`Dw5_iba_i,mem_u_o5,headers_o5,start_length5,StartFrm5,EndFrm5,transmit_done5,adr_valid5,`
24			`Dw6_iba_i,mem_u_o6,headers_o6,start_length6,StartFrm6,EndFrm6,transmit_done6,adr_valid6`
25
26			`);`
27
28			`input reset, clk,StartFrm1,EndFrm1,`
29			`StartFrm2,EndFrm2,`
30			`StartFrm3,EndFrm3,`
31			`StartFrm4,EndFrm4,`
32			`StartFrm5,EndFrm5,`
33			`StartFrm6,EndFrm6;`
34			`output transmit_done1,`
35			`transmit_done2,`
36			`transmit_done3,`
37			`transmit_done4,`
38			`transmit_done5,`
39			`transmit_done6;`
40			`input [31:0] Dw1_iba_i,Dw2_iba_i,Dw3_iba_i,Dw4_iba_i,Dw5_iba_i,Dw6_iba_i;`
41			`output [31:0] mem_u_o1,mem_u_o2,mem_u_o3,mem_u_o4,mem_u_o5,mem_u_o6;`
42			`output [31:0] headers_o1,headers_o2,headers_o3,headers_o4,headers_o5,headers_o6;`
43			`input [15:0] start_length1,start_length2,start_length3,start_length4,start_length5,start_length6;//from DPQ`
44			`input adr_valid1,adr_valid2,adr_valid3,adr_valid4,adr_valid5,adr_valid6;`
45			`mem_basic_unit basic_mem1(.reset(reset),.clk(clk),.Dw_iba_i(Dw1_iba_i),.ram_do(mem_u_o1),.StartFrm(StartFrm1),.EndFrm(EndFrm1),.header_to_dcp(headers_o1),.start_length(start_length1),.transmit_done(transmit_done1),.adr_valid(adr_valid1));`
46			`mem_basic_unit basic_mem2(.reset(reset),.clk(clk),.Dw_iba_i(Dw2_iba_i),.ram_do(mem_u_o2),.StartFrm(StartFrm2),.EndFrm(EndFrm2),.header_to_dcp(headers_o2),.start_length(start_length2),.transmit_done(transmit_done2),.adr_valid(adr_valid2));`
47			`mem_basic_unit basic_mem3(.reset(reset),.clk(clk),.Dw_iba_i(Dw3_iba_i),.ram_do(mem_u_o3),.StartFrm(StartFrm3),.EndFrm(EndFrm3),.header_to_dcp(headers_o3),.start_length(start_length3),.transmit_done(transmit_done3),.adr_valid(adr_valid3));`
48			`mem_basic_unit basic_mem4(.reset(reset),.clk(clk),.Dw_iba_i(Dw4_iba_i),.ram_do(mem_u_o4),.StartFrm(StartFrm4),.EndFrm(EndFrm4),.header_to_dcp(headers_o4),.start_length(start_length4),.transmit_done(transmit_done4),.adr_valid(adr_valid4));`
49			`mem_basic_unit basic_mem5(.reset(reset),.clk(clk),.Dw_iba_i(Dw5_iba_i),.ram_do(mem_u_o5),.StartFrm(StartFrm5),.EndFrm(EndFrm5),.header_to_dcp(headers_o5),.start_length(start_length5),.transmit_done(transmit_done5),.adr_valid(adr_valid5));`
50			`mem_basic_unit basic_mem6(.reset(reset),.clk(clk),.Dw_iba_i(Dw6_iba_i),.ram_do(mem_u_o6),.StartFrm(StartFrm6),.EndFrm(EndFrm6),.header_to_dcp(headers_o6),.start_length(start_length6),.transmit_done(transmit_done6),.adr_valid(adr_valid6));`
51
52			`endmodule`
53
54			`module Complete_on_write(reset , clk , Dw_iba_i,ram_oe,ram_we,Completed_ram_do,same_DW_read,complete_Ack);`
55
56			`input reset, clk, ram_oe, ram_we;`
57			`input [31:0] Dw_iba_i;`
58			`output [31:0] Completed_ram_do;`
59			`output complete_Ack;`
60			`input [2:0] same_DW_read;`
61			`reg [31:0] Completed_ram_do ;`
62			`reg [31:0] delay_data_unit_1 , delay_data_unit_2;`
63			`initial delay_data_unit_1 = 32'h0;`
64			`initial delay_data_unit_2 = 32'h0;`
65
66			`assign complete_Ack = 1;`
67
68			`// fsm replacement trial version`
69			`reg xor_data;`
70			`always @ (posedge clk)`
71			`begin`
72
73			`delay_data_unit_1<=Dw_iba_i;`
74			`delay_data_unit_2<=delay_data_unit_1;`
75			`xor_data <= \|(delay_data_unit_1^Dw_iba_i);`
76
77			`end`
78
79			`reg [3:0] fsm_cycle;`
80			`initial fsm_cycle =0 ;`
81			`always @ (posedge clk)`
82			`begin`
83			`case (fsm_cycle)`
84			`3'h0: begin`
85			`Completed_ram_do <= delay_data_unit_1;`
86			`if (ram_we==1)`
87			`begin`
88			`fsm_cycle = 1;`
89			`end`
90			`end`
91			`3'h1: begin`
92			`fsm_cycle = 2;`
93			`Completed_ram_do <= delay_data_unit_2;`
94			`end`
95			`3'h2: begin fsm_cycle = 3; end`
96			`3'h3: begin fsm_cycle = 4; end`
97			`3'h4: begin fsm_cycle = 5; end`
98			`3'h5: begin fsm_cycle = 6; end`
99			`3'h6: begin fsm_cycle = 7; end`
100			`3'h7: begin fsm_cycle = 0; end`
101			`endcase`
102			`end`
103
104			`endmodule`
105			`/* this unit should return`
106			`1. full packets by DPQ request - ram_do________________________________________`
107			`2. header only to dcp - header_out \|___ 32 bit_-Dmac \| length\|start addr\|`
108			`3. how to distinct in start addrs ? every time it toggle ??`
109			`start_length {length 8bit , start_adrr 8bit }`
110			`*/`
111			`module mem_basic_unit(reset , clk , Dw_iba_i , ram_do,StartFrm,EndFrm , header_to_dcp,start_length, transmit_done,adr_valid); //add done from iba to dpq`
112
113			`input StartFrm,EndFrm;`
114			`input reset, clk;`
115			`input [31:0] Dw_iba_i;`
116			`input [15:0] start_length;`
117			`input adr_valid; // from dpq - request to release that addr`
118			`output transmit_done; // tell DPQ transmission completed for last request`
119			`output [31:0] ram_do,header_to_dcp;`
120			`wire ram_ce , complete_Ack;`
121			`reg ram_oe , tst_reg;`
122			`reg ram_we, ram_we_pre,ram_oe_pre , headers_2_dcp_en , dmac_en;`
123			`reg [7:0] ram_addr ,w_ram_addr ;`
124			`reg [31:0] Dmac_header,Dmac_header1 , header_to_dcp;`
125			`wire [31:0] ram_do1 ;`
126			`reg [7:0] header_out_length , header_out_start_addr, input_length , counter_length ;`
127			`reg [2:0] same_DW_read_cnt , same_DW_free_cnt ;`
128			`reg [3:0] fsm_state, counter_modulu8_fsm;`
129			`reg transmit_done, increment_same_DW;`
130			`reg read_arguments_valid, read_valid , div_2_clk,div_4_clk;`
131			`reg ipg_out_mem; // this bit indicate when we can start read again from mem.`
132			`assign ram_ce = 1;`
133			`// assign ram_do = Dw1_iba_i;`
134			`initial begin`
135			`ram_addr =0;`
136			`w_ram_addr=0;`
137			`header_out_length=0;`
138			`counter_length=0;`
139			`header_out_start_addr=0;`
140			`dmac_en=1;`
141			`transmit_done=0;`
142			`read_arguments_valid=0;`
143			`div_2_clk =0;`
144			`div_4_clk =0;`
145			`same_DW_read_cnt=0;`
146			`ram_oe=0;`
147			`increment_same_DW=0;`
148			`same_DW_free_cnt = 0;`
149			`ipg_out_mem = 0;`
150			`fsm_state = 0;`
151			`read_valid=0;`
152			`counter_modulu8_fsm=0;`
153			`end`
154			`reg [31:0] prev_input, xor_data ;`
155			`always @ (posedge clk)`
156			`begin`
157			`div_2_clk = clk^div_2_clk;`
158			`prev_input <= Dw_iba_i;`
159
160			`ram_we <= \|(prev_input^Dw_iba_i); //ram_we pulse every word change`
161			`ram_oe <= (~\|(prev_input^Dw_iba_i));`
162
163
164			`end`
165
166			`always @(posedge StartFrm)`
167			`begin`
168			`headers_2_dcp_en = 0;`
169			`header_out_length = 0;`
170			`end`
171			`always @ (negedge ram_we)`
172			`begin`
173			`header_out_length=header_out_length+1;`
174			`end`
175			`always @ (posedge EndFrm)`
176			`begin`
177			`headers_2_dcp_en=1;`
178			`dmac_en=1;`
179			`end`
180			`//complete mem output upon write to mem interupts`
181			`Complete_on_write complete_on_write1(.reset(reset),.clk(clk),.Dw_iba_i(ram_do1),.ram_oe(ram_oe),.ram_we(ram_we),.Completed_ram_do(ram_do),.complete_Ack(complete_Ack),.same_DW_read(same_DW_read_cnt));`
182			`// \| 32bit dmac \| 16 bit dmac \| 8 bit length\| 8 bit start addr\|`
183			`//Go into write interval`
184			`always @ (posedge ram_we) //write interval`
185			`begin`
186			`w_ram_addr = w_ram_addr +1; //need better management on free mem when can write?`
187			`ram_addr = w_ram_addr;`
188			`if (header_out_length==0)`
189			`begin`
190			`header_out_start_addr=ram_addr; //mark start_addr for dcp`
191			`Dmac_header=Dw_iba_i; //take dmac for header to dcp`
192			`end`
193			`if (header_out_length==1)`
194			`begin`
195			`Dmac_header1=Dw_iba_i; //take dmac for header to dcp`
196			`end`
197			`if (headers_2_dcp_en==1 && dmac_en==1)`
198			`begin`
199			`header_to_dcp=Dmac_header;`
200			`dmac_en=0;`
201			`end`
202			`else if(headers_2_dcp_en==1 && dmac_en==0)`
203			`begin`
204			`header_to_dcp={Dmac_header1[31:16],header_out_length,header_out_start_addr};`
205			`headers_2_dcp_en=0;`
206			`dmac_en=1;`
207			`end else header_to_dcp=0;`
208			`end`
209
210			`// when ram_we go down we move back to read cycle.`
211			`always @ (negedge ram_we)`
212			`begin`
213
214			`if ( adr_valid ==1)`
215			`begin`
216			`ram_addr = start_length[7:0] + counter_length;`
217			`end`
218			`else`
219			`begin`
220			`ram_addr = 8'hzz;`
221			`end`
222			`end`
223
224
225
226
227
228			`//arguments are valid from DPQ . can start with reading from iba`
229			`always @ (posedge adr_valid)`
230			`begin`
231			`counter_modulu8_fsm=0 ;`
232			`end`
233
234			`always @( posedge clk)`
235			`begin`
236
237			`same_DW_free_cnt <= same_DW_free_cnt + 1;`
238			`if ( ram_oe == 1 && adr_valid ==1)`
239			`begin`
240			`same_DW_read_cnt = same_DW_read_cnt + 1;`
241			`if (same_DW_read_cnt == 1 )`
242			`begin`
243			`increment_same_DW=1;`
244			`ipg_out_mem = 1;`
245			`end`
246			`end`
247
248			`end`
249
250			`always @(posedge clk)`
251			`begin`
252			`case (counter_modulu8_fsm)`
253			`3'h0: begin`
254			`if (read_arguments_valid == 1)`
255			`begin`
256			`counter_modulu8_fsm = 1;`
257			`// counter_length <= counter_length + 1;`
258			`end`
259			`end`
260
261			`3'h1: begin`
262			`if (read_arguments_valid == 1)`
263			`counter_length = counter_length + 1;`
264			`begin`
265			`counter_modulu8_fsm = 2;`
266			`ram_addr = start_length[7:0] + counter_length -1;`
267			`end`
268			`end`
269
270			`3'h2: begin`
271			`if (read_arguments_valid == 1)`
272			`begin`
273			`counter_modulu8_fsm = 3;`
274			`end`
275			`end`
276
277			`3'h3: begin`
278			`if (read_arguments_valid == 1)`
279			`begin`
280			`counter_modulu8_fsm = 4;`
281			`end`
282			`end`
283			`3'h4: begin`
284			`if (read_arguments_valid == 1)`
285			`begin`
286			`counter_modulu8_fsm = 5;`
287			`end`
288			`end`
289
290			`3'h5: begin`
291			`if (read_arguments_valid == 1)`
292			`begin`
293			`counter_modulu8_fsm = 6;`
294			`end`
295			`end`
296
297			`3'h6: begin`
298			`if (read_arguments_valid == 1)`
299			`begin`
300			`counter_modulu8_fsm = 7;`
301			`end`
302			`end`
303
304			`3'h7: begin`
305			`if (read_arguments_valid == 1)`
306			`begin`
307			`counter_modulu8_fsm = 0;`
308			`end`
309			`end`
310
311			`endcase`
312			`end`
313
314			`//fsm new`
315			`always @(posedge clk)`
316			`begin`
317			`case (fsm_state)`
318			`3'h0: begin // not started`
319			`transmit_done = 0;`
320			`counter_length = 0;`
321			`if (adr_valid == 1)`
322			`begin`
323			`fsm_state = 1;`
324
325			`read_arguments_valid =1;`
326			`end`
327			`end`
328			`3'h1: begin // transmitting`
329			`transmit_done = 0;`
330
331			`if (same_DW_free_cnt == 0)`
332			`begin`
333
334			`end`
335			`if (ram_addr ==start_length[15:8]+start_length[7:0] )`
336			`begin`
337			`read_arguments_valid =0;`
338			`increment_same_DW=0;`
339			`fsm_state = 2;`
340			`end`
341			`end`
342			`3'h2: begin // pending1`
343			`transmit_done = 1;`
344			`fsm_state = 3;`
345			`end`
346			`3'h3: begin // pending2`
347			`transmit_done = 1;`
348			`fsm_state = 4;`
349			`end`
350
351			`3'h4: begin // pending3`
352			`transmit_done = 1;`
353			`fsm_state = 0;`
354
355			`// end`
356			`end`
357
358			`endcase`
359			`end`
360
361
362
363			`eth_spram_256x32`
364			`mem1`
365			`(`
366			`.clk (~clk),`
367			`.rst (reset),`
368			`.ce (ram_ce), // Chip enable input, active high`
369			`.we ({ram_we & complete_Ack,ram_we & complete_Ack,ram_we & complete_Ack,ram_we & complete_Ack}), // Write enable input, active high`
370			`.oe (ram_oe), // Output enable input, active high`
371			`.addr (ram_addr), // address bus inputs`
372			`.di (Dw_iba_i), // input data bus`
373			`.dato (ram_do1) // output data bus`
374			`ifdef ETH_BIST
375			`,`
376			`.mbist_si_i (0),`
377			`.mbist_so_o (0),`
378			`.mbist_ctrl_i (0)`
379			`endif
380			`);`
381
382
383
384			`endmodule`