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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [iba_modules.v] - Blame information for rev 3

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/*****************************************************************************/
// Id ..........iba_modules.v                                                 //
// Author.......Ran Minerbi                                                   //
//                                                                            //
//   Unit Description   :                                                     //
//    iba collect  frames from physical layer.                                //
//    Keeps payload of frames that received                                   //
//    And haven't been sent yet.                                              //
//    Iba save a copy of the payload and send                                 //
//    Packet descriptors to dcp unit.                                         //
//    Iba send frames to XBar upon receiving                                  //
//    READY signal from dpq module.                                           //
//                                                                            //                                                                        //
//                                                                            //
/*****************************************************************************/
 
 
module mem_units(reset,clk,Dw1_iba_i,mem_u_o1,headers_o1,start_length1,StartFrm1,EndFrm1,transmit_done1,adr_valid1,
                           Dw2_iba_i,mem_u_o2,headers_o2,start_length2,StartFrm2,EndFrm2,transmit_done2,adr_valid2,
                           Dw3_iba_i,mem_u_o3,headers_o3,start_length3,StartFrm3,EndFrm3,transmit_done3,adr_valid3,
                           Dw4_iba_i,mem_u_o4,headers_o4,start_length4,StartFrm4,EndFrm4,transmit_done4,adr_valid4,
                           Dw5_iba_i,mem_u_o5,headers_o5,start_length5,StartFrm5,EndFrm5,transmit_done5,adr_valid5,
                           Dw6_iba_i,mem_u_o6,headers_o6,start_length6,StartFrm6,EndFrm6,transmit_done6,adr_valid6
 
                 );
 
   input reset, clk,StartFrm1,EndFrm1,
                    StartFrm2,EndFrm2,
                    StartFrm3,EndFrm3,
                    StartFrm4,EndFrm4,
                    StartFrm5,EndFrm5,
                    StartFrm6,EndFrm6;
            output  transmit_done1,
                    transmit_done2,
                    transmit_done3,
                    transmit_done4,
                    transmit_done5,
                    transmit_done6;
   input [31:0] Dw1_iba_i,Dw2_iba_i,Dw3_iba_i,Dw4_iba_i,Dw5_iba_i,Dw6_iba_i;
   output [31:0] mem_u_o1,mem_u_o2,mem_u_o3,mem_u_o4,mem_u_o5,mem_u_o6;
   output [31:0] headers_o1,headers_o2,headers_o3,headers_o4,headers_o5,headers_o6;
   input [15:0] start_length1,start_length2,start_length3,start_length4,start_length5,start_length6;//from DPQ
   input adr_valid1,adr_valid2,adr_valid3,adr_valid4,adr_valid5,adr_valid6;
   mem_basic_unit basic_mem1(.reset(reset),.clk(clk),.Dw_iba_i(Dw1_iba_i),.ram_do(mem_u_o1),.StartFrm(StartFrm1),.EndFrm(EndFrm1),.header_to_dcp(headers_o1),.start_length(start_length1),.transmit_done(transmit_done1),.adr_valid(adr_valid1));
   mem_basic_unit basic_mem2(.reset(reset),.clk(clk),.Dw_iba_i(Dw2_iba_i),.ram_do(mem_u_o2),.StartFrm(StartFrm2),.EndFrm(EndFrm2),.header_to_dcp(headers_o2),.start_length(start_length2),.transmit_done(transmit_done2),.adr_valid(adr_valid2));
   mem_basic_unit basic_mem3(.reset(reset),.clk(clk),.Dw_iba_i(Dw3_iba_i),.ram_do(mem_u_o3),.StartFrm(StartFrm3),.EndFrm(EndFrm3),.header_to_dcp(headers_o3),.start_length(start_length3),.transmit_done(transmit_done3),.adr_valid(adr_valid3));
   mem_basic_unit basic_mem4(.reset(reset),.clk(clk),.Dw_iba_i(Dw4_iba_i),.ram_do(mem_u_o4),.StartFrm(StartFrm4),.EndFrm(EndFrm4),.header_to_dcp(headers_o4),.start_length(start_length4),.transmit_done(transmit_done4),.adr_valid(adr_valid4));
   mem_basic_unit basic_mem5(.reset(reset),.clk(clk),.Dw_iba_i(Dw5_iba_i),.ram_do(mem_u_o5),.StartFrm(StartFrm5),.EndFrm(EndFrm5),.header_to_dcp(headers_o5),.start_length(start_length5),.transmit_done(transmit_done5),.adr_valid(adr_valid5));
   mem_basic_unit basic_mem6(.reset(reset),.clk(clk),.Dw_iba_i(Dw6_iba_i),.ram_do(mem_u_o6),.StartFrm(StartFrm6),.EndFrm(EndFrm6),.header_to_dcp(headers_o6),.start_length(start_length6),.transmit_done(transmit_done6),.adr_valid(adr_valid6));
 
endmodule
 
module Complete_on_write(reset , clk , Dw_iba_i,ram_oe,ram_we,Completed_ram_do,same_DW_read,addr_valid);
 
     input reset, clk, ram_oe, ram_we;
     input [31:0] Dw_iba_i;
     output [31:0] Completed_ram_do;
     input  [2:0] same_DW_read;
     input  addr_valid;
     reg [31:0] Completed_ram_do  ;
     reg [31:0] delay_data_unit_1 , delay_data_unit_2;
      initial begin
        delay_data_unit_1 = 32'h0;
        delay_data_unit_2 = 32'h0;
        xor_data = 0;
        cnt_fsm = 0;
        clk_cnt = 0;
     end
       reg xor_data;
     //this blk to solve the read mem with unvalid ram_addr 
       always @ (posedge clk)
       begin
        if (addr_valid == 1)
            begin
                delay_data_unit_1 <= Dw_iba_i;
                delay_data_unit_2<=delay_data_unit_1;
                xor_data <= |(delay_data_unit_1^Dw_iba_i);
            end
         else
            begin
                delay_data_unit_1 = 0;
                delay_data_unit_2 = 0;
            end
       end
     //  
            reg [7:0]clk_cnt;
            reg [1:0]cnt_fsm;
            always @(posedge clk)
             begin
               case (cnt_fsm)
                    2'h0: begin
                             if (xor_data ==1)
                                begin
                                    cnt_fsm = 1;
                                    clk_cnt = 0;
                                end
                          end
                    2'h1: begin
                            clk_cnt = clk_cnt+1;
                            if (xor_data == 1)
                              begin
                                 clk_cnt = 0;
                              end
                           end
                endcase
             end
 
            reg [3:0] fsm_cycle;
       initial fsm_cycle =0 ;
       always @ (posedge clk)
       begin
           case (fsm_cycle)
               3'h0: begin
                  Completed_ram_do <= delay_data_unit_1;
                  if (ram_we==1)
                     begin
                       fsm_cycle = 1;
                     end
                  end
               3'h1: begin
                        fsm_cycle = 2;
                        Completed_ram_do <= delay_data_unit_2;
                        end
               3'h2: begin fsm_cycle = 3; end
               3'h3: begin fsm_cycle = 4; end
               3'h4: begin fsm_cycle = 5; end
               3'h5: begin fsm_cycle = 6; end
               3'h6: begin fsm_cycle = 7; end
               3'h7: begin fsm_cycle = 0; end
           endcase
       end
 
endmodule
   /* this unit should return
      1. full packets by DPQ request - ram_do________________________________________
      2. header only to dcp - header_out   |___ 32 bit_-Dmac | length|start addr|
      3. how to distinct in start addrs ?   every time it toggle ??
       start_length   {length 8bit  , start_adrr 8bit }
      */
      module mem_basic_unit(reset , clk , Dw_iba_i , ram_do,StartFrm,EndFrm , header_to_dcp,start_length, transmit_done,adr_valid);   //add done from iba to dpq
 
        input StartFrm,EndFrm;
        input reset, clk;
        input [31:0] Dw_iba_i;
        input [15:0] start_length;
        input adr_valid;         // from dpq - request to release that addr
        output transmit_done;    // tell DPQ transmission completed for last request
        output [31:0] ram_do,header_to_dcp;
       wire  ram_ce ;
       reg   ram_oe , tst_reg;
       reg  ram_we, ram_we_pre,ram_oe_pre , headers_2_dcp_en , dmac_en;
       reg [7:0]   ram_addr ,w_ram_addr ;
       reg [31:0] Dmac_header,Dmac_header1 , header_to_dcp;
       wire [31:0] ram_do1 ;
       reg [7:0] header_out_length , header_out_start_addr, input_length , counter_length ;
       reg [2:0] same_DW_read_cnt , same_DW_free_cnt ;
       reg [3:0] fsm_state, counter_modulu8_fsm;
       reg transmit_done, increment_same_DW;
       reg read_arguments_valid,read_argumets_valid_delay_unit1,read_argumets_valid_delay_unit2, read_valid , div_2_clk,div_4_clk;
       reg ipg_out_mem;   // this bit indicate when we can start read again from mem.
       assign ram_ce = 1;
       //  assign  ram_do = Dw1_iba_i;
        initial begin
           ram_addr =0;
           w_ram_addr=0;
           header_out_length=0;
           counter_length=0;
           header_out_start_addr=0;
           dmac_en=1;
           transmit_done=0;
           read_arguments_valid=0;
           div_2_clk =0;
            div_4_clk =0;
            same_DW_read_cnt=0;
            ram_oe=0;
            increment_same_DW=0;
            same_DW_free_cnt = 0;
            ipg_out_mem = 0;
            fsm_state = 0;
            read_valid=0;
            counter_modulu8_fsm=0;
         end
        reg [31:0] prev_input, xor_data ;
       always @ (posedge clk)
       begin
         div_2_clk = clk^div_2_clk;
         prev_input <= Dw_iba_i;
 
         ram_we <= |(prev_input^Dw_iba_i); //ram_we pulse every word change
         ram_oe <= (~|(prev_input^Dw_iba_i)) & read_argumets_valid_delay_unit2;
         read_argumets_valid_delay_unit1 <= read_arguments_valid;
         read_argumets_valid_delay_unit2 <=read_argumets_valid_delay_unit1;
         end
 
       always @(posedge StartFrm)
       begin
          headers_2_dcp_en = 0;
          header_out_length = 0;
        end
        always @ (negedge ram_we)
        begin
           header_out_length=header_out_length+1;
        end
        always @ (posedge EndFrm)
        begin
           headers_2_dcp_en=1;
           dmac_en=1;
        end
     //complete mem output upon write to mem interupts  
     Complete_on_write complete_on_write1(.reset(reset),.clk(clk),.Dw_iba_i(ram_do1),.ram_oe(ram_oe),.ram_we(ram_we),.Completed_ram_do(ram_do),.same_DW_read(same_DW_read_cnt),.addr_valid(read_argumets_valid_delay_unit2));
     //   | 32bit dmac | 16 bit dmac | 8 bit length| 8 bit start addr|
       //Go into write interval 
       always @ (posedge ram_we)    //write interval
        begin
            w_ram_addr = w_ram_addr +1;              //need better management on free mem when can write?
            ram_addr = w_ram_addr;
            if (header_out_length==0)
                begin
                    header_out_start_addr=ram_addr; //mark start_addr for dcp
                    Dmac_header=Dw_iba_i;           //take dmac for header to dcp
                 end
            if (header_out_length==1)
                begin
                    Dmac_header1=Dw_iba_i;        //take dmac for header to dcp
                 end
            if (headers_2_dcp_en==1 && dmac_en==1)
                begin
                 header_to_dcp=Dmac_header;
                 dmac_en=0;
                end
                else if(headers_2_dcp_en==1 && dmac_en==0)
                    begin
                      header_to_dcp={Dmac_header1[31:16],header_out_length,header_out_start_addr};
                       headers_2_dcp_en=0;
                        dmac_en=1;
                     end    else  header_to_dcp=0;
        end
 
        // when ram_we go down we move back to read cycle.
        always @ (negedge   ram_we)
        begin
 
             if (  adr_valid ==1)
                 begin
                   ram_addr =  start_length[7:0] + counter_length;
                  end
                  else
                  begin
                      ram_addr = 8'hzz;
                  end
         end
 
 
 
 
 
            //arguments are valid from DPQ . can start with reading from iba
        always @ (posedge adr_valid)
          begin
               counter_modulu8_fsm=0 ;
            end
 
        always @( posedge clk)
         begin
 
             same_DW_free_cnt <= same_DW_free_cnt + 1;
             if ( ram_oe == 1 && adr_valid ==1)
               begin
                     same_DW_read_cnt = same_DW_read_cnt + 1;
                     if (same_DW_read_cnt == 1 )
                         begin
                          increment_same_DW=1;
                          ipg_out_mem = 1;
                         end
               end
 
        end
 
        always @(posedge clk)
         begin
             case (counter_modulu8_fsm)
                 3'h0: begin
                     if (read_arguments_valid == 1)
                         begin
                              counter_modulu8_fsm = 1;
                            //  counter_length <= counter_length + 1;
                          end
                     end
 
                  3'h1: begin
                     if (read_arguments_valid == 1)
                           counter_length = counter_length + 1;
                         begin
                              counter_modulu8_fsm = 2;
                              ram_addr =  start_length[7:0] + counter_length -1;
                          end
                     end
 
                3'h2: begin
                    if (read_arguments_valid == 1)
                        begin
                             counter_modulu8_fsm = 3;
                         end
                    end
 
                 3'h3: begin
                    if (read_arguments_valid == 1)
                        begin
                             counter_modulu8_fsm = 4;
                         end
                    end
                   3'h4: begin
                      if (read_arguments_valid == 1)
                          begin
                               counter_modulu8_fsm = 5;
                           end
                      end
 
                 3'h5: begin
                     if (read_arguments_valid == 1)
                         begin
                              counter_modulu8_fsm = 6;
                          end
                     end
 
                  3'h6: begin
                     if (read_arguments_valid == 1)
                         begin
                              counter_modulu8_fsm = 7;
                          end
                     end
 
                   3'h7: begin
                     if (read_arguments_valid == 1)
                         begin
                              counter_modulu8_fsm = 0;
                          end
                     end
 
             endcase
         end
 
        //fsm new
        always @(posedge clk)
        begin
          case (fsm_state)
              3'h0: begin            //  not started
                     transmit_done = 0;
                     counter_length = 0;
                    if (adr_valid == 1)
                        begin
                            fsm_state = 1;
 
                            read_arguments_valid =1;
                        end
                  end
              3'h1: begin            //  transmitting
                    transmit_done = 0;
 
                     if (same_DW_free_cnt == 0)
                         begin
 
                         end
                    if (ram_addr ==start_length[15:8]+start_length[7:0] )
                       begin
                          read_arguments_valid =0;
                          increment_same_DW=0;
                          fsm_state = 2;
                        end
                    end
              3'h2: begin            //  pending1
                      transmit_done = 1;
                      fsm_state = 3;
                    end
               3'h3: begin            //  pending2
                      transmit_done = 1;
                      fsm_state = 4;
                    end
 
              3'h4: begin            //  pending3
                      transmit_done = 1;
                      fsm_state = 0;
 
                   //     end
                    end
 
          endcase
        end
 
 
 
        eth_spram_256x32
             mem1
             (
              .clk     (~clk),
              .rst     (reset),
              .ce      (ram_ce),                                                                                         // Chip enable input, active high   
              .we      ({ram_we ,ram_we ,ram_we,ram_we }),      // Write enable input, active high  
              .oe      (ram_oe),                                                                                         // Output enable input, active high 
              .addr    (ram_addr),                                                                                       // address bus inputs               
              .di      (Dw_iba_i),                                                                                      // input data bus                   
              .dato    (ram_do1)                                                                                        // output data bus                
        `ifdef ETH_BIST
              ,
              .mbist_si_i       (0),
              .mbist_so_o       (0),
              .mbist_ctrl_i       (0)
        `endif
              );
 
 
 
endmodule

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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [iba_modules.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	ranm11
2			`/*****************************************************************************/`
3			`// Id ..........iba_modules.v //`
4			`// Author.......Ran Minerbi //`
5			`// //`
6			`// Unit Description : //`
7			`// iba collect frames from physical layer. //`
8			`// Keeps payload of frames that received //`
9			`// And haven't been sent yet. //`
10			`// Iba save a copy of the payload and send //`
11			`// Packet descriptors to dcp unit. //`
12			`// Iba send frames to XBar upon receiving //`
13			`// READY signal from dpq module. //`
14			`// // //`
15			`// //`
16			`/*****************************************************************************/`
17
18
19			`module mem_units(reset,clk,Dw1_iba_i,mem_u_o1,headers_o1,start_length1,StartFrm1,EndFrm1,transmit_done1,adr_valid1,`
20			`Dw2_iba_i,mem_u_o2,headers_o2,start_length2,StartFrm2,EndFrm2,transmit_done2,adr_valid2,`
21			`Dw3_iba_i,mem_u_o3,headers_o3,start_length3,StartFrm3,EndFrm3,transmit_done3,adr_valid3,`
22			`Dw4_iba_i,mem_u_o4,headers_o4,start_length4,StartFrm4,EndFrm4,transmit_done4,adr_valid4,`
23			`Dw5_iba_i,mem_u_o5,headers_o5,start_length5,StartFrm5,EndFrm5,transmit_done5,adr_valid5,`
24			`Dw6_iba_i,mem_u_o6,headers_o6,start_length6,StartFrm6,EndFrm6,transmit_done6,adr_valid6`
25
26			`);`
27
28			`input reset, clk,StartFrm1,EndFrm1,`
29			`StartFrm2,EndFrm2,`
30			`StartFrm3,EndFrm3,`
31			`StartFrm4,EndFrm4,`
32			`StartFrm5,EndFrm5,`
33			`StartFrm6,EndFrm6;`
34			`output transmit_done1,`
35			`transmit_done2,`
36			`transmit_done3,`
37			`transmit_done4,`
38			`transmit_done5,`
39			`transmit_done6;`
40			`input [31:0] Dw1_iba_i,Dw2_iba_i,Dw3_iba_i,Dw4_iba_i,Dw5_iba_i,Dw6_iba_i;`
41			`output [31:0] mem_u_o1,mem_u_o2,mem_u_o3,mem_u_o4,mem_u_o5,mem_u_o6;`
42			`output [31:0] headers_o1,headers_o2,headers_o3,headers_o4,headers_o5,headers_o6;`
43			`input [15:0] start_length1,start_length2,start_length3,start_length4,start_length5,start_length6;//from DPQ`
44			`input adr_valid1,adr_valid2,adr_valid3,adr_valid4,adr_valid5,adr_valid6;`
45			`mem_basic_unit basic_mem1(.reset(reset),.clk(clk),.Dw_iba_i(Dw1_iba_i),.ram_do(mem_u_o1),.StartFrm(StartFrm1),.EndFrm(EndFrm1),.header_to_dcp(headers_o1),.start_length(start_length1),.transmit_done(transmit_done1),.adr_valid(adr_valid1));`
46			`mem_basic_unit basic_mem2(.reset(reset),.clk(clk),.Dw_iba_i(Dw2_iba_i),.ram_do(mem_u_o2),.StartFrm(StartFrm2),.EndFrm(EndFrm2),.header_to_dcp(headers_o2),.start_length(start_length2),.transmit_done(transmit_done2),.adr_valid(adr_valid2));`
47			`mem_basic_unit basic_mem3(.reset(reset),.clk(clk),.Dw_iba_i(Dw3_iba_i),.ram_do(mem_u_o3),.StartFrm(StartFrm3),.EndFrm(EndFrm3),.header_to_dcp(headers_o3),.start_length(start_length3),.transmit_done(transmit_done3),.adr_valid(adr_valid3));`
48			`mem_basic_unit basic_mem4(.reset(reset),.clk(clk),.Dw_iba_i(Dw4_iba_i),.ram_do(mem_u_o4),.StartFrm(StartFrm4),.EndFrm(EndFrm4),.header_to_dcp(headers_o4),.start_length(start_length4),.transmit_done(transmit_done4),.adr_valid(adr_valid4));`
49			`mem_basic_unit basic_mem5(.reset(reset),.clk(clk),.Dw_iba_i(Dw5_iba_i),.ram_do(mem_u_o5),.StartFrm(StartFrm5),.EndFrm(EndFrm5),.header_to_dcp(headers_o5),.start_length(start_length5),.transmit_done(transmit_done5),.adr_valid(adr_valid5));`
50			`mem_basic_unit basic_mem6(.reset(reset),.clk(clk),.Dw_iba_i(Dw6_iba_i),.ram_do(mem_u_o6),.StartFrm(StartFrm6),.EndFrm(EndFrm6),.header_to_dcp(headers_o6),.start_length(start_length6),.transmit_done(transmit_done6),.adr_valid(adr_valid6));`
51
52			`endmodule`
53
54	3	ranm11	`module Complete_on_write(reset , clk , Dw_iba_i,ram_oe,ram_we,Completed_ram_do,same_DW_read,addr_valid);`
55	2	ranm11
56			`input reset, clk, ram_oe, ram_we;`
57			`input [31:0] Dw_iba_i;`
58			`output [31:0] Completed_ram_do;`
59			`input [2:0] same_DW_read;`
60	3	ranm11	`input addr_valid;`
61	2	ranm11	`reg [31:0] Completed_ram_do ;`
62			`reg [31:0] delay_data_unit_1 , delay_data_unit_2;`
63	3	ranm11	`initial begin`
64			`delay_data_unit_1 = 32'h0;`
65			`delay_data_unit_2 = 32'h0;`
66			`xor_data = 0;`
67			`cnt_fsm = 0;`
68			`clk_cnt = 0;`
69			`end`
70	2	ranm11	`reg xor_data;`
71	3	ranm11	`//this blk to solve the read mem with unvalid ram_addr`
72	2	ranm11	`always @ (posedge clk)`
73			`begin`
74	3	ranm11	`if (addr_valid == 1)`
75			`begin`
76			`delay_data_unit_1 <= Dw_iba_i;`
77			`delay_data_unit_2<=delay_data_unit_1;`
78			`xor_data <= \|(delay_data_unit_1^Dw_iba_i);`
79			`end`
80			`else`
81			`begin`
82			`delay_data_unit_1 = 0;`
83			`delay_data_unit_2 = 0;`
84			`end`
85			`end`
86			`//`
87			`reg [7:0]clk_cnt;`
88			`reg [1:0]cnt_fsm;`
89			`always @(posedge clk)`
90			`begin`
91			`case (cnt_fsm)`
92			`2'h0: begin`
93			`if (xor_data ==1)`
94			`begin`
95			`cnt_fsm = 1;`
96			`clk_cnt = 0;`
97			`end`
98			`end`
99			`2'h1: begin`
100			`clk_cnt = clk_cnt+1;`
101			`if (xor_data == 1)`
102			`begin`
103			`clk_cnt = 0;`
104			`end`
105			`end`
106			`endcase`
107			`end`
108
109	2	ranm11	`reg [3:0] fsm_cycle;`
110			`initial fsm_cycle =0 ;`
111			`always @ (posedge clk)`
112			`begin`
113			`case (fsm_cycle)`
114			`3'h0: begin`
115			`Completed_ram_do <= delay_data_unit_1;`
116			`if (ram_we==1)`
117			`begin`
118			`fsm_cycle = 1;`
119			`end`
120			`end`
121			`3'h1: begin`
122			`fsm_cycle = 2;`
123			`Completed_ram_do <= delay_data_unit_2;`
124			`end`
125			`3'h2: begin fsm_cycle = 3; end`
126			`3'h3: begin fsm_cycle = 4; end`
127			`3'h4: begin fsm_cycle = 5; end`
128			`3'h5: begin fsm_cycle = 6; end`
129			`3'h6: begin fsm_cycle = 7; end`
130			`3'h7: begin fsm_cycle = 0; end`
131			`endcase`
132			`end`
133
134			`endmodule`
135			`/* this unit should return`
136			`1. full packets by DPQ request - ram_do________________________________________`
137			`2. header only to dcp - header_out \|___ 32 bit_-Dmac \| length\|start addr\|`
138			`3. how to distinct in start addrs ? every time it toggle ??`
139			`start_length {length 8bit , start_adrr 8bit }`
140			`*/`
141			`module mem_basic_unit(reset , clk , Dw_iba_i , ram_do,StartFrm,EndFrm , header_to_dcp,start_length, transmit_done,adr_valid); //add done from iba to dpq`
142
143			`input StartFrm,EndFrm;`
144			`input reset, clk;`
145			`input [31:0] Dw_iba_i;`
146			`input [15:0] start_length;`
147			`input adr_valid; // from dpq - request to release that addr`
148			`output transmit_done; // tell DPQ transmission completed for last request`
149			`output [31:0] ram_do,header_to_dcp;`
150	3	ranm11	`wire ram_ce ;`
151	2	ranm11	`reg ram_oe , tst_reg;`
152			`reg ram_we, ram_we_pre,ram_oe_pre , headers_2_dcp_en , dmac_en;`
153			`reg [7:0] ram_addr ,w_ram_addr ;`
154			`reg [31:0] Dmac_header,Dmac_header1 , header_to_dcp;`
155			`wire [31:0] ram_do1 ;`
156			`reg [7:0] header_out_length , header_out_start_addr, input_length , counter_length ;`
157			`reg [2:0] same_DW_read_cnt , same_DW_free_cnt ;`
158			`reg [3:0] fsm_state, counter_modulu8_fsm;`
159			`reg transmit_done, increment_same_DW;`
160	3	ranm11	`reg read_arguments_valid,read_argumets_valid_delay_unit1,read_argumets_valid_delay_unit2, read_valid , div_2_clk,div_4_clk;`
161	2	ranm11	`reg ipg_out_mem; // this bit indicate when we can start read again from mem.`
162			`assign ram_ce = 1;`
163			`// assign ram_do = Dw1_iba_i;`
164			`initial begin`
165			`ram_addr =0;`
166			`w_ram_addr=0;`
167			`header_out_length=0;`
168			`counter_length=0;`
169			`header_out_start_addr=0;`
170			`dmac_en=1;`
171			`transmit_done=0;`
172			`read_arguments_valid=0;`
173			`div_2_clk =0;`
174			`div_4_clk =0;`
175			`same_DW_read_cnt=0;`
176			`ram_oe=0;`
177			`increment_same_DW=0;`
178			`same_DW_free_cnt = 0;`
179			`ipg_out_mem = 0;`
180			`fsm_state = 0;`
181			`read_valid=0;`
182			`counter_modulu8_fsm=0;`
183			`end`
184			`reg [31:0] prev_input, xor_data ;`
185			`always @ (posedge clk)`
186			`begin`
187			`div_2_clk = clk^div_2_clk;`
188			`prev_input <= Dw_iba_i;`
189
190			`ram_we <= \|(prev_input^Dw_iba_i); //ram_we pulse every word change`
191	3	ranm11	`ram_oe <= (~\|(prev_input^Dw_iba_i)) & read_argumets_valid_delay_unit2;`
192			`read_argumets_valid_delay_unit1 <= read_arguments_valid;`
193			`read_argumets_valid_delay_unit2 <=read_argumets_valid_delay_unit1;`
194	2	ranm11	`end`
195
196			`always @(posedge StartFrm)`
197			`begin`
198			`headers_2_dcp_en = 0;`
199			`header_out_length = 0;`
200			`end`
201			`always @ (negedge ram_we)`
202			`begin`
203			`header_out_length=header_out_length+1;`
204			`end`
205			`always @ (posedge EndFrm)`
206			`begin`
207			`headers_2_dcp_en=1;`
208			`dmac_en=1;`
209			`end`
210			`//complete mem output upon write to mem interupts`
211	3	ranm11	`Complete_on_write complete_on_write1(.reset(reset),.clk(clk),.Dw_iba_i(ram_do1),.ram_oe(ram_oe),.ram_we(ram_we),.Completed_ram_do(ram_do),.same_DW_read(same_DW_read_cnt),.addr_valid(read_argumets_valid_delay_unit2));`
212	2	ranm11	`// \| 32bit dmac \| 16 bit dmac \| 8 bit length\| 8 bit start addr\|`
213			`//Go into write interval`
214			`always @ (posedge ram_we) //write interval`
215			`begin`
216			`w_ram_addr = w_ram_addr +1; //need better management on free mem when can write?`
217			`ram_addr = w_ram_addr;`
218			`if (header_out_length==0)`
219			`begin`
220			`header_out_start_addr=ram_addr; //mark start_addr for dcp`
221			`Dmac_header=Dw_iba_i; //take dmac for header to dcp`
222			`end`
223			`if (header_out_length==1)`
224			`begin`
225			`Dmac_header1=Dw_iba_i; //take dmac for header to dcp`
226			`end`
227			`if (headers_2_dcp_en==1 && dmac_en==1)`
228			`begin`
229			`header_to_dcp=Dmac_header;`
230			`dmac_en=0;`
231			`end`
232			`else if(headers_2_dcp_en==1 && dmac_en==0)`
233			`begin`
234			`header_to_dcp={Dmac_header1[31:16],header_out_length,header_out_start_addr};`
235			`headers_2_dcp_en=0;`
236			`dmac_en=1;`
237			`end else header_to_dcp=0;`
238			`end`
239
240			`// when ram_we go down we move back to read cycle.`
241			`always @ (negedge ram_we)`
242			`begin`
243
244			`if ( adr_valid ==1)`
245			`begin`
246			`ram_addr = start_length[7:0] + counter_length;`
247			`end`
248			`else`
249			`begin`
250			`ram_addr = 8'hzz;`
251			`end`
252			`end`
253
254
255
256
257
258			`//arguments are valid from DPQ . can start with reading from iba`
259			`always @ (posedge adr_valid)`
260			`begin`
261			`counter_modulu8_fsm=0 ;`
262			`end`
263
264			`always @( posedge clk)`
265			`begin`
266
267			`same_DW_free_cnt <= same_DW_free_cnt + 1;`
268			`if ( ram_oe == 1 && adr_valid ==1)`
269			`begin`
270			`same_DW_read_cnt = same_DW_read_cnt + 1;`
271			`if (same_DW_read_cnt == 1 )`
272			`begin`
273			`increment_same_DW=1;`
274			`ipg_out_mem = 1;`
275			`end`
276			`end`
277
278			`end`
279
280			`always @(posedge clk)`
281			`begin`
282			`case (counter_modulu8_fsm)`
283			`3'h0: begin`
284			`if (read_arguments_valid == 1)`
285			`begin`
286			`counter_modulu8_fsm = 1;`
287			`// counter_length <= counter_length + 1;`
288			`end`
289			`end`
290
291			`3'h1: begin`
292			`if (read_arguments_valid == 1)`
293			`counter_length = counter_length + 1;`
294			`begin`
295			`counter_modulu8_fsm = 2;`
296			`ram_addr = start_length[7:0] + counter_length -1;`
297			`end`
298			`end`
299
300			`3'h2: begin`
301			`if (read_arguments_valid == 1)`
302			`begin`
303			`counter_modulu8_fsm = 3;`
304			`end`
305			`end`
306
307			`3'h3: begin`
308			`if (read_arguments_valid == 1)`
309			`begin`
310			`counter_modulu8_fsm = 4;`
311			`end`
312			`end`
313			`3'h4: begin`
314			`if (read_arguments_valid == 1)`
315			`begin`
316			`counter_modulu8_fsm = 5;`
317			`end`
318			`end`
319
320			`3'h5: begin`
321			`if (read_arguments_valid == 1)`
322			`begin`
323			`counter_modulu8_fsm = 6;`
324			`end`
325			`end`
326
327			`3'h6: begin`
328			`if (read_arguments_valid == 1)`
329			`begin`
330			`counter_modulu8_fsm = 7;`
331			`end`
332			`end`
333
334			`3'h7: begin`
335			`if (read_arguments_valid == 1)`
336			`begin`
337			`counter_modulu8_fsm = 0;`
338			`end`
339			`end`
340
341			`endcase`
342			`end`
343
344			`//fsm new`
345			`always @(posedge clk)`
346			`begin`
347			`case (fsm_state)`
348			`3'h0: begin // not started`
349			`transmit_done = 0;`
350			`counter_length = 0;`
351			`if (adr_valid == 1)`
352			`begin`
353			`fsm_state = 1;`
354
355			`read_arguments_valid =1;`
356			`end`
357			`end`
358			`3'h1: begin // transmitting`
359			`transmit_done = 0;`
360
361			`if (same_DW_free_cnt == 0)`
362			`begin`
363
364			`end`
365			`if (ram_addr ==start_length[15:8]+start_length[7:0] )`
366			`begin`
367			`read_arguments_valid =0;`
368			`increment_same_DW=0;`
369			`fsm_state = 2;`
370			`end`
371			`end`
372			`3'h2: begin // pending1`
373			`transmit_done = 1;`
374			`fsm_state = 3;`
375			`end`
376			`3'h3: begin // pending2`
377			`transmit_done = 1;`
378			`fsm_state = 4;`
379			`end`
380
381			`3'h4: begin // pending3`
382			`transmit_done = 1;`
383			`fsm_state = 0;`
384
385			`// end`
386			`end`
387
388			`endcase`
389			`end`
390
391
392
393			`eth_spram_256x32`
394			`mem1`
395			`(`
396			`.clk (~clk),`
397			`.rst (reset),`
398			`.ce (ram_ce), // Chip enable input, active high`
399	3	ranm11	`.we ({ram_we ,ram_we ,ram_we,ram_we }), // Write enable input, active high`
400	2	ranm11	`.oe (ram_oe), // Output enable input, active high`
401			`.addr (ram_addr), // address bus inputs`
402			`.di (Dw_iba_i), // input data bus`
403			`.dato (ram_do1) // output data bus`
404			`ifdef ETH_BIST
405			`,`
406			`.mbist_si_i (0),`
407			`.mbist_so_o (0),`
408			`.mbist_ctrl_i (0)`
409			`endif
410			`);`
411
412
413
414			`endmodule`