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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [plu_moduls.v] - Blame information for rev 2

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/*****************************************************************************/
4
// Id ..........plu_modules.v                                                 //
5
// Author.......Ran Minerbi                                                   //
6
//                                                                            //
7
//   Unit Description   :                                                     //
8
//     plu is the physical layer.                                             //
9
//     Usually implemented as analog SerDes.                                  //
10
//     The unit Serialize the frames on transmission                          //
11
//     And De-Serialize on receive.                                           //
12
                                                                              //
13
/*****************************************************************************/
14
 
15
 
16
 
17
 
18
module nibble_2_word(reset,clk , pi1 , Tx7in ,RxStartFrm_out , RxEndFrm_out);
19
 
20
 
21
  input  reset , clk;
22
  input  [3:0] pi1;
23
  output [7:0] Tx7in;
24
  output   RxStartFrm_out ,  RxEndFrm_out ;
25
  initial begin
26
   ControlFrmAddressOK = 0;
27
 // Tx7in=0;
28
  end
29
   //out regs Rxs
30
  reg Rx_1_Valid ,ControlFrmAddressOK;
31
  reg  [3:0] pi1_1 , pi1_2, pi1_3;
32
 // wire  [7:0] Tx7in;
33
  wire [7:0] RxData;
34
  wire [15:0] RxByteCnt;
35
  wire [1:0] RxStateData;
36
  wire   RxValid ,RxStartFrm ,RxEndFrm ,RxByteCntEq0,RxByteCntGreat2 ,RxByteCntMaxFrame,RxCrcError,RxStateIdle,RxStatePreamble,RxStateSFD ,RxAbort ,AddressMiss ;
37
 
38
 
39
   always @ (posedge clk or posedge reset)
40
   begin
41
       if (reset)
42
           begin
43
         //     pi1_w = 0;
44
          //    pi2_w = 0;
45
            end
46
           else
47
            begin
48
             pi1_1 <= pi1;
49
             pi1_2 <= pi1_1;
50
             pi1_3 <= pi1_2;
51
             Rx_1_Valid =|( pi1| pi1_1 | pi1_2| pi1_3);
52
            end
53
   end
54
 
55
 
56
   eth_rxethmac rxethmac1          //need to duplicate 6 time
57
(
58
  .MRxClk(clk),
59
  .MRxDV(Rx_1_Valid),
60
  .MRxD(pi1),
61
  .Transmitting(1'b0),
62
  .HugEn(1'b0),
63
  .DlyCrcEn(1'b0),
64
  .MaxFL(32'h0600),
65
  .r_IFG(1'b1),
66
  .Reset(reset),
67
  .RxData(Tx7in),
68
  .RxValid(RxValid),
69
  .RxStartFrm(RxStartFrm_out),
70
  .RxEndFrm(RxEndFrm_out),
71
  .ByteCnt(RxByteCnt),
72
  .ByteCntEq0(RxByteCntEq0),
73
  .ByteCntGreat2(RxByteCntGreat2),
74
  .ByteCntMaxFrame(RxByteCntMaxFrame),
75
  .CrcError(RxCrcError),
76
  .StateIdle(RxStateIdle),
77
  .StatePreamble(RxStatePreamble),
78
  .StateSFD(RxStateSFD),
79
  .StateData(RxStateData),
80
  .MAC(48'h0),
81
  .r_Pro(1'b1),
82
  .r_Bro(1'b1),
83
  .r_HASH0(32'h0),
84
  .r_HASH1(32'h0),
85
  .RxAbort(RxAbort),
86
  .AddressMiss(AddressMiss),
87
  .PassAll(1'b1),
88
  .ControlFrmAddressOK(ControlFrmAddressOK)
89
);
90
 
91
 
92
 
93
 
94
endmodule
95
 
96
 
97
 
98
 
99
module plu_serdes(reset,clk , pi1 , po1 ,RxStartFrm_out , RxEndFrm_out);
100
 
101
  input  reset , clk;
102
  input  [3:0] pi1;
103
  output [3:0] po1;
104
  output   RxStartFrm_out ,  RxEndFrm_out ;
105
  initial  ControlFrmAddressOK = 0;
106
 
107
   //out regs Rxs
108
  reg Rx_1_Valid ,ControlFrmAddressOK;
109
  reg  [3:0] pi1_1 , pi1_2, pi1_3;
110
  wire [7:0] RxData;
111
  wire [15:0] RxByteCnt;
112
  wire [1:0] RxStateData;
113
  wire   RxValid ,RxStartFrm ,RxEndFrm ,RxByteCntEq0,RxByteCntGreat2 ,RxByteCntMaxFrame,RxCrcError,RxStateIdle,RxStatePreamble,RxStateSFD ,RxAbort ,AddressMiss ;
114
 
115
 
116
   always @ (posedge clk or posedge reset)
117
   begin
118
       if (reset)
119
           begin
120
         //     pi1_w = 0;
121
          //    pi2_w = 0;
122
            end
123
           else
124
            begin
125
             pi1_1 <= pi1;
126
             pi1_2 <= pi1_1;
127
             pi1_3 <= pi1_2;
128
             Rx_1_Valid =|( pi1| pi1_1 | pi1_2| pi1_3);
129
            end
130
   end
131
 
132
 
133
   eth_rxethmac rxethmac1          //need to duplicate 6 time
134
(
135
  .MRxClk(clk),
136
  .MRxDV(Rx_1_Valid),
137
  .MRxD(pi1),
138
  .Transmitting(1'b0),
139
  .HugEn(1'b0),
140
  .DlyCrcEn(1'b0),
141
  .MaxFL(32'h0600),
142
  .r_IFG(1'b1),
143
  .Reset(reset),
144
  .RxData(RxData),
145
  .RxValid(RxValid),
146
  .RxStartFrm(RxStartFrm),
147
  .RxEndFrm(RxEndFrm),
148
  .ByteCnt(RxByteCnt),
149
  .ByteCntEq0(RxByteCntEq0),
150
  .ByteCntGreat2(RxByteCntGreat2),
151
  .ByteCntMaxFrame(RxByteCntMaxFrame),
152
  .CrcError(RxCrcError),
153
  .StateIdle(RxStateIdle),
154
  .StatePreamble(RxStatePreamble),
155
  .StateSFD(RxStateSFD),
156
  .StateData(RxStateData),
157
  .MAC(48'h0),
158
  .r_Pro(1'b1),
159
  .r_Bro(1'b1),
160
  .r_HASH0(32'h0),
161
  .r_HASH1(32'h0),
162
  .RxAbort(RxAbort),
163
  .AddressMiss(AddressMiss),
164
  .PassAll(1'b1),
165
  .ControlFrmAddressOK(ControlFrmAddressOK)
166
);
167
 
168
 //Tx 
169
   initial
170
  begin
171
     TxCarrierSense = 1'b0;
172
     TxUnderRun = 1'b0;
173
     for_under_run = 1'b0;
174
     // #7160   Rx_1_Valid = 1'b0;PadOut = 1;
175
     r_MinFL = 16'h0040;
176
     r_MaxFL = 16'h0600;
177
     CrcEnOut = 1;
178
     r_FullD =1;
179
     r_HugEn = 0;
180
     r_DlyCrcEn = 0;
181
     r_IPGT= 7'h12;
182
     r_IPGR1 = 7'hc;
183
     r_IPGR2 = 7'h12;
184
     r_CollValid = 6'h3f;
185
     r_MaxRet = 4'hf;
186
     r_NoBckof = 1'b0;
187
     r_ExDfrEn =1'b0;
188
     Collision <= 1'b0;
189
       #67027   Rx_1_Valid = 1'b1;
190
  end
191
  initial begin
192
      #74940   TxUnderRun = 1'b1;  //74940
193
      #360   TxUnderRun = 1'b0;
194
      #9960   TxUnderRun = 1'b1;   // 84240
195
      #360   TxUnderRun = 1'b0;
196
      #11400   TxUnderRun = 1'b1;    //96000
197
      #360   TxUnderRun = 1'b0;
198
      #10760   TxUnderRun = 1'b1;    //107120
199
      #360   TxUnderRun = 1'b0;
200
      #10840   TxUnderRun = 1'b1;    //107120
201
      #360   TxUnderRun = 1'b0;
202
 
203
 
204
      end
205
 
206
       always @ (posedge RxEndFrm)
207
           begin
208
             # 560 for_under_run = 1'b1;
209
              # 360 for_under_run = 1'b0;
210
           end
211
 
212
    reg   TxCarrierSense ,Collision,PadOut ,CrcEnOut,r_FullD ,r_HugEn,r_DlyCrcEn,r_ExDfrEn, r_NoBckof , TxUnderRun ,for_under_run ;
213
    reg [15:0] r_MinFL;
214
    reg [15:0] r_MaxFL;
215
    reg [6:0] r_IPGT ,r_IPGR1 ,r_IPGR2;
216
    reg [5:0] r_CollValid;
217
    reg [3:0] r_MaxRet;
218
    wire [3:0] RetryCnt;
219
    wire [1:0] StateData;
220
    wire [7:0] Tx7in;
221
    wire RxStartFrm_out ,RxEndFrm_out;
222
   StartFrmExtender Extender(.reset(reset),.clk(clk) , .in(RxData),.extOut(Tx7in) ,.RxStartFrm(RxStartFrm) ,.RxEndFrm(RxEndFrm),.RxStartFrm_out(RxStartFrm_out),.RxEndFrm_out(RxEndFrm_out) );
223
 
224
eth_txethmac txethmac1
225
(
226
  .MTxClk(clk),                      //
227
  .Reset(reset),                     //
228
  .CarrierSense(TxCarrierSense),     //
229
  .Collision(Collision),             //
230
  .TxData(Tx7in),                   //
231
  .TxStartFrm(RxStartFrm_out),           //
232
  .TxUnderRun(for_under_run),           //
233
  .TxEndFrm(RxEndFrm_out),               //
234
  .Pad(PadOut),                      //
235
  .MinFL(r_MinFL),                   //
236
  .CrcEn(CrcEnOut),                  //
237
  .FullD(r_FullD),                   //
238
  .HugEn(r_HugEn),                   //
239
  .DlyCrcEn(r_DlyCrcEn),             //
240
  .IPGT(r_IPGT),                     //
241
  .IPGR1(r_IPGR1),                   //
242
  .IPGR2(r_IPGR2),                   //
243
  .CollValid(r_CollValid),           //
244
  .MaxRet(r_MaxRet),                 //
245
  .NoBckof(r_NoBckof),               //
246
  .ExDfrEn(r_ExDfrEn),               //
247
  .MaxFL(r_MaxFL),                   //
248
  .MTxEn(mtxen_pad_o),
249
  .MTxD(po1),                        //  plu output [3:0]
250
  .MTxErr(mtxerr_pad_o),
251
  .TxUsedData(TxUsedDataIn),
252
  .TxDone(TxDoneIn),
253
  .TxRetry(TxRetry),
254
  .TxAbort(TxAbortIn),
255
  .WillTransmit(WillTransmit),
256
  .ResetCollision(ResetCollision),
257
  .RetryCnt(RetryCnt),               //
258
  .StartTxDone(StartTxDone),
259
  .StartTxAbort(StartTxAbort),
260
  .MaxCollisionOccured(MaxCollisionOccured),
261
  .LateCollision(LateCollision),
262
  .DeferIndication(DeferIndication),
263
  .StatePreamble(StatePreamble),
264
  .StateData(StateData)              //
265
);
266
 
267
 
268
 
269
 
270
 
271
endmodule
272
 
273
 
274
module word_2_nibble(reset,clk , po1 , RxData ,RxStartFrm , RxEndFrm);
275
 
276
    input  reset , clk;
277
  output  [3:0] po1;
278
  input [7:0] RxData;
279
  input   RxStartFrm ,  RxEndFrm ;
280
 
281
    //Tx 
282
   initial
283
  begin
284
     TxCarrierSense = 1'b0;
285
     TxUnderRun = 1'b0;
286
     for_under_run = 1'b0;
287
     r_MinFL = 16'h0040;
288
     r_MaxFL = 16'h0600;
289
     CrcEnOut = 1;
290
     r_FullD =1;
291
     r_HugEn = 0;
292
     r_DlyCrcEn = 0;
293
     r_IPGT= 7'h12;
294
     r_IPGR1 = 7'hc;
295
     r_IPGR2 = 7'h12;
296
     r_CollValid = 6'h3f;
297
     r_MaxRet = 4'hf;
298
     r_NoBckof = 1'b0;
299
     r_ExDfrEn =1'b0;
300
     Collision <= 1'b0;
301
    // RxStartFrm_out = 0;
302
 
303
  end
304
 
305
       always @ (posedge RxEndFrm)
306
           begin
307
             # 560 for_under_run = 1'b1;
308
              # 360 for_under_run = 1'b0;
309
           end
310
 
311
    reg   TxCarrierSense ,Collision,PadOut ,CrcEnOut,r_FullD ,r_HugEn,r_DlyCrcEn,r_ExDfrEn, r_NoBckof , TxUnderRun ,for_under_run ;
312
    reg [15:0] r_MinFL;
313
    reg [15:0] r_MaxFL;
314
    reg [6:0] r_IPGT ,r_IPGR1 ,r_IPGR2;
315
    reg [5:0] r_CollValid;
316
    reg [3:0] r_MaxRet;
317
    wire [3:0] RetryCnt;
318
    wire [1:0] StateData;
319
    wire [7:0] Tx7in;
320
    wire RxStartFrm ,RxEndFrm;
321
    wire RxStartFrm_out;
322
   StartFrmExtender Extender(.reset(reset),.clk(clk) , .in(RxData),.extOut(Tx7in) ,.RxStartFrm(RxStartFrm) ,.RxEndFrm(RxEndFrm),.RxStartFrm_out(RxStartFrm_out),.RxEndFrm_out(RxEndFrm_out) );
323
 
324
eth_txethmac txethmac1
325
(
326
  .MTxClk(clk),                      //
327
  .Reset(reset),                     //
328
  .CarrierSense(TxCarrierSense),     //
329
  .Collision(Collision),             //
330
  .TxData(Tx7in),                   //
331
  .TxStartFrm(RxStartFrm_out),           //
332
  .TxUnderRun(for_under_run),           //
333
  .TxEndFrm(RxEndFrm_out),               //
334
  .Pad(PadOut),                      //
335
  .MinFL(r_MinFL),                   //
336
  .CrcEn(CrcEnOut),                  //
337
  .FullD(r_FullD),                   //
338
  .HugEn(r_HugEn),                   //
339
  .DlyCrcEn(r_DlyCrcEn),             //
340
  .IPGT(r_IPGT),                     //
341
  .IPGR1(r_IPGR1),                   //
342
  .IPGR2(r_IPGR2),                   //
343
  .CollValid(r_CollValid),           //
344
  .MaxRet(r_MaxRet),                 //
345
  .NoBckof(r_NoBckof),               //
346
  .ExDfrEn(r_ExDfrEn),               //
347
  .MaxFL(r_MaxFL),                   //
348
  .MTxEn(mtxen_pad_o),
349
  .MTxD(po1),                        //  plu output [3:0]
350
  .MTxErr(mtxerr_pad_o),
351
  .TxUsedData(TxUsedDataIn),
352
  .TxDone(TxDoneIn),
353
  .TxRetry(TxRetry),
354
  .TxAbort(TxAbortIn),
355
  .WillTransmit(WillTransmit),
356
  .ResetCollision(ResetCollision),
357
  .RetryCnt(RetryCnt),               //
358
  .StartTxDone(StartTxDone),
359
  .StartTxAbort(StartTxAbort),
360
  .MaxCollisionOccured(MaxCollisionOccured),
361
  .LateCollision(LateCollision),
362
  .DeferIndication(DeferIndication),
363
  .StatePreamble(StatePreamble),
364
  .StateData(StateData)              //
365
  );
366
 
367
 
368
endmodule
369
 
370
 
371
module Dword_to_byte(reset,clk ,byte ,Dword , TxStartFrm , TxEndFrm ,TxStartFrm_0,TxEndFrm_1 );
372
 
373
    output [7:0] byte;
374
    input [31:0] Dword;
375
    input reset ,clk , TxStartFrm , TxEndFrm;
376
    output TxStartFrm_0 , TxEndFrm_1;
377
   // output TxStartFrm_ , TxEndFrm_;
378
     reg  clk_div2 ,clk_div4 ;
379
     reg [2:0] mod4;
380
     reg [1:0] mod4_;
381
     reg [7:0] byte;
382
     reg TxStartFrm_ , TxEndFrm_ ,TxStartFrm_1,TxStartFrm_2, start_en , start_en_ ,end_en , start_signal_detect;
383
     reg [9:0] counter;
384
     wire   TxStartFrm_0 , TxEndFrm_1;
385
     initial begin
386
         mod4=0;
387
         mod4_=0;
388
         counter =0;
389
         clk_div2=0;
390
         byte=0;
391
         clk_div4=0;
392
         start_en=0;
393
         TxStartFrm_1=0;
394
         TxStartFrm_2=0;
395
 
396
         end_en=0  ;
397
         start_en_=0;
398
         start_signal_detect=0;
399
         TxStartFrm_=0;
400
         end
401
 
402
      always @(posedge TxEndFrm )
403
        begin
404
            end_en<=1;
405
            mod4 <=0 ;
406
         end
407
      always @(posedge TxStartFrm )
408
        begin
409
           mod4_ <= 0;
410
           mod4 <= 0;
411
           counter=0;
412
          // start_en<=1;      //push simultaneously
413
           //clk_div2=1;
414
         end
415
 
416
     always @(posedge clk)
417
            begin
418
              clk_div2 <= clk^clk_div2;
419
              clk_div4 <= (~clk_div2)^clk_div4;
420
       /*    TxStartFrm_2<=TxStartFrm_1;
421
            TxStartFrm_<=(mod4_ ==2'b01)?TxStartFrm_:0;      */
422
            // TxEndFrm_1<=TxEndFrm_;        
423
             end
424
      assign  TxStartFrm_0=TxStartFrm_ & start_signal_detect & clk_div2;
425
      assign TxEndFrm_1 = end_en & (mod4==5);
426
      always @ (posedge clk_div2)
427
      begin
428
           TxEndFrm_<=(mod4==4)?(~clk_div2)&end_en:TxEndFrm;
429
           end_en<= (mod4==5)?0:end_en;
430
           mod4<=mod4+1;
431
          mod4_<=mod4_+1;
432
          start_signal_detect = |Dword;
433
          TxStartFrm_=start_signal_detect & clk_div2;
434
          if (start_signal_detect & clk_div2)
435
              begin
436
                  counter<=counter+1;
437
                  end
438
                  if (counter >0)
439
                      begin
440
                       TxStartFrm_ =0;
441
                      end
442
          case(mod4_)
443
 
444
            2'h0:  byte<= Dword[31:24] ;
445
            2'h1:  byte<= Dword[23:16] ;
446
            2'h2:  byte<= Dword[15:8] ;
447
            2'h3:  byte<= Dword[7:0] ;
448
          endcase
449
 
450
       end
451
 
452
    endmodule
453
 
454
 
455
module byte_to_Dword(reset,clk ,byte ,Dword , RxStartFrm_ ,RxEndFrm_);
456
   input [9:0] byte;
457
    output [31:0] Dword;
458
    input reset ,clk;
459
    output RxStartFrm_ ,RxEndFrm_;
460
     reg [31:0] Dword, Dword1;
461
     reg [1:0] mod4 , mod4_;
462
     reg [7:0] RxData;
463
     reg  RxStartFrm ,RxEndFrm, RxStartFrm_ ,RxEndFrm_ , signal_detect;
464
     reg  clk_div2 ,clk_div4 ,shift_start;
465
     initial  begin
466
     mod4 = 0;
467
     RxData =0 ; clk_div2 = 0 ; RxStartFrm=0 ;RxEndFrm=0;
468
     clk_div4=0 ; shift_start=0;
469
     Dword=0; Dword1=0;
470
     end
471
 
472
    always @(negedge clk_div2 )
473
    begin
474
 
475
 
476
                case(mod4_)
477
 
478
                2'h0:      Dword1[31:24] <= RxData;
479
                2'h1:      Dword1[23:16] <= RxData;
480
                2'h2:      Dword1[15:8]  <= RxData;
481
                2'h3:      Dword1[7:0]   <= RxData;
482
              endcase
483
                mod4 <= mod4 + 1;
484
     end
485
 
486
      always @(posedge clk)
487
          begin
488
              clk_div2 <= clk^clk_div2;
489
              mod4_<=mod4;
490
              clk_div4 <= clk_div2^clk_div4;
491
              RxStartFrm <= byte[1];
492
              RxEndFrm   <= byte[0];
493
              RxData <=  byte[9:2];
494
              RxStartFrm_ <= byte[1];
495
              RxEndFrm_   <= byte[0];
496
           end
497
 
498
      always @(posedge clk_div2)
499
          begin
500
              if (mod4==0)
501
                begin
502
                Dword<=Dword1;
503
                signal_detect=|Dword1;
504
           //     RxStartFrm =1;
505
                end
506
                if (mod4 == 3)
507
                 begin
508
              //      RxStartFrm_<= clk_div2; 
509
              //      RxEndFrm_<= clk_div2;
510
             //     RxStartFrm=0;
511
                    shift_start<=0;
512
                end else begin
513
               //      RxStartFrm=0;
514
                    end
515
 
516
           end
517
       always @ (posedge RxStartFrm )
518
              begin
519
                mod4 <= 0;
520
                shift_start<=1;
521
                clk_div2=1;
522
              end
523
 
524
 
525
endmodule
526
 
527
module word_to_Dword (reset,clk ,in1,in2,in3,in4,in5,in6,out1,out2,out3,out4,out5,out6,
528
                      RxStartFrm1 ,RxStartFrm2,RxStartFrm3,RxStartFrm4,RxStartFrm5,RxStartFrm6,
529
                      RxEndFrm1,RxEndFrm2,RxEndFrm3,RxEndFrm4,RxEndFrm5,RxEndFrm6
530
                      );
531
    input [9:0] in1,in2,in3,in4,in5,in6;
532
    output [31:0] out1,out2,out3,out4,out5,out6;
533
    input reset ,clk;
534
     output RxStartFrm1 ,RxStartFrm2,RxStartFrm3,RxStartFrm4,RxStartFrm5,RxStartFrm6;
535
     output RxEndFrm1,RxEndFrm2,RxEndFrm3,RxEndFrm4,RxEndFrm5,RxEndFrm6;
536
   byte_to_Dword  byte_to_Dword1(.reset(reset),.clk(clk) ,.byte(in1) ,.Dword(out1),.RxStartFrm_(RxStartFrm1) ,.RxEndFrm_(RxEndFrm1));
537
   byte_to_Dword  byte_to_Dword2(.reset(reset),.clk(clk) ,.byte(in2) ,.Dword(out2),.RxStartFrm_(RxStartFrm2) ,.RxEndFrm_(RxEndFrm2));
538
   byte_to_Dword  byte_to_Dword3(.reset(reset),.clk(clk) ,.byte(in3) ,.Dword(out3),.RxStartFrm_(RxStartFrm3) ,.RxEndFrm_(RxEndFrm3));
539
   byte_to_Dword  byte_to_Dword4(.reset(reset),.clk(clk) ,.byte(in4) ,.Dword(out4),.RxStartFrm_(RxStartFrm4) ,.RxEndFrm_(RxEndFrm4));
540
   byte_to_Dword  byte_to_Dword5(.reset(reset),.clk(clk) ,.byte(in5) ,.Dword(out5),.RxStartFrm_(RxStartFrm5) ,.RxEndFrm_(RxEndFrm5));
541
   byte_to_Dword  byte_to_Dword6(.reset(reset),.clk(clk) ,.byte(in6) ,.Dword(out6),.RxStartFrm_(RxStartFrm6) ,.RxEndFrm_(RxEndFrm6));
542
 
543
 
544
endmodule
545
 
546
module StartFrmExtender (reset,clk , in,extOut ,RxStartFrm ,RxEndFrm,RxStartFrm_out ,RxEndFrm_out );
547
   input  reset , clk ,RxStartFrm ,RxEndFrm;
548
   input [7:0] in;
549
   output [7:0] extOut ;
550
   output RxStartFrm_out ,RxEndFrm_out;
551
   reg [7:0] first_sample ;
552
   reg div_2_clk;
553
   reg [6:0] counter;
554
   reg [1:0] state;
555
   reg [7:0] extOut ;
556
   reg RxStartFrm_out ,RxEndFrm_out;
557
   reg write_fifo , read_fifo , TxFifoClear ;
558
   wire            TxBufferFull;
559
   wire            TxBufferAlmostFull;
560
   wire            TxBufferAlmostEmpty;
561
   wire            TxBufferEmpty;
562
   wire [7:0] queue_out;
563
   wire [4:0] txfifo_cnt;
564
    eth_fifo #(
565
           .DATA_WIDTH(8),
566
           .DEPTH(32),
567
           .CNT_WIDTH(5))
568
 ext_fifo (
569
         .clk            (~div_2_clk),
570
         .reset          (reset),
571
         // Inputs
572
         .data_in        (in),
573
         .write          (write_fifo),
574
         .read           (read_fifo),
575
         .clear          (TxFifoClear),
576
         // Outputs
577
         .data_out       (queue_out),
578
         .full           (TxBufferFull),
579
         .almost_full    (TxBufferAlmostFull),
580
         .almost_empty   (TxBufferAlmostEmpty),
581
         .empty          (TxBufferEmpty),
582
         .cnt            (txfifo_cnt)
583
        );
584
 
585
    initial begin
586
    div_2_clk=0;
587
    RxEndFrm_out = 0;
588
    read_fifo =0;
589
    RxStartFrm_out = 0;
590
  // #67800  write_fifo=1;
591
    end
592
 
593
   always @(posedge  RxStartFrm)
594
   begin
595
         div_2_clk=1;
596
       end
597
   always @ (posedge clk or posedge reset )
598
   begin
599
       if (reset)
600
           begin
601
             extOut <= 0;
602
            end
603
           else
604
            begin
605
               div_2_clk <= div_2_clk^clk;
606
            end
607
   end
608
   always @(negedge reset)
609
   begin
610
        RxStartFrm_out <= 0;
611
    end
612
 
613
   always @ (posedge clk)
614
          begin
615
              if (RxStartFrm)
616
               begin
617
                  counter=0;
618
                  first_sample <= in;
619
                  state <= 2'h0;
620
                  assign   write_fifo=1;
621
              end
622
 
623
              if (RxEndFrm)
624
              begin
625
                 assign  write_fifo=0;
626
                   state<=2'h2;
627
              end
628
      end //clk 
629
 
630
    always @(negedge RxStartFrm)      //negedge
631
     begin
632
         RxStartFrm_out <= 1;
633
     end
634
   always @ (posedge div_2_clk)
635
      begin
636
       counter <= counter + 1;
637
       if (counter < 7 & state ==0)
638
         begin
639
              extOut <= first_sample;
640
              assign   write_fifo=1;
641
              assign   read_fifo =0;
642
         end
643
       else if (counter>=7 & state ==0)
644
             begin
645
                 extOut <= queue_out;
646
                    RxStartFrm_out = 0;
647
              assign   write_fifo=1;
648
              assign   read_fifo =1;
649
             end
650
       else if (state ==2 & ~TxBufferEmpty)
651
           begin
652
              extOut <= queue_out;
653
            assign  write_fifo=0;
654
            assign  read_fifo =1;
655
           end
656
        else if (state ==2 & TxBufferEmpty)
657
            begin
658
               extOut <= in;
659
             assign  write_fifo=0;
660
             assign  read_fifo =0;
661
             state <= 2'h3;
662
             assign TxFifoClear = 1;
663
             assign RxEndFrm_out = 1;
664
            end
665
            else if (state == 3)
666
                begin
667
                    assign TxFifoClear = 0;
668
                    assign RxEndFrm_out = 0;
669
                end
670
 
671
      end
672
 
673
 
674
endmodule
675
 

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