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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [plu_moduls.v] - Blame information for rev 4

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/*****************************************************************************/
// Id ..........plu_modules.v                                                 //
// Author.......Ran Minerbi                                                   //
//                                                                            //
//   Unit Description   :                                                     //
//     plu is the physical layer.                                             //
//     Usually implemented as analog SerDes.                                  //
//     The unit Serialize the frames on transmission                          //
//     And De-Serialize on receive.                                           //
                                                                              //
/*****************************************************************************/
 
 
 
 
module nibble_2_word(reset,clk , pi1 , Tx7in ,RxStartFrm_out , RxEndFrm_out);
 
 
  input  reset , clk;
  input  [3:0] pi1;
  output [7:0] Tx7in;
  output   RxStartFrm_out ,  RxEndFrm_out ;
  initial begin
   ControlFrmAddressOK = 0;
 // Tx7in=0;
  end
   //out regs Rxs
  reg Rx_1_Valid ,ControlFrmAddressOK;
  reg  [3:0] pi1_1 , pi1_2, pi1_3;
 // wire  [7:0] Tx7in;
  wire [7:0] RxData;
  wire [15:0] RxByteCnt;
  wire [1:0] RxStateData;
  wire   RxValid ,RxStartFrm ,RxEndFrm ,RxByteCntEq0,RxByteCntGreat2 ,RxByteCntMaxFrame,RxCrcError,RxStateIdle,RxStatePreamble,RxStateSFD ,RxAbort ,AddressMiss ;
 
 
   always @ (posedge clk or posedge reset)
   begin
       if (reset)
           begin
         //     pi1_w = 0;
          //    pi2_w = 0;
            end
           else
            begin
             pi1_1 <= pi1;
             pi1_2 <= pi1_1;
             pi1_3 <= pi1_2;
             Rx_1_Valid =|( pi1| pi1_1 | pi1_2| pi1_3);
            end
   end
 
 
   eth_rxethmac rxethmac1          //need to duplicate 6 time
(
  .MRxClk(clk),
  .MRxDV(Rx_1_Valid),
  .MRxD(pi1),
  .Transmitting(1'b0),
  .HugEn(1'b0),
  .DlyCrcEn(1'b0),
  .MaxFL(32'h0600),
  .r_IFG(1'b1),
  .Reset(reset),
  .RxData(Tx7in),
  .RxValid(RxValid),
  .RxStartFrm(RxStartFrm_out),
  .RxEndFrm(RxEndFrm_out),
  .ByteCnt(RxByteCnt),
  .ByteCntEq0(RxByteCntEq0),
  .ByteCntGreat2(RxByteCntGreat2),
  .ByteCntMaxFrame(RxByteCntMaxFrame),
  .CrcError(RxCrcError),
  .StateIdle(RxStateIdle),
  .StatePreamble(RxStatePreamble),
  .StateSFD(RxStateSFD),
  .StateData(RxStateData),
  .MAC(48'h0),
  .r_Pro(1'b1),
  .r_Bro(1'b1),
  .r_HASH0(32'h0),
  .r_HASH1(32'h0),
  .RxAbort(RxAbort),
  .AddressMiss(AddressMiss),
  .PassAll(1'b1),
  .ControlFrmAddressOK(ControlFrmAddressOK)
);
 
 
 
 
endmodule
 
 
 
 
module plu_serdes(reset,clk , pi1 , po1 ,RxStartFrm_out , RxEndFrm_out);
 
  input  reset , clk;
  input  [3:0] pi1;
  output [3:0] po1;
  output   RxStartFrm_out ,  RxEndFrm_out ;
  initial  ControlFrmAddressOK = 0;
 
   //out regs Rxs
  reg Rx_1_Valid ,ControlFrmAddressOK;
  reg  [3:0] pi1_1 , pi1_2, pi1_3;
  wire [7:0] RxData;
  wire [15:0] RxByteCnt;
  wire [1:0] RxStateData;
  wire   RxValid ,RxStartFrm ,RxEndFrm ,RxByteCntEq0,RxByteCntGreat2 ,RxByteCntMaxFrame,RxCrcError,RxStateIdle,RxStatePreamble,RxStateSFD ,RxAbort ,AddressMiss ;
 
 
   always @ (posedge clk or posedge reset)
   begin
       if (reset)
           begin
         //     pi1_w = 0;
          //    pi2_w = 0;
            end
           else
            begin
             pi1_1 <= pi1;
             pi1_2 <= pi1_1;
             pi1_3 <= pi1_2;
             Rx_1_Valid =|( pi1| pi1_1 | pi1_2| pi1_3);
            end
   end
 
 
   eth_rxethmac rxethmac1          //need to duplicate 6 time
(
  .MRxClk(clk),
  .MRxDV(Rx_1_Valid),
  .MRxD(pi1),
  .Transmitting(1'b0),
  .HugEn(1'b0),
  .DlyCrcEn(1'b0),
  .MaxFL(32'h0600),
  .r_IFG(1'b1),
  .Reset(reset),
  .RxData(RxData),
  .RxValid(RxValid),
  .RxStartFrm(RxStartFrm),
  .RxEndFrm(RxEndFrm),
  .ByteCnt(RxByteCnt),
  .ByteCntEq0(RxByteCntEq0),
  .ByteCntGreat2(RxByteCntGreat2),
  .ByteCntMaxFrame(RxByteCntMaxFrame),
  .CrcError(RxCrcError),
  .StateIdle(RxStateIdle),
  .StatePreamble(RxStatePreamble),
  .StateSFD(RxStateSFD),
  .StateData(RxStateData),
  .MAC(48'h0),
  .r_Pro(1'b1),
  .r_Bro(1'b1),
  .r_HASH0(32'h0),
  .r_HASH1(32'h0),
  .RxAbort(RxAbort),
  .AddressMiss(AddressMiss),
  .PassAll(1'b1),
  .ControlFrmAddressOK(ControlFrmAddressOK)
);
 
 //Tx 
   initial
  begin
     TxCarrierSense = 1'b0;
     TxUnderRun = 1'b0;
     for_under_run = 1'b0;
     // #7160   Rx_1_Valid = 1'b0;PadOut = 1;
     r_MinFL = 16'h0040;
     r_MaxFL = 16'h0600;
     CrcEnOut = 1;
     r_FullD =1;
     r_HugEn = 0;
     r_DlyCrcEn = 0;
     r_IPGT= 7'h12;
     r_IPGR1 = 7'hc;
     r_IPGR2 = 7'h12;
     r_CollValid = 6'h3f;
     r_MaxRet = 4'hf;
     r_NoBckof = 1'b0;
     r_ExDfrEn =1'b0;
     Collision <= 1'b0;
       #67027   Rx_1_Valid = 1'b1;
  end
  initial begin
      #74940   TxUnderRun = 1'b1;  //74940
      #360   TxUnderRun = 1'b0;
      #9960   TxUnderRun = 1'b1;   // 84240
      #360   TxUnderRun = 1'b0;
      #11400   TxUnderRun = 1'b1;    //96000
      #360   TxUnderRun = 1'b0;
      #10760   TxUnderRun = 1'b1;    //107120
      #360   TxUnderRun = 1'b0;
      #10840   TxUnderRun = 1'b1;    //107120
      #360   TxUnderRun = 1'b0;
 
 
      end
 
       always @ (posedge RxEndFrm)
           begin
             # 560 for_under_run = 1'b1;
              # 360 for_under_run = 1'b0;
           end
 
    reg   TxCarrierSense ,Collision,PadOut ,CrcEnOut,r_FullD ,r_HugEn,r_DlyCrcEn,r_ExDfrEn, r_NoBckof , TxUnderRun ,for_under_run ;
    reg [15:0] r_MinFL;
    reg [15:0] r_MaxFL;
    reg [6:0] r_IPGT ,r_IPGR1 ,r_IPGR2;
    reg [5:0] r_CollValid;
    reg [3:0] r_MaxRet;
    wire [3:0] RetryCnt;
    wire [1:0] StateData;
    wire [7:0] Tx7in;
    wire RxStartFrm_out ,RxEndFrm_out;
   StartFrmExtender Extender(.reset(reset),.clk(clk) , .in(RxData),.extOut(Tx7in) ,.RxStartFrm(RxStartFrm) ,.RxEndFrm(RxEndFrm),.RxStartFrm_out(RxStartFrm_out),.RxEndFrm_out(RxEndFrm_out) );
 
eth_txethmac txethmac1
(
  .MTxClk(clk),                      //
  .Reset(reset),                     //
  .CarrierSense(TxCarrierSense),     //
  .Collision(Collision),             //
  .TxData(Tx7in),                   //
  .TxStartFrm(RxStartFrm_out),           //
  .TxUnderRun(for_under_run),           //
  .TxEndFrm(RxEndFrm_out),               //
  .Pad(PadOut),                      //
  .MinFL(r_MinFL),                   //
  .CrcEn(CrcEnOut),                  //
  .FullD(r_FullD),                   //
  .HugEn(r_HugEn),                   //
  .DlyCrcEn(r_DlyCrcEn),             //
  .IPGT(r_IPGT),                     //
  .IPGR1(r_IPGR1),                   //
  .IPGR2(r_IPGR2),                   //
  .CollValid(r_CollValid),           //
  .MaxRet(r_MaxRet),                 //
  .NoBckof(r_NoBckof),               //
  .ExDfrEn(r_ExDfrEn),               //
  .MaxFL(r_MaxFL),                   //
  .MTxEn(mtxen_pad_o),
  .MTxD(po1),                        //  plu output [3:0]
  .MTxErr(mtxerr_pad_o),
  .TxUsedData(TxUsedDataIn),
  .TxDone(TxDoneIn),
  .TxRetry(TxRetry),
  .TxAbort(TxAbortIn),
  .WillTransmit(WillTransmit),
  .ResetCollision(ResetCollision),
  .RetryCnt(RetryCnt),               //
  .StartTxDone(StartTxDone),
  .StartTxAbort(StartTxAbort),
  .MaxCollisionOccured(MaxCollisionOccured),
  .LateCollision(LateCollision),
  .DeferIndication(DeferIndication),
  .StatePreamble(StatePreamble),
  .StateData(StateData)              //
);
 
 
 
 
 
endmodule
 
 
module word_2_nibble(reset,clk , po1 , RxData ,RxStartFrm , RxEndFrm);
 
    input  reset , clk;
  output  [3:0] po1;
  input [7:0] RxData;
  input   RxStartFrm ,  RxEndFrm ;
 
    //Tx 
   initial
  begin
     TxCarrierSense = 1'b0;
     TxUnderRun = 1'b0;
     for_under_run = 1'b0;
     r_MinFL = 16'h0040;
     r_MaxFL = 16'h0600;
     CrcEnOut = 1;
     r_FullD =1;
     r_HugEn = 0;
     r_DlyCrcEn = 0;
     r_IPGT= 7'h12;
     r_IPGR1 = 7'hc;
     r_IPGR2 = 7'h12;
     r_CollValid = 6'h3f;
     r_MaxRet = 4'hf;
     r_NoBckof = 1'b0;
     r_ExDfrEn =1'b0;
     Collision <= 1'b0;
    // RxStartFrm_out = 0;
 
  end
 
       always @ (posedge RxEndFrm)
           begin
             # 560 for_under_run = 1'b1;
              # 360 for_under_run = 1'b0;
           end
 
    reg   TxCarrierSense ,Collision,PadOut ,CrcEnOut,r_FullD ,r_HugEn,r_DlyCrcEn,r_ExDfrEn, r_NoBckof , TxUnderRun ,for_under_run ;
    reg [15:0] r_MinFL;
    reg [15:0] r_MaxFL;
    reg [6:0] r_IPGT ,r_IPGR1 ,r_IPGR2;
    reg [5:0] r_CollValid;
    reg [3:0] r_MaxRet;
    wire [3:0] RetryCnt;
    wire [1:0] StateData;
    wire [7:0] Tx7in;
    wire RxStartFrm ,RxEndFrm;
    wire RxStartFrm_out;
   StartFrmExtender Extender(.reset(reset),.clk(clk) , .in(RxData),.extOut(Tx7in) ,.RxStartFrm(RxStartFrm) ,.RxEndFrm(RxEndFrm),.RxStartFrm_out(RxStartFrm_out),.RxEndFrm_out(RxEndFrm_out) );
 
eth_txethmac txethmac1
(
  .MTxClk(clk),                      //
  .Reset(reset),                     //
  .CarrierSense(TxCarrierSense),     //
  .Collision(Collision),             //
  .TxData(Tx7in),                   //
  .TxStartFrm(RxStartFrm_out),           //
  .TxUnderRun(for_under_run),           //
  .TxEndFrm(RxEndFrm_out),               //
  .Pad(PadOut),                      //
  .MinFL(r_MinFL),                   //
  .CrcEn(CrcEnOut),                  //
  .FullD(r_FullD),                   //
  .HugEn(r_HugEn),                   //
  .DlyCrcEn(r_DlyCrcEn),             //
  .IPGT(r_IPGT),                     //
  .IPGR1(r_IPGR1),                   //
  .IPGR2(r_IPGR2),                   //
  .CollValid(r_CollValid),           //
  .MaxRet(r_MaxRet),                 //
  .NoBckof(r_NoBckof),               //
  .ExDfrEn(r_ExDfrEn),               //
  .MaxFL(r_MaxFL),                   //
  .MTxEn(mtxen_pad_o),
  .MTxD(po1),                        //  plu output [3:0]
  .MTxErr(mtxerr_pad_o),
  .TxUsedData(TxUsedDataIn),
  .TxDone(TxDoneIn),
  .TxRetry(TxRetry),
  .TxAbort(TxAbortIn),
  .WillTransmit(WillTransmit),
  .ResetCollision(ResetCollision),
  .RetryCnt(RetryCnt),               //
  .StartTxDone(StartTxDone),
  .StartTxAbort(StartTxAbort),
  .MaxCollisionOccured(MaxCollisionOccured),
  .LateCollision(LateCollision),
  .DeferIndication(DeferIndication),
  .StatePreamble(StatePreamble),
  .StateData(StateData)              //
  );
 
 
endmodule
 
 
module Dword_to_byte(reset,clk ,byte ,Dword , TxStartFrm , TxEndFrm ,TxStartFrm_0,TxEndFrm_1 );
 
    output [7:0] byte;
    input [31:0] Dword;
    input reset ,clk , TxStartFrm , TxEndFrm;
    output TxStartFrm_0 , TxEndFrm_1;
   // output TxStartFrm_ , TxEndFrm_;
     reg  clk_div2 ,clk_div4 ;
     reg [1:0] mod4;
     reg [1:0] mod4_;
     reg [7:0] byte;
     reg TxStartFrm_ , TxEndFrm_ ,TxStartFrm_1,TxStartFrm_2, start_en , start_en_ ,end_en , start_signal_detect;
     reg [9:0] counter;
     reg [1:0] FSMState;
     wire   TxStartFrm_0 , TxEndFrm_1;
     initial begin
        FSMState = 0;
         mod4=0;
         mod4_=0;
         counter =0;
         clk_div2=0;
         byte=0;
         clk_div4=0;
         start_en=0;
         TxStartFrm_1=0;
         TxStartFrm_2=0;
 
         end_en=0  ;
         start_en_=0;
         start_signal_detect=0;
         TxStartFrm_=0;
         end
 
      always @(posedge TxEndFrm )
        begin
            end_en<=1;
       //     mod4 <=0 ;
         end
      always @(posedge TxStartFrm )
        begin
           mod4_ <= 0;
         //  mod4 <= 0;
           counter=0;
          // start_en<=1;      //push simultaneously
           //clk_div2=1;
         end
 
     always @(posedge clk)
            begin
              clk_div2 <= clk^clk_div2;
              clk_div4 <= (~clk_div2)^clk_div4;
       /*    TxStartFrm_2<=TxStartFrm_1;
            TxStartFrm_<=(mod4_ ==2'b01)?TxStartFrm_:0;      */
            // TxEndFrm_1<=TxEndFrm_;        
             end
      assign  TxStartFrm_0=TxStartFrm_ & start_signal_detect & clk_div2;
      assign TxEndFrm_1 = end_en & (mod4==5);
      always @ (posedge clk_div2)
      begin
           TxEndFrm_<=(mod4==4)?(~clk_div2)&end_en:TxEndFrm;
           end_en<= (mod4==5)?0:end_en;
 
          mod4_<=mod4_+1;
          start_signal_detect = |Dword;
          TxStartFrm_=start_signal_detect & clk_div2;
          if (start_signal_detect & clk_div2)
              begin
                  counter<=counter+1;
                  end
                  if (counter >0)
                      begin
                       TxStartFrm_ =0;
                      end
 
 
 
       end
        always @(negedge clk_div2)
        begin
        case(mod4)
 
            2'h0:  byte<= Dword[31:24] ;
            2'h1:  byte<= Dword[23:16] ;
            2'h2:  byte<= Dword[15:8] ;
            2'h3:  byte<= Dword[7:0] ;
          endcase
        end
        always @ (posedge clk_div2)
        begin
            case (FSMState)
            2'b00: begin    // this is non recieving frame state
                    if (start_signal_detect == 0)
                        begin
                        //FSMState <= 2'b00;
                        mod4 <= 0;
                        end
                    else if (start_signal_detect == 1)
                        begin
                        FSMState <= 2'b11;
                        mod4 <= mod4+1;
                        end
                    end
        //    2'b01:  begin
         //           if (start_signal_detect == 1)
          //              begin
           //             FSMState <= 2'b11;
           //             mod4 <= 0;
           //             end
            //        end 
            2'b11: begin
                    if (start_signal_detect == 1)
                        begin
                        //FSMState <= 2'b11;
                        mod4 <= mod4 +1;
                        end
                        else if (start_signal_detect==0)
                        begin
                        FSMState<= 2'b00;
                        end
                    end
            endcase
        end
    endmodule
 
 
module byte_to_Dword(reset,clk ,byte ,Dword , RxStartFrm_ ,RxEndFrm_);
   input [9:0] byte;
    output [31:0] Dword;
    input reset ,clk;
    output RxStartFrm_ ,RxEndFrm_;
     reg [31:0] Dword, Dword1;
     reg [1:0] mod4 , mod4_;
     reg [7:0] RxData;
     reg  RxStartFrm ,RxEndFrm, RxStartFrm_ ,RxEndFrm_ , signal_detect;
     reg  clk_div2 ,clk_div4 ,shift_start;
     initial  begin
     mod4 = 0;
     RxData =0 ; clk_div2 = 0 ; RxStartFrm=0 ;RxEndFrm=0;
     clk_div4=0 ; shift_start=0;
     Dword=0; Dword1=0;
     end
 
    always @(negedge clk_div2 )
    begin
 
 
                case(mod4_)
 
                2'h0:      Dword1[31:24] <= RxData;
                2'h1:      Dword1[23:16] <= RxData;
                2'h2:      Dword1[15:8]  <= RxData;
                2'h3:      Dword1[7:0]   <= RxData;
              endcase
                mod4 <= mod4 + 1;
     end
 
      always @(posedge clk)
          begin
              clk_div2 <= clk^clk_div2;
              mod4_<=mod4;
              clk_div4 <= clk_div2^clk_div4;
              RxStartFrm <= byte[1];
              RxEndFrm   <= byte[0];
              RxData <=  byte[9:2];
              RxStartFrm_ <= byte[1];
              RxEndFrm_   <= byte[0];
           end
 
      always @(posedge clk_div2)
          begin
              if (mod4==0)
                begin
                Dword<=Dword1;
                signal_detect=|Dword1;
           //     RxStartFrm =1;
                end
                if (mod4 == 3)
                 begin
              //      RxStartFrm_<= clk_div2; 
              //      RxEndFrm_<= clk_div2;
             //     RxStartFrm=0;
                    shift_start<=0;
                end else begin
               //      RxStartFrm=0;
                    end
 
           end
       always @ (posedge RxStartFrm )
              begin
                mod4 <= 0;
                shift_start<=1;
                clk_div2=1;
              end
 
 
endmodule
 
module word_to_Dword (reset,clk ,in1,in2,in3,in4,in5,in6,out1,out2,out3,out4,out5,out6,
                      RxStartFrm1 ,RxStartFrm2,RxStartFrm3,RxStartFrm4,RxStartFrm5,RxStartFrm6,
                      RxEndFrm1,RxEndFrm2,RxEndFrm3,RxEndFrm4,RxEndFrm5,RxEndFrm6
                      );
    input [9:0] in1,in2,in3,in4,in5,in6;
    output [31:0] out1,out2,out3,out4,out5,out6;
    input reset ,clk;
     output RxStartFrm1 ,RxStartFrm2,RxStartFrm3,RxStartFrm4,RxStartFrm5,RxStartFrm6;
     output RxEndFrm1,RxEndFrm2,RxEndFrm3,RxEndFrm4,RxEndFrm5,RxEndFrm6;
   byte_to_Dword  byte_to_Dword1(.reset(reset),.clk(clk) ,.byte(in1) ,.Dword(out1),.RxStartFrm_(RxStartFrm1) ,.RxEndFrm_(RxEndFrm1));
   byte_to_Dword  byte_to_Dword2(.reset(reset),.clk(clk) ,.byte(in2) ,.Dword(out2),.RxStartFrm_(RxStartFrm2) ,.RxEndFrm_(RxEndFrm2));
   byte_to_Dword  byte_to_Dword3(.reset(reset),.clk(clk) ,.byte(in3) ,.Dword(out3),.RxStartFrm_(RxStartFrm3) ,.RxEndFrm_(RxEndFrm3));
   byte_to_Dword  byte_to_Dword4(.reset(reset),.clk(clk) ,.byte(in4) ,.Dword(out4),.RxStartFrm_(RxStartFrm4) ,.RxEndFrm_(RxEndFrm4));
   byte_to_Dword  byte_to_Dword5(.reset(reset),.clk(clk) ,.byte(in5) ,.Dword(out5),.RxStartFrm_(RxStartFrm5) ,.RxEndFrm_(RxEndFrm5));
   byte_to_Dword  byte_to_Dword6(.reset(reset),.clk(clk) ,.byte(in6) ,.Dword(out6),.RxStartFrm_(RxStartFrm6) ,.RxEndFrm_(RxEndFrm6));
 
 
endmodule
 
module StartFrmExtender (reset,clk , in,extOut ,RxStartFrm ,RxEndFrm,RxStartFrm_out ,RxEndFrm_out );
   input  reset , clk ,RxStartFrm ,RxEndFrm;
   input [7:0] in;
   output [7:0] extOut ;
   output RxStartFrm_out ,RxEndFrm_out;
   reg [7:0] first_sample ;
   reg div_2_clk;
   reg [6:0] counter;
   reg [1:0] state;
   reg [7:0] extOut ;
   reg RxStartFrm_out ,RxEndFrm_out;
   reg write_fifo , read_fifo , TxFifoClear ;
   wire            TxBufferFull;
   wire            TxBufferAlmostFull;
   wire            TxBufferAlmostEmpty;
   wire            TxBufferEmpty;
   wire [7:0] queue_out;
   wire [4:0] txfifo_cnt;
    eth_fifo #(
           .DATA_WIDTH(8),
           .DEPTH(32),
           .CNT_WIDTH(5))
 ext_fifo (
         .clk            (~div_2_clk),
         .reset          (reset),
         // Inputs
         .data_in        (in),
         .write          (write_fifo),
         .read           (read_fifo),
         .clear          (TxFifoClear),
         // Outputs
         .data_out       (queue_out),
         .full           (TxBufferFull),
         .almost_full    (TxBufferAlmostFull),
         .almost_empty   (TxBufferAlmostEmpty),
         .empty          (TxBufferEmpty),
         .cnt            (txfifo_cnt)
        );
 
    initial begin
    div_2_clk=0;
    RxEndFrm_out = 0;
    read_fifo =0;
    RxStartFrm_out = 0;
  // #67800  write_fifo=1;
    end
 
   always @(posedge  RxStartFrm)
   begin
         div_2_clk=1;
       end
   always @ (posedge clk or posedge reset )
   begin
       if (reset)
           begin
             extOut <= 0;
            end
           else
            begin
               div_2_clk <= div_2_clk^clk;
            end
   end
   always @(negedge reset)
   begin
        RxStartFrm_out <= 0;
    end
 
   always @ (posedge clk)
          begin
              if (RxStartFrm)
               begin
                  counter=0;
                  first_sample <= in;
                  state <= 2'h0;
                  assign   write_fifo=1;
              end
 
              if (RxEndFrm)
              begin
                 assign  write_fifo=0;
                   state<=2'h2;
              end
      end //clk 
 
    always @(negedge RxStartFrm)      //negedge
     begin
         RxStartFrm_out <= 1;
     end
   always @ (posedge div_2_clk)
      begin
       counter <= counter + 1;
       if (counter < 7 & state ==0)
         begin
              extOut <= first_sample;
              assign   write_fifo=1;
              assign   read_fifo =0;
         end
       else if (counter>=7 & state ==0)
             begin
                 extOut <= queue_out;
                    RxStartFrm_out = 0;
              assign   write_fifo=1;
              assign   read_fifo =1;
             end
       else if (state ==2 & ~TxBufferEmpty)
           begin
              extOut <= queue_out;
            assign  write_fifo=0;
            assign  read_fifo =1;
           end
        else if (state ==2 & TxBufferEmpty)
            begin
               extOut <= in;
             assign  write_fifo=0;
             assign  read_fifo =0;
             state <= 2'h3;
             assign TxFifoClear = 1;
             assign RxEndFrm_out = 1;
            end
            else if (state == 3)
                begin
                    assign TxFifoClear = 0;
                    assign RxEndFrm_out = 0;
                end
 
      end
 
 
endmodule
 

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[/] [mac_layer_switch/] [trunk/] [rtl/] [verilog/] [plu_moduls.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	ranm11
2
3			`/*****************************************************************************/`
4			`// Id ..........plu_modules.v //`
5			`// Author.......Ran Minerbi //`
6			`// //`
7			`// Unit Description : //`
8			`// plu is the physical layer. //`
9			`// Usually implemented as analog SerDes. //`
10			`// The unit Serialize the frames on transmission //`
11			`// And De-Serialize on receive. //`
12			`//`
13			`/*****************************************************************************/`
14
15
16
17
18			`module nibble_2_word(reset,clk , pi1 , Tx7in ,RxStartFrm_out , RxEndFrm_out);`
19
20
21			`input reset , clk;`
22			`input [3:0] pi1;`
23			`output [7:0] Tx7in;`
24			`output RxStartFrm_out , RxEndFrm_out ;`
25			`initial begin`
26			`ControlFrmAddressOK = 0;`
27			`// Tx7in=0;`
28			`end`
29			`//out regs Rxs`
30			`reg Rx_1_Valid ,ControlFrmAddressOK;`
31			`reg [3:0] pi1_1 , pi1_2, pi1_3;`
32			`// wire [7:0] Tx7in;`
33			`wire [7:0] RxData;`
34			`wire [15:0] RxByteCnt;`
35			`wire [1:0] RxStateData;`
36			`wire RxValid ,RxStartFrm ,RxEndFrm ,RxByteCntEq0,RxByteCntGreat2 ,RxByteCntMaxFrame,RxCrcError,RxStateIdle,RxStatePreamble,RxStateSFD ,RxAbort ,AddressMiss ;`
37
38
39			`always @ (posedge clk or posedge reset)`
40			`begin`
41			`if (reset)`
42			`begin`
43			`// pi1_w = 0;`
44			`// pi2_w = 0;`
45			`end`
46			`else`
47			`begin`
48			`pi1_1 <= pi1;`
49			`pi1_2 <= pi1_1;`
50			`pi1_3 <= pi1_2;`
51			`Rx_1_Valid =\|( pi1\| pi1_1 \| pi1_2\| pi1_3);`
52			`end`
53			`end`
54
55
56			`eth_rxethmac rxethmac1 //need to duplicate 6 time`
57			`(`
58			`.MRxClk(clk),`
59			`.MRxDV(Rx_1_Valid),`
60			`.MRxD(pi1),`
61			`.Transmitting(1'b0),`
62			`.HugEn(1'b0),`
63			`.DlyCrcEn(1'b0),`
64			`.MaxFL(32'h0600),`
65			`.r_IFG(1'b1),`
66			`.Reset(reset),`
67			`.RxData(Tx7in),`
68			`.RxValid(RxValid),`
69			`.RxStartFrm(RxStartFrm_out),`
70			`.RxEndFrm(RxEndFrm_out),`
71			`.ByteCnt(RxByteCnt),`
72			`.ByteCntEq0(RxByteCntEq0),`
73			`.ByteCntGreat2(RxByteCntGreat2),`
74			`.ByteCntMaxFrame(RxByteCntMaxFrame),`
75			`.CrcError(RxCrcError),`
76			`.StateIdle(RxStateIdle),`
77			`.StatePreamble(RxStatePreamble),`
78			`.StateSFD(RxStateSFD),`
79			`.StateData(RxStateData),`
80			`.MAC(48'h0),`
81			`.r_Pro(1'b1),`
82			`.r_Bro(1'b1),`
83			`.r_HASH0(32'h0),`
84			`.r_HASH1(32'h0),`
85			`.RxAbort(RxAbort),`
86			`.AddressMiss(AddressMiss),`
87			`.PassAll(1'b1),`
88			`.ControlFrmAddressOK(ControlFrmAddressOK)`
89			`);`
90
91
92
93
94			`endmodule`
95
96
97
98
99			`module plu_serdes(reset,clk , pi1 , po1 ,RxStartFrm_out , RxEndFrm_out);`
100
101			`input reset , clk;`
102			`input [3:0] pi1;`
103			`output [3:0] po1;`
104			`output RxStartFrm_out , RxEndFrm_out ;`
105			`initial ControlFrmAddressOK = 0;`
106
107			`//out regs Rxs`
108			`reg Rx_1_Valid ,ControlFrmAddressOK;`
109			`reg [3:0] pi1_1 , pi1_2, pi1_3;`
110			`wire [7:0] RxData;`
111			`wire [15:0] RxByteCnt;`
112			`wire [1:0] RxStateData;`
113			`wire RxValid ,RxStartFrm ,RxEndFrm ,RxByteCntEq0,RxByteCntGreat2 ,RxByteCntMaxFrame,RxCrcError,RxStateIdle,RxStatePreamble,RxStateSFD ,RxAbort ,AddressMiss ;`
114
115
116			`always @ (posedge clk or posedge reset)`
117			`begin`
118			`if (reset)`
119			`begin`
120			`// pi1_w = 0;`
121			`// pi2_w = 0;`
122			`end`
123			`else`
124			`begin`
125			`pi1_1 <= pi1;`
126			`pi1_2 <= pi1_1;`
127			`pi1_3 <= pi1_2;`
128			`Rx_1_Valid =\|( pi1\| pi1_1 \| pi1_2\| pi1_3);`
129			`end`
130			`end`
131
132
133			`eth_rxethmac rxethmac1 //need to duplicate 6 time`
134			`(`
135			`.MRxClk(clk),`
136			`.MRxDV(Rx_1_Valid),`
137			`.MRxD(pi1),`
138			`.Transmitting(1'b0),`
139			`.HugEn(1'b0),`
140			`.DlyCrcEn(1'b0),`
141			`.MaxFL(32'h0600),`
142			`.r_IFG(1'b1),`
143			`.Reset(reset),`
144			`.RxData(RxData),`
145			`.RxValid(RxValid),`
146			`.RxStartFrm(RxStartFrm),`
147			`.RxEndFrm(RxEndFrm),`
148			`.ByteCnt(RxByteCnt),`
149			`.ByteCntEq0(RxByteCntEq0),`
150			`.ByteCntGreat2(RxByteCntGreat2),`
151			`.ByteCntMaxFrame(RxByteCntMaxFrame),`
152			`.CrcError(RxCrcError),`
153			`.StateIdle(RxStateIdle),`
154			`.StatePreamble(RxStatePreamble),`
155			`.StateSFD(RxStateSFD),`
156			`.StateData(RxStateData),`
157			`.MAC(48'h0),`
158			`.r_Pro(1'b1),`
159			`.r_Bro(1'b1),`
160			`.r_HASH0(32'h0),`
161			`.r_HASH1(32'h0),`
162			`.RxAbort(RxAbort),`
163			`.AddressMiss(AddressMiss),`
164			`.PassAll(1'b1),`
165			`.ControlFrmAddressOK(ControlFrmAddressOK)`
166			`);`
167
168			`//Tx`
169			`initial`
170			`begin`
171			`TxCarrierSense = 1'b0;`
172			`TxUnderRun = 1'b0;`
173			`for_under_run = 1'b0;`
174			`// #7160 Rx_1_Valid = 1'b0;PadOut = 1;`
175			`r_MinFL = 16'h0040;`
176			`r_MaxFL = 16'h0600;`
177			`CrcEnOut = 1;`
178			`r_FullD =1;`
179			`r_HugEn = 0;`
180			`r_DlyCrcEn = 0;`
181			`r_IPGT= 7'h12;`
182			`r_IPGR1 = 7'hc;`
183			`r_IPGR2 = 7'h12;`
184			`r_CollValid = 6'h3f;`
185			`r_MaxRet = 4'hf;`
186			`r_NoBckof = 1'b0;`
187			`r_ExDfrEn =1'b0;`
188			`Collision <= 1'b0;`
189			`#67027 Rx_1_Valid = 1'b1;`
190			`end`
191			`initial begin`
192			`#74940 TxUnderRun = 1'b1; //74940`
193			`#360 TxUnderRun = 1'b0;`
194			`#9960 TxUnderRun = 1'b1; // 84240`
195			`#360 TxUnderRun = 1'b0;`
196			`#11400 TxUnderRun = 1'b1; //96000`
197			`#360 TxUnderRun = 1'b0;`
198			`#10760 TxUnderRun = 1'b1; //107120`
199			`#360 TxUnderRun = 1'b0;`
200			`#10840 TxUnderRun = 1'b1; //107120`
201			`#360 TxUnderRun = 1'b0;`
202
203
204			`end`
205
206			`always @ (posedge RxEndFrm)`
207			`begin`
208			`# 560 for_under_run = 1'b1;`
209			`# 360 for_under_run = 1'b0;`
210			`end`
211
212			`reg TxCarrierSense ,Collision,PadOut ,CrcEnOut,r_FullD ,r_HugEn,r_DlyCrcEn,r_ExDfrEn, r_NoBckof , TxUnderRun ,for_under_run ;`
213			`reg [15:0] r_MinFL;`
214			`reg [15:0] r_MaxFL;`
215			`reg [6:0] r_IPGT ,r_IPGR1 ,r_IPGR2;`
216			`reg [5:0] r_CollValid;`
217			`reg [3:0] r_MaxRet;`
218			`wire [3:0] RetryCnt;`
219			`wire [1:0] StateData;`
220			`wire [7:0] Tx7in;`
221			`wire RxStartFrm_out ,RxEndFrm_out;`
222			`StartFrmExtender Extender(.reset(reset),.clk(clk) , .in(RxData),.extOut(Tx7in) ,.RxStartFrm(RxStartFrm) ,.RxEndFrm(RxEndFrm),.RxStartFrm_out(RxStartFrm_out),.RxEndFrm_out(RxEndFrm_out) );`
223
224			`eth_txethmac txethmac1`
225			`(`
226			`.MTxClk(clk), //`
227			`.Reset(reset), //`
228			`.CarrierSense(TxCarrierSense), //`
229			`.Collision(Collision), //`
230			`.TxData(Tx7in), //`
231			`.TxStartFrm(RxStartFrm_out), //`
232			`.TxUnderRun(for_under_run), //`
233			`.TxEndFrm(RxEndFrm_out), //`
234			`.Pad(PadOut), //`
235			`.MinFL(r_MinFL), //`
236			`.CrcEn(CrcEnOut), //`
237			`.FullD(r_FullD), //`
238			`.HugEn(r_HugEn), //`
239			`.DlyCrcEn(r_DlyCrcEn), //`
240			`.IPGT(r_IPGT), //`
241			`.IPGR1(r_IPGR1), //`
242			`.IPGR2(r_IPGR2), //`
243			`.CollValid(r_CollValid), //`
244			`.MaxRet(r_MaxRet), //`
245			`.NoBckof(r_NoBckof), //`
246			`.ExDfrEn(r_ExDfrEn), //`
247			`.MaxFL(r_MaxFL), //`
248			`.MTxEn(mtxen_pad_o),`
249			`.MTxD(po1), // plu output [3:0]`
250			`.MTxErr(mtxerr_pad_o),`
251			`.TxUsedData(TxUsedDataIn),`
252			`.TxDone(TxDoneIn),`
253			`.TxRetry(TxRetry),`
254			`.TxAbort(TxAbortIn),`
255			`.WillTransmit(WillTransmit),`
256			`.ResetCollision(ResetCollision),`
257			`.RetryCnt(RetryCnt), //`
258			`.StartTxDone(StartTxDone),`
259			`.StartTxAbort(StartTxAbort),`
260			`.MaxCollisionOccured(MaxCollisionOccured),`
261			`.LateCollision(LateCollision),`
262			`.DeferIndication(DeferIndication),`
263			`.StatePreamble(StatePreamble),`
264			`.StateData(StateData) //`
265			`);`
266
267
268
269
270
271			`endmodule`
272
273
274			`module word_2_nibble(reset,clk , po1 , RxData ,RxStartFrm , RxEndFrm);`
275
276			`input reset , clk;`
277			`output [3:0] po1;`
278			`input [7:0] RxData;`
279			`input RxStartFrm , RxEndFrm ;`
280
281			`//Tx`
282			`initial`
283			`begin`
284			`TxCarrierSense = 1'b0;`
285			`TxUnderRun = 1'b0;`
286			`for_under_run = 1'b0;`
287			`r_MinFL = 16'h0040;`
288			`r_MaxFL = 16'h0600;`
289			`CrcEnOut = 1;`
290			`r_FullD =1;`
291			`r_HugEn = 0;`
292			`r_DlyCrcEn = 0;`
293			`r_IPGT= 7'h12;`
294			`r_IPGR1 = 7'hc;`
295			`r_IPGR2 = 7'h12;`
296			`r_CollValid = 6'h3f;`
297			`r_MaxRet = 4'hf;`
298			`r_NoBckof = 1'b0;`
299			`r_ExDfrEn =1'b0;`
300			`Collision <= 1'b0;`
301			`// RxStartFrm_out = 0;`
302
303			`end`
304
305			`always @ (posedge RxEndFrm)`
306			`begin`
307			`# 560 for_under_run = 1'b1;`
308			`# 360 for_under_run = 1'b0;`
309			`end`
310
311			`reg TxCarrierSense ,Collision,PadOut ,CrcEnOut,r_FullD ,r_HugEn,r_DlyCrcEn,r_ExDfrEn, r_NoBckof , TxUnderRun ,for_under_run ;`
312			`reg [15:0] r_MinFL;`
313			`reg [15:0] r_MaxFL;`
314			`reg [6:0] r_IPGT ,r_IPGR1 ,r_IPGR2;`
315			`reg [5:0] r_CollValid;`
316			`reg [3:0] r_MaxRet;`
317			`wire [3:0] RetryCnt;`
318			`wire [1:0] StateData;`
319			`wire [7:0] Tx7in;`
320			`wire RxStartFrm ,RxEndFrm;`
321			`wire RxStartFrm_out;`
322			`StartFrmExtender Extender(.reset(reset),.clk(clk) , .in(RxData),.extOut(Tx7in) ,.RxStartFrm(RxStartFrm) ,.RxEndFrm(RxEndFrm),.RxStartFrm_out(RxStartFrm_out),.RxEndFrm_out(RxEndFrm_out) );`
323
324			`eth_txethmac txethmac1`
325			`(`
326			`.MTxClk(clk), //`
327			`.Reset(reset), //`
328			`.CarrierSense(TxCarrierSense), //`
329			`.Collision(Collision), //`
330			`.TxData(Tx7in), //`
331			`.TxStartFrm(RxStartFrm_out), //`
332			`.TxUnderRun(for_under_run), //`
333			`.TxEndFrm(RxEndFrm_out), //`
334			`.Pad(PadOut), //`
335			`.MinFL(r_MinFL), //`
336			`.CrcEn(CrcEnOut), //`
337			`.FullD(r_FullD), //`
338			`.HugEn(r_HugEn), //`
339			`.DlyCrcEn(r_DlyCrcEn), //`
340			`.IPGT(r_IPGT), //`
341			`.IPGR1(r_IPGR1), //`
342			`.IPGR2(r_IPGR2), //`
343			`.CollValid(r_CollValid), //`
344			`.MaxRet(r_MaxRet), //`
345			`.NoBckof(r_NoBckof), //`
346			`.ExDfrEn(r_ExDfrEn), //`
347			`.MaxFL(r_MaxFL), //`
348			`.MTxEn(mtxen_pad_o),`
349			`.MTxD(po1), // plu output [3:0]`
350			`.MTxErr(mtxerr_pad_o),`
351			`.TxUsedData(TxUsedDataIn),`
352			`.TxDone(TxDoneIn),`
353			`.TxRetry(TxRetry),`
354			`.TxAbort(TxAbortIn),`
355			`.WillTransmit(WillTransmit),`
356			`.ResetCollision(ResetCollision),`
357			`.RetryCnt(RetryCnt), //`
358			`.StartTxDone(StartTxDone),`
359			`.StartTxAbort(StartTxAbort),`
360			`.MaxCollisionOccured(MaxCollisionOccured),`
361			`.LateCollision(LateCollision),`
362			`.DeferIndication(DeferIndication),`
363			`.StatePreamble(StatePreamble),`
364			`.StateData(StateData) //`
365			`);`
366
367
368			`endmodule`
369
370
371			`module Dword_to_byte(reset,clk ,byte ,Dword , TxStartFrm , TxEndFrm ,TxStartFrm_0,TxEndFrm_1 );`
372
373			`output [7:0] byte;`
374			`input [31:0] Dword;`
375			`input reset ,clk , TxStartFrm , TxEndFrm;`
376			`output TxStartFrm_0 , TxEndFrm_1;`
377			`// output TxStartFrm_ , TxEndFrm_;`
378			`reg clk_div2 ,clk_div4 ;`
379	4	ranm11	`reg [1:0] mod4;`
380	2	ranm11	`reg [1:0] mod4_;`
381			`reg [7:0] byte;`
382			`reg TxStartFrm_ , TxEndFrm_ ,TxStartFrm_1,TxStartFrm_2, start_en , start_en_ ,end_en , start_signal_detect;`
383			`reg [9:0] counter;`
384	4	ranm11	`reg [1:0] FSMState;`
385	2	ranm11	`wire TxStartFrm_0 , TxEndFrm_1;`
386			`initial begin`
387	4	ranm11	`FSMState = 0;`
388	2	ranm11	`mod4=0;`
389			`mod4_=0;`
390			`counter =0;`
391			`clk_div2=0;`
392			`byte=0;`
393			`clk_div4=0;`
394			`start_en=0;`
395			`TxStartFrm_1=0;`
396			`TxStartFrm_2=0;`
397
398			`end_en=0 ;`
399			`start_en_=0;`
400			`start_signal_detect=0;`
401			`TxStartFrm_=0;`
402			`end`
403
404			`always @(posedge TxEndFrm )`
405			`begin`
406			`end_en<=1;`
407	4	ranm11	`// mod4 <=0 ;`
408	2	ranm11	`end`
409			`always @(posedge TxStartFrm )`
410			`begin`
411			`mod4_ <= 0;`
412	4	ranm11	`// mod4 <= 0;`
413	2	ranm11	`counter=0;`
414			`// start_en<=1; //push simultaneously`
415			`//clk_div2=1;`
416			`end`
417
418			`always @(posedge clk)`
419			`begin`
420			`clk_div2 <= clk^clk_div2;`
421			`clk_div4 <= (~clk_div2)^clk_div4;`
422			`/* TxStartFrm_2<=TxStartFrm_1;`
423			`TxStartFrm_<=(mod4_ ==2'b01)?TxStartFrm_:0; */`
424			`// TxEndFrm_1<=TxEndFrm_;`
425			`end`
426			`assign TxStartFrm_0=TxStartFrm_ & start_signal_detect & clk_div2;`
427			`assign TxEndFrm_1 = end_en & (mod4==5);`
428			`always @ (posedge clk_div2)`
429			`begin`
430			`TxEndFrm_<=(mod4==4)?(~clk_div2)&end_en:TxEndFrm;`
431			`end_en<= (mod4==5)?0:end_en;`
432	4	ranm11
433	2	ranm11	`mod4_<=mod4_+1;`
434			`start_signal_detect = \|Dword;`
435			`TxStartFrm_=start_signal_detect & clk_div2;`
436			`if (start_signal_detect & clk_div2)`
437			`begin`
438			`counter<=counter+1;`
439			`end`
440			`if (counter >0)`
441			`begin`
442			`TxStartFrm_ =0;`
443			`end`
444	4	ranm11
445
446
447			`end`
448			`always @(negedge clk_div2)`
449			`begin`
450			`case(mod4)`
451	2	ranm11
452			`2'h0: byte<= Dword[31:24] ;`
453			`2'h1: byte<= Dword[23:16] ;`
454			`2'h2: byte<= Dword[15:8] ;`
455			`2'h3: byte<= Dword[7:0] ;`
456			`endcase`
457	4	ranm11	`end`
458			`always @ (posedge clk_div2)`
459			`begin`
460			`case (FSMState)`
461			`2'b00: begin // this is non recieving frame state`
462			`if (start_signal_detect == 0)`
463			`begin`
464			`//FSMState <= 2'b00;`
465			`mod4 <= 0;`
466			`end`
467			`else if (start_signal_detect == 1)`
468			`begin`
469			`FSMState <= 2'b11;`
470			`mod4 <= mod4+1;`
471			`end`
472			`end`
473			`// 2'b01: begin`
474			`// if (start_signal_detect == 1)`
475			`// begin`
476			`// FSMState <= 2'b11;`
477			`// mod4 <= 0;`
478			`// end`
479			`// end`
480			`2'b11: begin`
481			`if (start_signal_detect == 1)`
482			`begin`
483			`//FSMState <= 2'b11;`
484			`mod4 <= mod4 +1;`
485			`end`
486			`else if (start_signal_detect==0)`
487			`begin`
488			`FSMState<= 2'b00;`
489			`end`
490			`end`
491			`endcase`
492			`end`
493	2	ranm11	`endmodule`
494
495
496			`module byte_to_Dword(reset,clk ,byte ,Dword , RxStartFrm_ ,RxEndFrm_);`
497			`input [9:0] byte;`
498			`output [31:0] Dword;`
499			`input reset ,clk;`
500			`output RxStartFrm_ ,RxEndFrm_;`
501			`reg [31:0] Dword, Dword1;`
502			`reg [1:0] mod4 , mod4_;`
503			`reg [7:0] RxData;`
504			`reg RxStartFrm ,RxEndFrm, RxStartFrm_ ,RxEndFrm_ , signal_detect;`
505			`reg clk_div2 ,clk_div4 ,shift_start;`
506			`initial begin`
507			`mod4 = 0;`
508			`RxData =0 ; clk_div2 = 0 ; RxStartFrm=0 ;RxEndFrm=0;`
509			`clk_div4=0 ; shift_start=0;`
510			`Dword=0; Dword1=0;`
511			`end`
512
513			`always @(negedge clk_div2 )`
514			`begin`
515
516
517			`case(mod4_)`
518
519			`2'h0: Dword1[31:24] <= RxData;`
520			`2'h1: Dword1[23:16] <= RxData;`
521			`2'h2: Dword1[15:8] <= RxData;`
522			`2'h3: Dword1[7:0] <= RxData;`
523			`endcase`
524			`mod4 <= mod4 + 1;`
525			`end`
526
527			`always @(posedge clk)`
528			`begin`
529			`clk_div2 <= clk^clk_div2;`
530			`mod4_<=mod4;`
531			`clk_div4 <= clk_div2^clk_div4;`
532			`RxStartFrm <= byte[1];`
533			`RxEndFrm <= byte[0];`
534			`RxData <= byte[9:2];`
535			`RxStartFrm_ <= byte[1];`
536			`RxEndFrm_ <= byte[0];`
537			`end`
538
539			`always @(posedge clk_div2)`
540			`begin`
541			`if (mod4==0)`
542			`begin`
543			`Dword<=Dword1;`
544			`signal_detect=\|Dword1;`
545			`// RxStartFrm =1;`
546			`end`
547			`if (mod4 == 3)`
548			`begin`
549			`// RxStartFrm_<= clk_div2;`
550			`// RxEndFrm_<= clk_div2;`
551			`// RxStartFrm=0;`
552			`shift_start<=0;`
553			`end else begin`
554			`// RxStartFrm=0;`
555			`end`
556
557			`end`
558			`always @ (posedge RxStartFrm )`
559			`begin`
560			`mod4 <= 0;`
561			`shift_start<=1;`
562			`clk_div2=1;`
563			`end`
564
565
566			`endmodule`
567
568			`module word_to_Dword (reset,clk ,in1,in2,in3,in4,in5,in6,out1,out2,out3,out4,out5,out6,`
569			`RxStartFrm1 ,RxStartFrm2,RxStartFrm3,RxStartFrm4,RxStartFrm5,RxStartFrm6,`
570			`RxEndFrm1,RxEndFrm2,RxEndFrm3,RxEndFrm4,RxEndFrm5,RxEndFrm6`
571			`);`
572			`input [9:0] in1,in2,in3,in4,in5,in6;`
573			`output [31:0] out1,out2,out3,out4,out5,out6;`
574			`input reset ,clk;`
575			`output RxStartFrm1 ,RxStartFrm2,RxStartFrm3,RxStartFrm4,RxStartFrm5,RxStartFrm6;`
576			`output RxEndFrm1,RxEndFrm2,RxEndFrm3,RxEndFrm4,RxEndFrm5,RxEndFrm6;`
577			`byte_to_Dword byte_to_Dword1(.reset(reset),.clk(clk) ,.byte(in1) ,.Dword(out1),.RxStartFrm_(RxStartFrm1) ,.RxEndFrm_(RxEndFrm1));`
578			`byte_to_Dword byte_to_Dword2(.reset(reset),.clk(clk) ,.byte(in2) ,.Dword(out2),.RxStartFrm_(RxStartFrm2) ,.RxEndFrm_(RxEndFrm2));`
579			`byte_to_Dword byte_to_Dword3(.reset(reset),.clk(clk) ,.byte(in3) ,.Dword(out3),.RxStartFrm_(RxStartFrm3) ,.RxEndFrm_(RxEndFrm3));`
580			`byte_to_Dword byte_to_Dword4(.reset(reset),.clk(clk) ,.byte(in4) ,.Dword(out4),.RxStartFrm_(RxStartFrm4) ,.RxEndFrm_(RxEndFrm4));`
581			`byte_to_Dword byte_to_Dword5(.reset(reset),.clk(clk) ,.byte(in5) ,.Dword(out5),.RxStartFrm_(RxStartFrm5) ,.RxEndFrm_(RxEndFrm5));`
582			`byte_to_Dword byte_to_Dword6(.reset(reset),.clk(clk) ,.byte(in6) ,.Dword(out6),.RxStartFrm_(RxStartFrm6) ,.RxEndFrm_(RxEndFrm6));`
583
584
585			`endmodule`
586
587			`module StartFrmExtender (reset,clk , in,extOut ,RxStartFrm ,RxEndFrm,RxStartFrm_out ,RxEndFrm_out );`
588			`input reset , clk ,RxStartFrm ,RxEndFrm;`
589			`input [7:0] in;`
590			`output [7:0] extOut ;`
591			`output RxStartFrm_out ,RxEndFrm_out;`
592			`reg [7:0] first_sample ;`
593			`reg div_2_clk;`
594			`reg [6:0] counter;`
595			`reg [1:0] state;`
596			`reg [7:0] extOut ;`
597			`reg RxStartFrm_out ,RxEndFrm_out;`
598			`reg write_fifo , read_fifo , TxFifoClear ;`
599			`wire TxBufferFull;`
600			`wire TxBufferAlmostFull;`
601			`wire TxBufferAlmostEmpty;`
602			`wire TxBufferEmpty;`
603			`wire [7:0] queue_out;`
604			`wire [4:0] txfifo_cnt;`
605			`eth_fifo #(`
606			`.DATA_WIDTH(8),`
607			`.DEPTH(32),`
608			`.CNT_WIDTH(5))`
609			`ext_fifo (`
610			`.clk (~div_2_clk),`
611			`.reset (reset),`
612			`// Inputs`
613			`.data_in (in),`
614			`.write (write_fifo),`
615			`.read (read_fifo),`
616			`.clear (TxFifoClear),`
617			`// Outputs`
618			`.data_out (queue_out),`
619			`.full (TxBufferFull),`
620			`.almost_full (TxBufferAlmostFull),`
621			`.almost_empty (TxBufferAlmostEmpty),`
622			`.empty (TxBufferEmpty),`
623			`.cnt (txfifo_cnt)`
624			`);`
625
626			`initial begin`
627			`div_2_clk=0;`
628			`RxEndFrm_out = 0;`
629			`read_fifo =0;`
630			`RxStartFrm_out = 0;`
631			`// #67800 write_fifo=1;`
632			`end`
633
634			`always @(posedge RxStartFrm)`
635			`begin`
636			`div_2_clk=1;`
637			`end`
638			`always @ (posedge clk or posedge reset )`
639			`begin`
640			`if (reset)`
641			`begin`
642			`extOut <= 0;`
643			`end`
644			`else`
645			`begin`
646			`div_2_clk <= div_2_clk^clk;`
647			`end`
648			`end`
649			`always @(negedge reset)`
650			`begin`
651			`RxStartFrm_out <= 0;`
652			`end`
653
654			`always @ (posedge clk)`
655			`begin`
656			`if (RxStartFrm)`
657			`begin`
658			`counter=0;`
659			`first_sample <= in;`
660			`state <= 2'h0;`
661			`assign write_fifo=1;`
662			`end`
663
664			`if (RxEndFrm)`
665			`begin`
666			`assign write_fifo=0;`
667			`state<=2'h2;`
668			`end`
669			`end //clk`
670
671			`always @(negedge RxStartFrm) //negedge`
672			`begin`
673			`RxStartFrm_out <= 1;`
674			`end`
675			`always @ (posedge div_2_clk)`
676			`begin`
677			`counter <= counter + 1;`
678			`if (counter < 7 & state ==0)`
679			`begin`
680			`extOut <= first_sample;`
681			`assign write_fifo=1;`
682			`assign read_fifo =0;`
683			`end`
684			`else if (counter>=7 & state ==0)`
685			`begin`
686			`extOut <= queue_out;`
687			`RxStartFrm_out = 0;`
688			`assign write_fifo=1;`
689			`assign read_fifo =1;`
690			`end`
691			`else if (state ==2 & ~TxBufferEmpty)`
692			`begin`
693			`extOut <= queue_out;`
694			`assign write_fifo=0;`
695			`assign read_fifo =1;`
696			`end`
697			`else if (state ==2 & TxBufferEmpty)`
698			`begin`
699			`extOut <= in;`
700			`assign write_fifo=0;`
701			`assign read_fifo =0;`
702			`state <= 2'h3;`
703			`assign TxFifoClear = 1;`
704			`assign RxEndFrm_out = 1;`
705			`end`
706			`else if (state == 3)`
707			`begin`
708			`assign TxFifoClear = 0;`
709			`assign RxEndFrm_out = 0;`
710			`end`
711
712			`end`
713
714
715			`endmodule`
716