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[/] [man2uart/] [web_uploads/] [Man2uartopencores.txt] - Blame information for rev 6

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-- Manchester to UART Converter
--              Manchester signal from Bosch speed doom controller keyboard
--              Device                  : EPM7128
                Total macrocells        : 114/128
-- Design by    Kenneth YK Ho
--              eyeonfly Limited
--              8 November 2004
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
 
entity Man2uart is
        port (  RxD             : in std_logic;
                clk             : in std_logic;
                reset           : in std_logic;
                check_pt1       : out std_logic;
                check_pt2       : out std_logic;
                check_pt3       : out std_logic;
                check_pt4       : out std_logic;
                check_pt5       : out std_logic;
                uart            : out std_logic
                );
end Man2uart;
 
architecture behavioural of Man2uart is
        type state_type is (guard_time, preamble, sync_start, data);
        type bit_type is (start,s0,s1,s2,s3,s4,s5,s6,s7,stop);
        signal uart_bit, next_bit                                       : bit_type;
        signal state, next_state                                        : state_type;
        signal phase_one, phase_two, phase_three                        : std_logic;
        signal Data_in, Data_change, Data_bit                           : std_logic;
        signal Data_counter                                             : std_logic_vector(3 downto 0);
        signal clock_timer                                              : std_logic_vector(5 downto 0);
        signal uart_active, uart_start, bit_change                      : std_logic;
        signal uart_not_start                                           : std_logic;
        signal uart_delay                                               : std_logic_vector(6 downto 0);
        signal Data_buffer, TxD                                         : std_logic_vector(7 downto 0);
        signal check                                                    : std_logic_vector(3 downto 0);
 
begin
        process (clk,reset)
        variable timer          : std_logic_vector(6 downto 0);
        variable Data_out       : std_logic_vector(7 downto 0);
        begin
                if reset = '1' then
                        state <= guard_time;
                        timer := "0000000";
                        uart <= '1';
                        uart_start <= '0';
                        uart_active <='0';
                elsif clk = '1' and clk'event then
                if clock_timer /= 108 then
                        clock_timer <= clock_timer + 1;
                else
                        clock_timer <= "000000";
                        timer := unsigned(timer) + 1 ;
 
                        state <= next_state;
                        Data_in <= RxD;
                        data_bit <= not RxD;
                        if Data_in = RxD then
                                Data_change <= '0';
                        else
                                Data_change <= '1';
                        end if;
------------creat time phase---------------------
                        if timer = 12 then
                                phase_one <= '1';
                        elsif timer = 19 or timer = 1 then
                                phase_one <= '0';
                        else
                                phase_one <= phase_one;
                        end if;
                        if timer = 25 then
                                phase_two <= '1';
                        elsif timer = 38 or timer = 1 then
                                phase_two <= '0';
                        else
                                phase_two <= phase_two;
                        end if;
                        if timer = 39 then
                                phase_three <= '1';
                        elsif timer = 70 or timer = 1 then
                                phase_three <= '0';
                        else
                                phase_three <= phase_three;
                        end if;
                        if timer = 91 then
                                timer := "1011010";
                        end if;
 
check_pt1 <= check(0);
check_pt2 <= check(1);
check_pt3 <= check(2);
check_pt4 <= check(3);
uart_not_start <= not uart_start;
check_pt5 <= uart_not_start;
 
                        if Data_change = '1' then
                                case state is
                                        when guard_time =>
check <= "0001";
                                                if timer = "1011010" then
                                                        if Data_in = '0' then
                                                                timer := "0000000";
                                                                next_state <= guard_time;
                                                        else
                                                                timer := "0000000";
                                                                next_state <= preamble;
                                                        end if;
                                                else
                                                        timer := "0000000";
                                                        next_state <= guard_time;
                                                end if;
                                        when preamble =>
check <= "0010";
                                                if Data_in = '0' then
                                                        if phase_one = '1' then
                                                                next_state <= preamble;
                                                        elsif phase_three = '1' then
                                                                timer := "0000000";
                                                                next_state <= sync_start;
                                                        else
                                                                if timer > 70 then
                                                                        timer := "0000000";
                                                                        next_state <= guard_time;
                                                                end if;
                                                        end if;
                                                else
                                                        timer := "0000000";
--                                                      if phase_two = '1' then
--                                                              next_state <= preamble;
--                                                      else
--                                                              next_state <= guard_time;
--                                                      end if;
                                                end if;
                                        when sync_start =>
check <= "0100";
                                                if Data_in = '0' then
                                                        timer := "0000000";
                                                        if phase_one = '1' then
                                                                Data_counter <= "0000";
                                                                next_state <= data;
                                                        else
                                                                if timer > 70 then
                                                                        timer := "0000000";
                                                                        next_state <= guard_time;
                                                                end if;
                                                        end if;
                                                else
                                                        timer := "0000000";
                                                        if phase_three = '1' then
                                                                next_state <= sync_start;
                                                        else
                                                                if timer > 70 then
                                                                        timer := "0000000";
                                                                        next_state <= guard_time;
                                                                end if;
                                                        end if;
                                                end if;
                                        when data =>
check <= "1000";
                                                if phase_one = '1' then
                                                        next_state <= data;
                                                elsif phase_two = '1' then
                                                        timer := "0000000";
                                                        if Data_counter = "1000" then
                                                                uart_active <= '1';
                                                                Data_buffer <= Data_out;
                                                                next_state <= guard_time;
                                                        else
                                                                Data_counter <= Data_counter + 1;
                                                                Data_out(7 downto 0) := Data_bit & Data_out(7 downto 1);
                                                                next_state <= data;
                                                        end if;
                                                else
                                                                if timer > 39 then
                                                                        timer := "0000000";
                                                                        next_state <= guard_time;
                                                                end if;
                                                end if;
                                        when others =>
                                                next_state <= guard_time;
                                end case;
                        end if;
----------- UART state
                        uart_bit <= next_bit;
 
                        if uart_delay = 104 then
                                uart_delay <= "0000000";
                                bit_change <= '1';
                        else
                                uart_delay <= uart_delay + 1;
                                bit_change <= '0';
                        end if;
 
                        if uart_active ='1' and uart_start = '0' then
                                uart_active <= '0';
                                uart_start <= '1';
                                TxD <= Data_buffer;
                        end if;
 
                        if bit_change = '1' then
                                case uart_bit is
                                        when start =>
                                                if uart_start = '0' then
                                                        next_bit <= stop;
                                                else
                                                        uart <= '0';
                                                        next_bit <= s0;
                                                end if;
                                        when s0 =>
                                                if uart_start = '0' then
                                                        next_bit <= stop;
                                                else
                                                uart <= TxD(0);
                                                next_bit <= s1;
                                                end if;
                                        when s1 =>
                                                if uart_start = '0' then
                                                        next_bit <= stop;
                                                else
                                                        uart <= TxD(1);
                                                        next_bit <= s2;
                                                end if;
                                        when s2 =>
                                                if uart_start = '0' then
                                                        next_bit <= stop;
                                                else
                                                        uart <= TxD(2);
                                                        next_bit <= s3;
                                                end if;
                                        when s3 =>
                                                if uart_start = '0' then
                                                        next_bit <= stop;
                                                else
                                                        uart <= TxD(3);
                                                        next_bit <= s4;
                                                end if;
                                        when s4 =>
                                                if uart_start = '0' then
                                                        next_bit <= stop;
                                                else
                                                        uart <= TxD(4);
                                                        next_bit <= s5;
                                                end if;
                                        when s5 =>
                                                if uart_start = '0' then
                                                        next_bit <= stop;
                                                else
                                                        uart <= TxD(5);
                                                        next_bit <= s6;
                                                end if;
                                        when s6 =>
                                                if uart_start = '0' then
                                                        next_bit <= stop;
                                                else
                                                        uart <= TxD(6);
                                                        next_bit <= s7;
                                                end if;
                                        when s7 =>
                                                if uart_start = '0' then
                                                        next_bit <= stop;
                                                else
                                                        uart <= TxD(7);
                                                        next_bit <= stop;
                                                        uart_start <= '0';
                                                end if;
                                        when stop =>
                                                uart <= '1';
                                                if uart_start = '0' then
                                                        next_bit <= stop;
                                                else
                                                        next_bit <= start;
                                                end if;
                                        when others =>
                                                next_bit <= stop;
                                                uart_start <= '0';
                                end case;
                        end if;
                end if;
                end if;
        end process;
end behavioural;

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Subversion Repositories man2uart

[/] [man2uart/] [web_uploads/] [Man2uartopencores.txt] - Blame information for rev 6

Line No.	Rev	Author	Line
1	6	root	`-- Manchester to UART Converter`
2			`-- Manchester signal from Bosch speed doom controller keyboard`
3			`-- Device : EPM7128`
4			`Total macrocells : 114/128`
5			`-- Design by Kenneth YK Ho`
6			`-- eyeonfly Limited`
7			`-- 8 November 2004`
8
9			`LIBRARY ieee;`
10			`USE ieee.std_logic_1164.ALL;`
11			`USE ieee.std_logic_arith.ALL;`
12			`USE ieee.std_logic_unsigned.ALL;`
13
14			`entity Man2uart is`
15			`port ( RxD : in std_logic;`
16			`clk : in std_logic;`
17			`reset : in std_logic;`
18			`check_pt1 : out std_logic;`
19			`check_pt2 : out std_logic;`
20			`check_pt3 : out std_logic;`
21			`check_pt4 : out std_logic;`
22			`check_pt5 : out std_logic;`
23			`uart : out std_logic`
24			`);`
25			`end Man2uart;`
26
27			`architecture behavioural of Man2uart is`
28			`type state_type is (guard_time, preamble, sync_start, data);`
29			`type bit_type is (start,s0,s1,s2,s3,s4,s5,s6,s7,stop);`
30			`signal uart_bit, next_bit : bit_type;`
31			`signal state, next_state : state_type;`
32			`signal phase_one, phase_two, phase_three : std_logic;`
33			`signal Data_in, Data_change, Data_bit : std_logic;`
34			`signal Data_counter : std_logic_vector(3 downto 0);`
35			`signal clock_timer : std_logic_vector(5 downto 0);`
36			`signal uart_active, uart_start, bit_change : std_logic;`
37			`signal uart_not_start : std_logic;`
38			`signal uart_delay : std_logic_vector(6 downto 0);`
39			`signal Data_buffer, TxD : std_logic_vector(7 downto 0);`
40			`signal check : std_logic_vector(3 downto 0);`
41
42			`begin`
43			`process (clk,reset)`
44			`variable timer : std_logic_vector(6 downto 0);`
45			`variable Data_out : std_logic_vector(7 downto 0);`
46			`begin`
47			`if reset = '1' then`
48			`state <= guard_time;`
49			`timer := "0000000";`
50			`uart <= '1';`
51			`uart_start <= '0';`
52			`uart_active <='0';`
53			`elsif clk = '1' and clk'event then`
54			`if clock_timer /= 108 then`
55			`clock_timer <= clock_timer + 1;`
56			`else`
57			`clock_timer <= "000000";`
58			`timer := unsigned(timer) + 1 ;`
59
60			`state <= next_state;`
61			`Data_in <= RxD;`
62			`data_bit <= not RxD;`
63			`if Data_in = RxD then`
64			`Data_change <= '0';`
65			`else`
66			`Data_change <= '1';`
67			`end if;`
68			`------------creat time phase---------------------`
69			`if timer = 12 then`
70			`phase_one <= '1';`
71			`elsif timer = 19 or timer = 1 then`
72			`phase_one <= '0';`
73			`else`
74			`phase_one <= phase_one;`
75			`end if;`
76			`if timer = 25 then`
77			`phase_two <= '1';`
78			`elsif timer = 38 or timer = 1 then`
79			`phase_two <= '0';`
80			`else`
81			`phase_two <= phase_two;`
82			`end if;`
83			`if timer = 39 then`
84			`phase_three <= '1';`
85			`elsif timer = 70 or timer = 1 then`
86			`phase_three <= '0';`
87			`else`
88			`phase_three <= phase_three;`
89			`end if;`
90			`if timer = 91 then`
91			`timer := "1011010";`
92			`end if;`
93
94			`check_pt1 <= check(0);`
95			`check_pt2 <= check(1);`
96			`check_pt3 <= check(2);`
97			`check_pt4 <= check(3);`
98			`uart_not_start <= not uart_start;`
99			`check_pt5 <= uart_not_start;`
100
101			`if Data_change = '1' then`
102			`case state is`
103			`when guard_time =>`
104			`check <= "0001";`
105			`if timer = "1011010" then`
106			`if Data_in = '0' then`
107			`timer := "0000000";`
108			`next_state <= guard_time;`
109			`else`
110			`timer := "0000000";`
111			`next_state <= preamble;`
112			`end if;`
113			`else`
114			`timer := "0000000";`
115			`next_state <= guard_time;`
116			`end if;`
117			`when preamble =>`
118			`check <= "0010";`
119			`if Data_in = '0' then`
120			`if phase_one = '1' then`
121			`next_state <= preamble;`
122			`elsif phase_three = '1' then`
123			`timer := "0000000";`
124			`next_state <= sync_start;`
125			`else`
126			`if timer > 70 then`
127			`timer := "0000000";`
128			`next_state <= guard_time;`
129			`end if;`
130			`end if;`
131			`else`
132			`timer := "0000000";`
133			`-- if phase_two = '1' then`
134			`-- next_state <= preamble;`
135			`-- else`
136			`-- next_state <= guard_time;`
137			`-- end if;`
138			`end if;`
139			`when sync_start =>`
140			`check <= "0100";`
141			`if Data_in = '0' then`
142			`timer := "0000000";`
143			`if phase_one = '1' then`
144			`Data_counter <= "0000";`
145			`next_state <= data;`
146			`else`
147			`if timer > 70 then`
148			`timer := "0000000";`
149			`next_state <= guard_time;`
150			`end if;`
151			`end if;`
152			`else`
153			`timer := "0000000";`
154			`if phase_three = '1' then`
155			`next_state <= sync_start;`
156			`else`
157			`if timer > 70 then`
158			`timer := "0000000";`
159			`next_state <= guard_time;`
160			`end if;`
161			`end if;`
162			`end if;`
163			`when data =>`
164			`check <= "1000";`
165			`if phase_one = '1' then`
166			`next_state <= data;`
167			`elsif phase_two = '1' then`
168			`timer := "0000000";`
169			`if Data_counter = "1000" then`
170			`uart_active <= '1';`
171			`Data_buffer <= Data_out;`
172			`next_state <= guard_time;`
173			`else`
174			`Data_counter <= Data_counter + 1;`
175			`Data_out(7 downto 0) := Data_bit & Data_out(7 downto 1);`
176			`next_state <= data;`
177			`end if;`
178			`else`
179			`if timer > 39 then`
180			`timer := "0000000";`
181			`next_state <= guard_time;`
182			`end if;`
183			`end if;`
184			`when others =>`
185			`next_state <= guard_time;`
186			`end case;`
187			`end if;`
188			`----------- UART state`
189			`uart_bit <= next_bit;`
190
191			`if uart_delay = 104 then`
192			`uart_delay <= "0000000";`
193			`bit_change <= '1';`
194			`else`
195			`uart_delay <= uart_delay + 1;`
196			`bit_change <= '0';`
197			`end if;`
198
199			`if uart_active ='1' and uart_start = '0' then`
200			`uart_active <= '0';`
201			`uart_start <= '1';`
202			`TxD <= Data_buffer;`
203			`end if;`
204
205			`if bit_change = '1' then`
206			`case uart_bit is`
207			`when start =>`
208			`if uart_start = '0' then`
209			`next_bit <= stop;`
210			`else`
211			`uart <= '0';`
212			`next_bit <= s0;`
213			`end if;`
214			`when s0 =>`
215			`if uart_start = '0' then`
216			`next_bit <= stop;`
217			`else`
218			`uart <= TxD(0);`
219			`next_bit <= s1;`
220			`end if;`
221			`when s1 =>`
222			`if uart_start = '0' then`
223			`next_bit <= stop;`
224			`else`
225			`uart <= TxD(1);`
226			`next_bit <= s2;`
227			`end if;`
228			`when s2 =>`
229			`if uart_start = '0' then`
230			`next_bit <= stop;`
231			`else`
232			`uart <= TxD(2);`
233			`next_bit <= s3;`
234			`end if;`
235			`when s3 =>`
236			`if uart_start = '0' then`
237			`next_bit <= stop;`
238			`else`
239			`uart <= TxD(3);`
240			`next_bit <= s4;`
241			`end if;`
242			`when s4 =>`
243			`if uart_start = '0' then`
244			`next_bit <= stop;`
245			`else`
246			`uart <= TxD(4);`
247			`next_bit <= s5;`
248			`end if;`
249			`when s5 =>`
250			`if uart_start = '0' then`
251			`next_bit <= stop;`
252			`else`
253			`uart <= TxD(5);`
254			`next_bit <= s6;`
255			`end if;`
256			`when s6 =>`
257			`if uart_start = '0' then`
258			`next_bit <= stop;`
259			`else`
260			`uart <= TxD(6);`
261			`next_bit <= s7;`
262			`end if;`
263			`when s7 =>`
264			`if uart_start = '0' then`
265			`next_bit <= stop;`
266			`else`
267			`uart <= TxD(7);`
268			`next_bit <= stop;`
269			`uart_start <= '0';`
270			`end if;`
271			`when stop =>`
272			`uart <= '1';`
273			`if uart_start = '0' then`
274			`next_bit <= stop;`
275			`else`
276			`next_bit <= start;`
277			`end if;`
278			`when others =>`
279			`next_bit <= stop;`
280			`uart_start <= '0';`
281			`end case;`
282			`end if;`
283			`end if;`
284			`end if;`
285			`end process;`
286			`end behavioural;`