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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.std_logic_arith.all ;
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entity me is
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port (
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rst : in std_logic; -- Power On Reset Active High
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rts : in std_logic; -- Request To Send Active Low
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txd : in std_logic; -- Data To Be Transmitted
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clkin : in std_logic ; -- Clk Input
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cts : out std_logic ; -- Clear to Sen Output Active Low
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txcout : out std_logic; -- TX CLK = just clkin /16
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txlen : out std_logic; -- TX Enable Active High
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mdo : out std_logic -- Manchester Encoded Data Output (TX "01" for 1 and "10" for 0)
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) ;
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end me ;
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-------------------------------------------------------------------------------
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architecture rtl of me is
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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begin -- architecture rtl
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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main : process (rst, clkin)
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-------------------------------------------------------------------------------
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type state_t is (
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idle,
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preamble,
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postpreamble,
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sending,
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eom
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);
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variable state : state_t;
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variable PrCounter : integer range 0 to 31;
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variable TxCounter : integer range 0 to 15;
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-- variables to hold the internal value of the output ports:
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variable TXCOUT_i : std_logic;
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variable CTS_i : std_logic;
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variable MDO_i : std_logic;
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variable MDO_i1 : std_logic;
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variable TXLEN_i : std_logic;
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-------------------------------------------------------------------------------
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begin
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-------------------------------------------------------------------------------
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if rst='1' then
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-------------------------------------------------------------------------------
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--asynchronously reset all internal variables
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state := idle;
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PrCounter := 30 ; -- adjunt to length of your preamble
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TxCounter := 0 ;
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TXCOUT_i := '0';
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CTS_i := '1';
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MDO_i := '0';
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MDO_i1 := '0';
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TXLEN_i := '0';
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-------------------------------------------------------------------------------
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elsif clkin'event and clkin='1' then
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-------------------------------------------------------------------------------
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--counter for clkin/16
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--must txcout have a 50% duty cycle?
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TxCounter := (TxCounter + 1) mod 16;
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if TxCounter = 0 then
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TXCOUT_i := '0';
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end if;
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if TxCounter = 8 then
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TXCOUT_i := '1';
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end if;
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-------------------------------------------------------------------------------
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case state is
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-------------------------------------------------------------------------------
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when idle =>
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if rts = '0' then
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state := preamble;
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PrCounter := 30 ;
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MDO_i := '0';
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end if;
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-------------------------------------------------------------------------------
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when preamble =>
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if TxCounter = 8 then --when to mark? 2? 3? ..7? 8?
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TXLEN_i := '1'; --when will it be turned off ? never?
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end if;
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if TxCounter = 8 then --when to toggle? 2? 3? .. 6?
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MDO_i := not(MDO_i); --preamble 15 times '10'
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PrCounter := PrCounter - 1;
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if PrCounter = 0 then
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state := postpreamble;
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PrCounter := 2; -- adjunt to length of your post-preamble.
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end if;
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end if;
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-------------------------------------------------------------------------------
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when postpreamble =>
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if TxCounter = 8 then --when to toggle? 2? 3? .. 6?
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MDO_i := '1'; -- post preamble: '11'
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PrCounter := PrCounter - 1;
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if PrCounter = 0 then
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--MDO_i := txd;
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state := sending;
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CTS_i := '0'; --when will it be turned off ? never?
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end if;
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end if;
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-------------------------------------------------------------------------------
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when sending =>
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if TxCounter = 8 then
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--this samples the date with clkin, not with txcout..
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--what is actually needed ?
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MDO_i := txd;
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if (rts = '1') then
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state := eom;
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PrCounter := 2;
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CTS_i := '1';
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MDO_i := '1';
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end if;
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end if;
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when eom =>
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if TxCounter = 8 then
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MDO_i := '1';
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PrCounter := PrCounter - 1;
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if PrCounter = 0 then
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state := idle;
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end if;
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end if;
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--manchester encoding not yet implemented, too many open questions..
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--to many unspecified specifications ;)!
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--how to return to idle?
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-------------------------------------------------------------------------------
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when others =>
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state := idle;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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end case;
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if state /= idle then
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if state = eom then
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MDO_i1 := MDO_i;
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elsif TxCounter = 8 then
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TXLEN_i := '1';
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MDO_i1 := not MDO_i;
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elsif TxCounter = 0 then
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MDO_i1 := MDO_i;
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end if;
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elsif TXCounter = 8 then
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TXLEN_i := '0';
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end if;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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end if;
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-------------------------------------------------------------------------------
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--assign output ports:
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txcout <= TXCOUT_i;
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cts <= CTS_i;
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mdo <= MDO_i1;
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txlen <= TXLEN_i;
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-------------------------------------------------------------------------------
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end process main;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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end ; -- architecture rtl
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------------------------------------------
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-- ME2.vhd
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