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--*************************************************************************
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--* *
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--* Copyright (C) 2014 William B Hunter - LGPL *
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--* *
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--* This source file may be used and distributed without *
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--* restriction provided that this copyright statement is not *
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--* removed from the file and that any derivative work contains *
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--* the original copyright notice and the associated disclaimer. *
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--* *
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--* This source file is free software; you can redistribute it *
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--* and/or modify it under the terms of the GNU Lesser General *
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--* Public License as published by the Free Software Foundation; *
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--* either version 2.1 of the License, or (at your option) any *
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--* later version. *
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--* *
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--* This source is distributed in the hope that it will be *
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--* useful, but WITHout ANY WARRANTY; without even the implied *
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--* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR *
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--* PURPOSE. See the GNU Lesser General Public License for more *
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--* details. *
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--* *
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--* You should have received a copy of the GNU Lesser General *
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--* Public License along with this source; if not, download it *
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--* from http://www.opencores.org/lgpl.shtml *
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--* *
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--*************************************************************************
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--
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-- Engineer: William B Hunter
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-- Create Date: 08/08/2014
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-- Project: Manchester Uart
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-- File: decode.vhd
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-- Description: This decoder recieves short bursts of 16 bit data words encoded with as manchester data.
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-- Because this is not a stream decoder, it has no sync pattern or packet alignment typical of manchester decoders.
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-- It therefore uses start and stop bits much like a UART. Both the start and stop bits are always ones. The idle
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-- state is always high, and the ones are a low to high transition in the middle of the bit period, and a zero is a
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-- high to low transition in the middle of the bit period. A high for 3 bit periods is a reset/resync.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity decode is
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Port(
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clk16x : in STD_LOGIC;
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srst : in STD_LOGIC;
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rxd : in STD_LOGIC;
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rx_data : out STD_LOGIC_VECTOR (15 downto 0);
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rx_stb : out STD_LOGIC;
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fm_err : out STD_LOGIC;
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rx_idle : out STD_LOGIC
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);
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end decode;
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architecture rtl of decode is
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signal shifter : std_logic_vector(15 downto 0);
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signal tick_cnt : integer range 0 to 31 := 0;
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signal bit_cnt : integer range 0 to 15 := 0;
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signal rcv_stb : std_logic := '0';
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signal debounce : std_logic_vector(3 downto 0) := (others=>'1');
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signal filt : std_logic := '1';
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signal filt_old : std_logic := '1';
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signal fall_det : std_logic := '0';
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signal rst_det : std_logic := '0';
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signal rst_cnt :integer range 0 to 15 := 0;
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signal rise_det : std_logic := '0';
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type rcv_state_type is (SM_SEEK, SM_START, SM_RCV, SM_END, SM_ERR);
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signal rcv_state : rcv_state_type := SM_SEEK;
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begin
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--this process debounces the input signal to remove noise. It also detects rising
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-- and falling edges and reset conditions.
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p_debounce: process(clk16x)
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begin
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if rising_edge(clk16x) then
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if srst = '1' then
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debounce <= "1111";
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rise_det <= '0';
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fall_det <= '0';
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rst_cnt <= 0;
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rst_det <= '0';
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filt_old <= '1';
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else
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if filt_old = '0' and filt = '1' then
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rise_det <= '1';
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fall_det <= '0';
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elsif filt_old = '1' and filt = '0' then
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rise_det <= '0';
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fall_det <= '1';
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else
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rise_det <= '0';
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fall_det <= '0';
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end if;
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if filt = '0' then
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rst_cnt <= 0;
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rst_det <= '0';
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elsif rst_cnt = 47 then
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rst_det <= '1';
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else
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rst_det <= '0';
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rst_cnt <= rst_cnt +1;
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end if;
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debounce <= debounce(2 downto 0) & rxd;
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filt_old <= filt;
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end if;
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end if;
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end process;
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--this is the actual debounce logic. It is a basic 2 out of three majority vote
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with debounce(3 downto 1) select filt <=
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'1' when "111",
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'1' when "110",
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'1' when "101",
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'1' when "011",
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'0' when others;
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--This process is the main reciever. It detects the start bit, 16 data bits and the stop bit.
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-- it does this by having a window for which it looks for the midbit transistions. When a transition is found,
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-- it syncs on the new transition so that it can look for the next. This allows the wide variation in clock rates
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-- between the transmitter and reciever.
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p_reciever: process(clk16x)
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begin
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if rising_edge(clk16x) then
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if srst = '1' then
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rcv_state <= SM_SEEK;
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rcv_stb <= '0';
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tick_cnt <= 0;
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bit_cnt <= 0;
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else
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case rcv_state is
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--The idle state is high, so look for the leading edge of the start bit which is a falling edge
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when SM_SEEK =>
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rcv_stb <= '0';
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tick_cnt <= 0;
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bit_cnt <= 0;
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if fall_det = '1' then
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rcv_state <= SM_START;
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end if;
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--After the falling edge, there should be the mid bit rising edge of the start bit, Make sure
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-- this appears in the right window
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when SM_START =>
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--skip the first 4 clock periods
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if tick_cnt < 4 then
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tick_cnt <= tick_cnt + 1;
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--The active window is ticks 4 to 10, look for the rising edge in this window
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elsif tick_cnt < 11 then
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--a rising edge in the window allows us to start recieveing data
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if rise_det = '1' then
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tick_cnt <= 0;
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rcv_state <= SM_RCV;
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--two falling edges in a row is an error
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elsif fall_det = '1' then
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rcv_state <= SM_ERR;
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tick_cnt <= 0;
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bit_cnt <= 0;
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else
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tick_cnt <= tick_cnt + 1;
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end if;
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--if there was no rising edge in the window, than error out
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else
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rcv_state <= SM_ERR;
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tick_cnt <= 0;
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bit_cnt <= 0;
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end if;
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when SM_RCV =>
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--During recieve, we only look for the mid bit transisions in the window of
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-- 12 to 18 ticks from the previous mid bit transition
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if tick_cnt < 12 then
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tick_cnt <= tick_cnt + 1;
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elsif tick_cnt < 19 then
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if rise_det = '1' or fall_det = '1' then
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tick_cnt <= 0;
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shifter <= shifter(14 downto 0) & rise_det;
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if bit_cnt = 15 then
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rcv_state <= SM_END;
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tick_cnt <= 0;
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else
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bit_cnt <= bit_cnt + 1;
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end if;
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else
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tick_cnt <= tick_cnt + 1;
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end if;
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else
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rcv_state <= SM_ERR;
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tick_cnt <= 0;
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bit_cnt <= 0;
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end if;
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when SM_END =>
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--after all 16 data bits, we should see a stop bit which is always 1 (rising edge)
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if tick_cnt < 12 then
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tick_cnt <= tick_cnt + 1;
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elsif tick_cnt < 19 then
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if rise_det = '1' then
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tick_cnt <= 0;
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bit_cnt <= 0;
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rcv_stb <= '1';
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rcv_state <= SM_SEEK;
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elsif fall_det = '1' then
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rcv_state <= SM_ERR;
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tick_cnt <= 0;
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bit_cnt <= 0;
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else
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tick_cnt <= tick_cnt + 1;
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end if;
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else
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rcv_state <= SM_ERR;
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tick_cnt <= 0;
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bit_cnt <= 0;
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end if;
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--this state handles the error conditions. The error persists until a reset condition
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--It is up to external logic to latch errors if nessesary
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when SM_ERR =>
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rcv_stb <= '0';
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tick_cnt <= 4;
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bit_cnt <= 0;
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if rst_det = '1' then
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rcv_state <= SM_SEEK;
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end if;
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--we should never get here
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when others =>
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rcv_stb <= '0';
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tick_cnt <= 4;
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bit_cnt <= 0;
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rcv_state <= SM_SEEK;
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end case;
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end if; --srst
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end if; --clk16x
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end process;
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rx_idle <= '1' when rcv_state = SM_SEEK else '0';
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fm_err <= '1' when rcv_state = SM_ERR else '0';
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rx_data <= shifter;
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rx_stb <= rcv_stb;
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end rtl;
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