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[/] [manchesterwireless/] [branches/] [singledouble/] [singleDouble/] [simTest.vhd] - Blame information for rev 8

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1 7 kingmu
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity test_sim is
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end test_sim;
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architecture Behavioral of test_sim is
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  COMPONENT singleDouble
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        PORT(
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    clk_i   :  in  std_logic;
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    ce_i    :  in  std_logic;
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    rst_i   :  in  std_logic;
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    data_i  :  in  std_logic;
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    q_o     :  out std_logic_vector(3 downto 0);
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    ready_o :  out std_logic
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                );
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        END COMPONENT;
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  signal clk : std_logic := '0';
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  signal ce_i : std_logic := '0';
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  signal mdi : std_logic := '0';
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  signal q_modified : std_logic_vector(3 downto 0);
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  signal nd_modified : std_logic;
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  constant period : time := 10 ns;
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  constant md_period : time := period*16;
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  signal reset : std_logic := '1';
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begin
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  Inst_modified: singleDouble PORT MAP(
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    clk_i =>  clk,
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    ce_i  =>  ce_i,
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    rst_i  =>  reset,
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    data_i   =>  mdi,
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    q_o     =>  q_modified,
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    ready_o    =>  nd_modified
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  );
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  process
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  begin
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    loop
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      reset <= '1';
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      ce_i <= '0';
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      wait for (2*md_period);
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      reset <= '0';
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      ce_i <= '1';
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      wait for 2*md_period;
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      mdi <= not mdi;
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      wait for 2*md_period;
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      mdi <= not mdi;
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      wait for md_period;
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      mdi <= not mdi;
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      wait for md_period;
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      mdi <= not mdi;
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      wait for md_period;
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      mdi <= not mdi;
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      wait for 2*md_period;
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      mdi <= not mdi;
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      wait for md_period;
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      mdi <= not mdi;
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      wait for 5*md_period;
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    end loop;
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  end process;
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  process
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  begin
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    loop
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      clk <= not clk;
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      wait for period/2;
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    end loop;
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  end process;
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end Behavioral;
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