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[/] [manchesterwireless/] [branches/] [singledouble/] [singleDouble/] [singleDouble.vhd] - Blame information for rev 7

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1 7 kingmu 
-----------------------------------------------------------------------------
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--      Copyright (C) 2009 José Rodríguez-Navarro
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--
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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-- Lesser General Public License for more details.
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--
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--  Identify single/double ones/zeros based on length
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--  of time data_i is high/low
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--
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--  Revision  Date        Author                Comment
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--  --------  ----------  --------------------  ----------------
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--  1.0       20/02/09    J. Rodriguez-Navarro  Initial revision
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--  1.1       21/06/09    M. Thiagarajan        Modified with FSM
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--  Future revisions tracked in Subversion at OpenCores.org
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--  under the manchesterwireless project
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.globals.all;
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--------------------------------------------------------------------------------
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entity singleDouble is
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  port (
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    clk_i   :  in  std_logic;
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    ce_i    :  in  std_logic;
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    rst_i   :  in  std_logic;
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    data_i  :  in  std_logic;
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    q_o     :  out std_logic_vector(3 downto 0);
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    ready_o :  out std_logic
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  );
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end;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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architecture behavioral of singleDouble is
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  signal single_one:      std_logic;
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  signal double_one:      std_logic;
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  signal single_zero:     std_logic;
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  signal double_zero:     std_logic;
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  signal count_ones    : integer range 0 to INTERVAL_MAX_DOUBLE;
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  signal count_zeros   : integer range 0 to INTERVAL_MAX_DOUBLE;
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  signal data_i_d  :         std_logic;
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  signal data_i_d2 :         std_logic;
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  signal    ct_state, nxt_state  : bit_vector(2 downto 0);
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  signal    ce_i_RT, data_i_RT, data_i_FT : std_logic;
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  signal    ce_i_d, ce_i_d2               : std_logic;
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  signal    count_zeros_en, count_ones_en : std_logic;
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  constant  IDLE: bit_vector(2 downto 0) := "001";
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  constant  CNT0: bit_vector(2 downto 0) := "010";
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  constant  CNT1: bit_vector(2 downto 0) := "100";
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  begin
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    process (clk_i,rst_i)
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    begin
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      if (rst_i = '1') then
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        ce_i_d  <= '0';
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        ce_i_d2 <= '0';
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      elsif (clk_i'event and clk_i = '1') then
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        ce_i_d    <= ce_i;
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        ce_i_d2  <= ce_i_d;
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      end if;
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    end process;
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    ce_i_RT   <= ce_i_d and (not(ce_i_d2));  --CE rising edge
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    process (clk_i,rst_i)
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    begin
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      if (rst_i = '1') then
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        data_i_d  <= '0';
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        data_i_d2 <= '0';
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      elsif (clk_i'event and clk_i = '1') then
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        data_i_d  <= data_i;
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        data_i_d2  <= data_i_d;
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      end if;
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    end process;
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    data_i_RT   <= data_i_d and (not(data_i_d2));  --Data rising edge
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    data_i_FT   <= (not data_i_d) and data_i_d2;  --Data falling edge
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    ready_o     <= ((data_i_RT or data_i_FT) and ce_i) or ce_i_RT;
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    process (clk_i,rst_i)  --State register
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    begin
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      if (rst_i = '1') then
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        ct_state <= IDLE;
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      elsif (clk_i'event and clk_i = '1') then
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        ct_state <= nxt_state;
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      end if;
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    end process;
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    process (ct_state,ce_i_RT,data_i,ce_i,data_i_FT,data_i_RT)  --Next State logic
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    begin
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      case ct_state is
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          when IDLE   =>
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            if ((ce_i_RT = '1') and (data_i = '0'))then
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              nxt_State <= CNT0;
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            elsif ((ce_i_RT = '1') and (data_i = '1')) then
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              nxt_state <= CNT1;
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            else
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              nxt_state <= IDLE;
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            end if;
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          when CNT0   =>
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            if (ce_i = '0') then
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              nxt_state <= IDLE;
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            elsif (data_i_RT = '1') then
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              nxt_state <= CNT1;
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            else
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              nxt_state <= CNT0;
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            end if;
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          when CNT1   =>
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            if (ce_i = '0') then
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              nxt_state <= IDLE;
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            elsif (data_i_FT = '1') then
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              nxt_state <= CNT0;
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            else
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              nxt_state <= CNT1;
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            end if;
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          when others   =>
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            nxt_state <=  IDLE;
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      end case;
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    end process;
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    process (ct_state)  --State output logic
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    begin
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      case ct_state is
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        when IDLE   =>
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          count_ones_en    <= '0';
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          count_zeros_en   <= '0';
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        when CNT0   =>
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          count_ones_en    <= '0';
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          count_zeros_en   <= '1';
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        when CNT1   =>
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          count_ones_en    <= '1';
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          count_zeros_en   <= '0';
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        when others    => null;
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    end case;
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  end process;
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  process (clk_i,rst_i)  --counters
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  begin
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    if (rst_i = '1') then
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      count_ones    <=  0;
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      count_zeros   <=  0;
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    elsif (clk_i'event and clk_i = '1') then
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      if (count_zeros_en = '1') then
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        count_zeros   <= count_zeros + 1;
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        count_ones    <= 0;
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      elsif (count_ones_en = '1') then
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        count_ones   <= count_ones + 1;
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        count_zeros    <= 0;
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      end if;
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    end if;
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  end process;
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  process(count_ones)
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  begin
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    if (count_ones >= INTERVAL_MIN_DOUBLE) and (count_ones <= INTERVAL_MAX_DOUBLE) then
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      double_one <= '1';
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    else
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      double_one <= '0';
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    end if;
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    if (count_ones >= INTERVAL_MIN_SINGLE) and (count_ones <= INTERVAL_MAX_SINGLE) then
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      single_one <= '1';
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    else
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      single_one <= '0';
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    end if;
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  end process;
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  process(count_zeros)
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  begin
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    if (count_zeros >= INTERVAL_MIN_DOUBLE) and (count_zeros <= INTERVAL_MAX_DOUBLE) then
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      double_zero <= '1';
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    else
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      double_zero <= '0';
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    end if;
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    if (count_zeros >= INTERVAL_MIN_SINGLE) and (count_zeros <= INTERVAL_MAX_SINGLE) then
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      single_zero <= '1';
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    else
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      single_zero <= '0';
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    end if;
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  end process;
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  process (rst_i,data_i_RT,data_i_FT)
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  begin
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    if (rst_i = '1') then
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      q_o   <= "0000";
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    else
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      q_o   <= double_zero & single_zero & double_one & single_one;
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    end if;
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  end process;
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end;

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