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[/] [manchesterwireless/] [branches/] [singledouble/] [singleDouble/] [synthTest.vhd] - Blame information for rev 8

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1 8 kingmu
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    16:03:52 06/22/2009 
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-- Design Name: 
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-- Module Name:    synthTest - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity synthTest is
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  port (
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    clk : in std_logic;
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    ce_i    :  in  std_logic;
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    reset   :  in  std_logic;
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    data_i  :  in  std_logic;
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    out_new     :  out std_logic_vector(3 downto 0);
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    nd_new :  out std_logic
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  );
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end synthTest;
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architecture Behavioral of synthTest is
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  COMPONENT singleDouble
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        PORT(
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    clk_i   :  in  std_logic;
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    ce_i    :  in  std_logic;
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    rst_i   :  in  std_logic;
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    data_i  :  in  std_logic;
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    q_o     :  out std_logic_vector(3 downto 0);
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    ready_o :  out std_logic
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                );
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        END COMPONENT;
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begin
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  Inst_modified: singleDouble PORT MAP(
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    clk_i =>  clk,
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    ce_i  =>  ce_i,
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    rst_i  =>  reset,
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    data_i   =>  data_i,
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    q_o     =>  out_new,
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    ready_o    =>  nd_new
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  );
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end Behavioral;
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