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[/] [manchesterwireless/] [branches/] [singledouble/] [waitForStart/] [waitForStart.vhd] - Blame information for rev 6

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1 2 kingmu
-----------------------------------------------------------------------------
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--      Copyright (C) 2009 Sam Green
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--
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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-- Lesser General Public License for more details.
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--
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-- Waits for data_i to high for INTERVAL_QUADRUPLE FPGA clocks then
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-- sends ready_o high
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--
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.globals.all;
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entity waitForStart is
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  port (
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    data_i : in  std_logic;
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    clk_i : in  std_logic;
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    rst_i : in std_logic;
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    ready_o : out  std_logic
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  );
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end;
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architecture behavioral of waitForStart is
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begin
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  process (clk_i, rst_i)
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    variable counter : integer;
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    variable lock : std_logic;
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  begin
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    if (rst_i = '1') then
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      ready_o <= '0';
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      counter := 0;
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      lock := '0';
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    elsif rising_edge(clk_i) then
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      if data_i = '1' then
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        counter := counter + 1;
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      else
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        counter := 0;
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      end if;
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      if counter > INTERVAL_QUADRUPLE or lock = '1' then
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        ready_o <= '1';
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        lock := '1';
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      else
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        ready_o <= '0';
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      end if;
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    end if;
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  end process;
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 end;
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