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[/] [manchesterwireless/] [trunk/] [decode/] [simTest.vhd] - Blame information for rev 10

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1 2 kingmu 
library IEEE;
2 
use IEEE.STD_LOGIC_1164.ALL;
3 
use IEEE.STD_LOGIC_ARITH.ALL;
4 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
5 
 
6 
use work.globals.all;
7 
 
8 
entity sim_test is
9 
end sim_test;
10 
 
11 
architecture Behavioral of sim_test is
12 
 
13 4 kingmu 
        COMPONENT decode
14 2 kingmu 
        PORT(
15 4 kingmu 
    clk_i     : in  std_logic;
16 2 kingmu 
    rst_i     : in  std_logic;
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    encoded_i : in  std_logic_vector(3 downto 0);
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    nd_i      : in  std_logic;
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    decoded_o : out std_logic_vector(WORD_LENGTH-1 downto 0);
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    nd_o      : out std_logic
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                );
22 
        END COMPONENT;
23 
 
24 
-- For encoded_i:
25 
--
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-- 0000 = null
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-- 0001 = single one
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-- 0010 = single zero
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-- 0100 = double one
30 
-- 1000 = double zero
31 
 
32 4 kingmu 
  signal clk_i : std_logic;
33 2 kingmu 
  signal rst_i : std_logic;
34 
  signal encoded_i : std_logic_vector(3 downto 0) := "0000";
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  signal nd_i : std_logic := '0';
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  signal decoded_o : std_logic_vector(WORD_LENGTH-1 downto 0);
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  signal nd_o : std_logic;
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  constant half_period : time := 10 ns;
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  constant period : time := 2*half_period;
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  constant mid_single : time := (INTERVAL_MIN_SINGLE+INTERVAL_MAX_SINGLE)/2*period;
41 
 
42 
begin
43 
 
44 4 kingmu 
        Inst_decode: decode PORT MAP(
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                clk_i     => clk_i,
46 2 kingmu 
                rst_i     => rst_i,
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                encoded_i => encoded_i,
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    nd_i      => nd_i,
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                decoded_o => decoded_o,
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                nd_o      => nd_o
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        );
52 
 
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  process
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  begin
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-- below never changes
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    rst_i <= '1';
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    wait for MID_SINGLE;
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    rst_i <= '0';
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    encoded_i <= "0000";
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    wait for MID_SINGLE;
62 
 
63 
 
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    nd_i <= '1';
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    wait for period;
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    nd_i <= '0';
67 
 
68 
    wait for MID_SINGLE;
69 
 
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    encoded_i <= "1000"; -- 00
71 
 
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    nd_i <= '1';
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    wait for period;
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    nd_i <= '0';
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76 
    wait for MID_SINGLE;
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78 
-- above never changes
79 
 
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    encoded_i <= "0010"; --11
81 
 
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    nd_i <= '1';
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    wait for period;
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    nd_i <= '0';
85 
 
86 
    wait for MID_SINGLE;
87 
 
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    encoded_i <= "0100"; --0
89 
 
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    nd_i <= '1';
91 
    wait for period;
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    nd_i <= '0';
93 
 
94 
    wait for MID_SINGLE;
95 
 
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    encoded_i <= "0001"; --1
97 
 
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    nd_i <= '1';
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    wait for period;
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    nd_i <= '0';
101 
 
102 
    wait for MID_SINGLE;
103 
 
104 
    encoded_i <= "1000"; --00
105 
 
106 
    nd_i <= '1';
107 
    wait for period;
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    nd_i <= '0';
109 
 
110 
    wait for MID_SINGLE;
111 
 
112 
 
113 
    encoded_i <= "0001"; --1
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    nd_i <= '1';
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    wait for period;
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    nd_i <= '0';
118 
 
119 
    wait for MID_SINGLE;
120 
 
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    encoded_i <= "0100"; --0
122 
 
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    nd_i <= '1';
124 
    wait for period;
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    nd_i <= '0';
126 
 
127 
    wait for MID_SINGLE;
128 
 
129 
    encoded_i <= "0001"; --1
130 
 
131 
    nd_i <= '1';
132 
    wait for period;
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    nd_i <= '0';
134 
 
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    wait for MID_SINGLE;
136 
 
137 
    encoded_i <= "0100"; --0
138 
 
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    nd_i <= '1';
140 
    wait for period;
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    nd_i <= '0';
142 
 
143 
    wait for MID_SINGLE;
144 
 
145 
    encoded_i <= "0001"; --1
146 
 
147 
    nd_i <= '1';
148 
    wait for period;
149 
    nd_i <= '0';
150 
 
151 
    wait for MID_SINGLE;
152 
 
153 
    encoded_i <= "0100"; --0
154 
 
155 
    nd_i <= '1';
156 
    wait for period;
157 
    nd_i <= '0';
158 
 
159 
    wait for MID_SINGLE;
160 
 
161 
    encoded_i <= "0001"; --1
162 
 
163 
    nd_i <= '1';
164 
    wait for period;
165 
    nd_i <= '0';
166 
 
167 
    wait for MID_SINGLE;
168 
 
169 
    encoded_i <= "0100"; --0
170 
 
171 
    nd_i <= '1';
172 
    wait for period;
173 
    nd_i <= '0';
174 
 
175 
    wait for MID_SINGLE;
176 
 
177 
    encoded_i <= "0001"; --1
178 
 
179 
    nd_i <= '1';
180 
    wait for period;
181 
    nd_i <= '0';
182 
 
183 
    wait for MID_SINGLE;
184 
 
185 
    encoded_i <= "0100"; --0
186 
 
187 
    nd_i <= '1';
188 
    wait for period;
189 
    nd_i <= '0';
190 
 
191 
    wait for MID_SINGLE;
192 
 
193 
    encoded_i <= "0001"; --1
194 
 
195 
    nd_i <= '1';
196 
    wait for period;
197 
    nd_i <= '0';
198 
 
199 
    wait for MID_SINGLE;
200 
 
201 
    encoded_i <= "0100"; --0
202 
 
203 
    nd_i <= '1';
204 
    wait for period;
205 
    nd_i <= '0';
206 
 
207 
    wait for MID_SINGLE;
208 
 
209 
 
210 
 
211 
 
212 
 
213 
    encoded_i <= "0001"; --1
214 
 
215 
    nd_i <= '1';
216 
    wait for period;
217 
    nd_i <= '0';
218 
 
219 
    wait for MID_SINGLE;
220 
 
221 
    encoded_i <= "0100"; --0
222 
 
223 
    nd_i <= '1';
224 
    wait for period;
225 
    nd_i <= '0';
226 
 
227 
    wait for MID_SINGLE;
228 
 
229 
    encoded_i <= "0001"; --1
230 
 
231 
    nd_i <= '1';
232 
    wait for period;
233 
    nd_i <= '0';
234 
 
235 
    wait for MID_SINGLE;
236 
 
237 
    encoded_i <= "0100"; --0
238 
 
239 
    nd_i <= '1';
240 
    wait for period;
241 
    nd_i <= '0';
242 
 
243 
    wait for MID_SINGLE;
244 
 
245 
  end process;
246 
 
247 
  clock : process
248 
  begin
249 
    clk_i <= '1';
250 
    loop
251 
      wait for half_period;
252 
      clk_i <= not clk_i;
253 
    end loop;
254 
  end process;
255 
 
256 
end Behavioral;
257 
 

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