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[/] [manchesterwireless/] [trunk/] [simTest.vhd] - Blame information for rev 2

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1 2 kingmu
library ieee;
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use ieee.std_logic_1164.all;
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use work.globals.all;
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entity testSim is
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end testSim;
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architecture Behavioral of testSim is
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  component decodeManchester
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  port (
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    clk_i             : in  std_logic;
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    rst_i             : in  std_logic;
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    data_i            : in  std_logic;
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    q_o               : out std_logic_vector(WORD_LENGTH-1 downto 0);
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    ready_o           : out std_logic;
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    recieved_debug    : out std_logic_vector(3 downto 0);
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    waitforstart_rdy  : out std_logic
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  );
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  end component;
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  signal decode_output : std_logic_vector(WORD_LENGTH-1 downto 0);
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  -- up/down and left/right buffers
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  signal parity_o_buff, parity_o_reg : std_logic;
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  signal button_o_buff, button_o_reg : std_logic_vector(1 downto 0);
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  signal ud_buff1, ud_buff2, lr_buff1, lr_buff2 : std_logic_vector(6 downto 0);
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  signal ud_buff1_reg, ud_buff2_reg, lr_buff1_reg, lr_buff2_reg : std_logic_vector(6 downto 0);
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  signal char_select : integer range 0 to 3;
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  signal reset_manchester, soft_reset, ready_o_buff : std_logic;
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  signal clk_i             : std_logic;
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  signal rst_i             : std_logic := '1';
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  signal data_i            : std_logic;
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  signal ready_o           : std_logic;
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  signal character_o       : std_logic_vector(0 to 7);
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  signal anode_ctrl        : std_logic_vector(3 downto 0);
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  signal button_o          : std_logic_vector(1 downto 0);
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  signal parity_o          : std_logic;
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  signal recieved_debug    : std_logic_vector(3 downto 0);
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  signal waitforstart_rdy  : std_logic;
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  signal coded_rdy: std_logic;
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  signal coded : std_logic_vector(WORD_LENGTH-1 downto 0);
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  constant half_period : time := 10 ns;
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  constant period : time := 2*half_period;
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  constant mid_single : time := (INTERVAL_MIN_SINGLE+INTERVAL_MAX_SINGLE)/2*period;
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  constant WORD : std_logic_vector(28 downto 0) := "01100101100101010101010101010";
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begin
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  character_o(7) <= '1'; -- turn off decimal point
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  reset_manchester <=  rst_i or soft_reset;
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  ready_o <= ready_o_buff;
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  inst_decodeManchester: decodeManchester
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  port map(
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    clk_i   => clk_i,
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    rst_i   => reset_manchester,
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    data_i  => data_i,
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    q_o     => decode_output,
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    ready_o => ready_o_buff,
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    recieved_debug => recieved_debug,
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    waitforstart_rdy => waitforstart_rdy
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  );
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  -- the transmitter is sending the following UP/DOWN (4 bits)
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  -- then left/right (3 bits), and finally the parity (1 bit)
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  -- each command was ror onto the transmitter -- one at a time.
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  -- the decoder was written to assume that all the data was in 
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  -- being shifted to the transmitter from the right
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  -- thus, while we are transmitting:
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  -- initialize|up/down|left/right|buttons|parity|stop
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  -- the decoder will return results to us as
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  -- parity|buttons|left/right|up/down
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  -- bits 9|  8-7  |   6-4    |  3-0
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  -- decode up/down first digit (ones place)
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  with decode_output(3 downto 0) select
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     ud_buff1  <= "0000001" when x"D",  -- off
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                   "1001111" when x"F",  -- 1
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                   "0010010" when x"7",  -- 2
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                   "0000110" when x"5",  -- 3
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                   "1001100" when x"1",  -- 4
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                   "0100100" when x"3",  -- 5
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                   "0100000" when x"2",  -- 6
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                   "0001111" when x"6",  -- 7
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                   "0000000" when x"e",  -- 8
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                   "0000100" when x"c",  -- 9
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                   "0000001" when x"a",  -- 10
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                   "1001111" when x"b",  -- 11
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                   "0010010" when x"9",  -- 12
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                   "0000110" when x"8",  -- 13
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                   "1111111" when others; -- 'E'rror
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  -- decode up/down second digit (tens place)                 
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  with decode_output(3 downto 0) select
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     ud_buff2  <=  "1001111" when x"a",  -- 10
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                   "1001111" when x"b",  -- 11
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                   "1001111" when x"9",  -- 12
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                   "1001111" when x"8",  -- 13
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                   "1111111" when others;
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  -- decode left/right first digit
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  with decode_output(6 downto 4) select
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     lr_buff1  <=  "1001111" when "010",  -- -1
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                   "0010010" when "011",  -- -2
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                   "0000110" when "001",  -- -3
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                   "0000001" when "110",  -- 0
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                   "1001111" when "100",  -- 1
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                   "0010010" when "101",  -- 2
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                   "0000110" when "111",  -- 3
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                   "1111111" when others;
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  -- decode left/right sign digit
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  with decode_output(6 downto 4) select
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     lr_buff2  <=  "1111110" when "010",  -- -1
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                   "1111110" when "011",  -- -2
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                   "1111110" when "001",  -- -3
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                   "1111111" when others;
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  -- decode buttons                    
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  with decode_output(8 downto 7) select
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     button_o_buff  <=  "11" when "10",  -- 00
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                        "01" when "11",  -- 10
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                        "10" when "01",  -- 01
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                        "00" when "00",  -- 11
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                        "11" when others;
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  parity_o_buff <= decode_output(9);
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  parity_o <= parity_o_reg;
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  process (clk_i,rst_i)
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    variable counter : integer range 0 to 1023;
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  begin
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     if rst_i = '1' then
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       char_select <= 0;
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       counter := 0;
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       div_clk := '0';
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       soft_reset <= '0';
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     elsif (clk_i'event and clk_i = '1') then
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       -- register the output
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       if (ready_o_buff = '1') then
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        ud_buff1_reg <= ud_buff1;
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        ud_buff2_reg <= ud_buff2;
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        lr_buff1_reg <= lr_buff1;
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        lr_buff2_reg <= lr_buff2;
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        button_o_reg <= button_o_buff;
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        parity_o_reg <= parity_o_buff;
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        soft_reset <= '1';
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       else
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        soft_reset <= '0';
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       end if;
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       counter := counter + 1;
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       if (counter = 1023) then
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         -- this is for simulation
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         -- ModelSim does not want to roll over
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         if char_select < 3 then
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          char_select <= char_select + 1;
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         else
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          char_select <= 0;
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         end if;
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         counter := 0;
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       end if;
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     end if;
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  end process;
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  -- set output
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  with char_select select
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    character_o(0 to 6) <= ud_buff2_reg when 0,
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                           ud_buff1_reg when 1,
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                           lr_buff2_reg when 2,
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                           lr_buff1_reg when 3;
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  with char_select select
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    anode_ctrl <= "0111" when 0,
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                  "1011" when 1,
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                  "1101" when 2,
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                  "1110" when 3;
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  process
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  begin
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    wait for 5*period;
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    rst_i <= '0';
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    -- begin transmission header 
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    data_i <= '1';
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    wait for 5*MID_SINGLE;
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    data_i <= '0';
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    wait for MID_SINGLE;
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    -- end transmission header
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    for i in WORD'left downto 0 loop
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      data_i <= WORD(i);
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      wait for MID_SINGLE;
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    end loop;
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    data_i <= '1';
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    wait for MID_SINGLE;
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    rst_i <= '1';
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    wait for 5*period;
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  end process;
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  clock : process
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  begin
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    clk_i <= '1';
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    loop
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      wait for half_period;
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      clk_i <= not clk_i;
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    end loop;
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  end process;
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end Behavioral;
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