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[/] [marca/] [tags/] [INITIAL/] [vhdl/] [uart_reverse.s] - Blame information for rev 8

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Line No. Rev Author Line
1 2 jeunes2
.data
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        data 0x0A
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        data 0x0D
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buffer:
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.text
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;;; initialization
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        ldib    r0, -8          ; config/status
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        ldib    r1, -6          ; data
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        ldil    r2,  lo(buffer) ; buffer address
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        ldih    r2,  hi(buffer) ; buffer address
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        ldib    r3,  0x0A       ; newline character
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        ldib    r4,  0x0D       ; carriage return
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        ldib    r5,  0           ; mode
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        ldib    r7,  isr        ; register isr
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        stvec   r7,  3
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        ldib    r7, (1 << 3)    ; enable receive interrupts
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        store   r7,  r0
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        sei                     ; enable interrupts
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;;; loop forever
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loop:   br loop
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;;; ISR
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isr:
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        cmpi    r5, 0            ; check mode
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        brnz    write_mode
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;;; reading
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read_mode:
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        load    r7, r1          ; read data
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        cmp     r7, r3          ; change mode upon newline
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        brnz    read_CR
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        ldib    r7, (1 << 2)    ; do the change
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        store   r7, r0
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        ldib    r5, 1
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        reti
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read_CR:
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        cmp     r7, r4          ; ignore carriage return
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        brnz    read_cont
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        reti
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read_cont:
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        storel  r7, r2          ; store date
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        addi    r2,  1
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        reti
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;;; writing
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write_mode:
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        addi    r2, -1
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        cmpi    r2, -1          ; change mode if there is no more data
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        brnz    write_cont
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        ldil    r2,  lo(buffer) ; correct pointer to buffer
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        ldih    r2,  hi(buffer)
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        ldib    r7, (1 << 3)    ; do the change
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        store   r7, r0
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        ldib    r5, 0
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        reti
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write_cont:
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        loadl   r7, r2          ; write data
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        store   r7, r1
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        reti
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