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\documentclass[10pt, twoside, a4paper]{article}
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\usepackage{longtable}
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\newcommand{\shl}{\ensuremath{<\!\!<}}
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\newcommand{\shr}{\ensuremath{>\!\!>\!\!>}}
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\newcommand{\sar}{\ensuremath{>\!\!>}}
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\newcommand{\at}{\ensuremath{\!\!:\!\!}}
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\title{marca - McAdam's RISC Computer Architecture\\Instruction Set Architecture}
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\author{Kenan Bilic, Roland Kammerer, Wolfgang Puffitsch}
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\begin{document}
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\maketitle
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\section{General}
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\begin{itemize}
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\item 16 16-bit registers, r0 \ldots r15
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\item any register as return address
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\item flags: Z, C, V, N
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\begin{itemize}
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\item Z: all bits of the last result are zero
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\item C: ``17$^{th}$ bit'' of the last result
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\item N: 16$^{th}$ bit of the last result
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\item V: overflow, after sub/cmp it is $r1 \at 15 \oplus r2 \at 15
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\oplus N \oplus C$, the latter two according to the result,
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other operations accordingly
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\item I: allow interrupts
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\item P: parity of the last result
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\end{itemize}
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Flags are written where meaningful: P and Z are computed whenever
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a register is written, arithmetic operations may change C, N and
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V, interrupts clear I upon entry.
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\item flags are stored and restored upon interrupt entry and exit
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to/from ``shflags'' (shadow flags)
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\item separate registers for interrupt vectors - read and written
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through ``ldvec'' / ``stvec''
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\item Some parts come from the Alpha architecture. The handling of
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branches is inspired by the Intel x86.
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\item External hardware modules shall be mapped to the highest
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memory locations.
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\end{itemize}
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The processor uses a Harvard architecture; although it has not
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prevailed in mainstream-architectures, it is still used in embedded
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processors such as the Atmel AVR. The separation of code- and
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data-memory is not flexible enough for mainstream systems, but with
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small embedded processors the program code tends to be fixed
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anyway. A Harvard architecture enables the processor to make use of
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more memory (which is an issue when the address space is limited to
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64k), and the program code can be read from a ROM directly. A
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transient failure thus cannot destroy the program by overwriting its
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code section.
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\clearpage
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\section{Instruction Set}
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{\small
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\begin{longtable}{llp{.62\textwidth}}
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Instruction & Opcode & Semantics \\
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add r1, r2, r3 & \texttt{0000} & $r1 + r2 \rightarrow r3$ \\
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sub r1, r2, r3 & \texttt{0001} & $r1 - r2 \rightarrow r3$ \\
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addc r1, r2, r3 & \texttt{0010} & $r1 + r2 + C \rightarrow r3$ \\
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subc r1, r2, r3 & \texttt{0011} & $r1 - r2 - C \rightarrow r3$ \\
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and r1, r2, r3 & \texttt{0100} & $r1 \wedge r2 \rightarrow r3$ \\
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or r1, r2, r3 & \texttt{0101} & $r1 \vee r2 \rightarrow r3$ \\
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xor r1, r2, r3 & \texttt{0110} & $r1 \oplus r2 \rightarrow r3$ \\
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mul r1, r2, r3 & \texttt{0111} & $r1 * r2 \rightarrow r3$ \\
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div r1, r2, r3 & \texttt{1000} & $r1 \div r2 \rightarrow r3$ \\
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udiv r1, r2, r3 & \texttt{1001} & $r1 \div r2 \rightarrow r3, \textnormal{unsigned} $ \\
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ldil r1, n8 & \texttt{1010} & $(r1 \wedge \texttt{0xff00}) \vee n8 \rightarrow r1, -128 \leq n8 \leq 255 $ \\
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ldih r1, n8 & \texttt{1011} & $(r1 \wedge \texttt{0x00ff}) \vee (n8 \shl 8) \rightarrow r1, -128 \leq n8 \leq 255 $ \\
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ldib r1, n8 & \texttt{1100} & $n8 \rightarrow r1, -128 \leq n8 \leq 127$ \\
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\hline
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mov r1, r2 & \texttt{11010000} & $r2 \rightarrow r1$ \\
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mod r1, r2 & \texttt{11010001} & $r1\ \textnormal{mod}\ r2 \rightarrow r1$ \\
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umod r1, r2 & \texttt{11010010} & $r1\ \textnormal{mod}\ r2 \rightarrow r1, \textnormal{unsigned} $ \\
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not r1, r2 & \texttt{11010011} & $\lnot r2 \rightarrow r1$ \\
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neg r1, r2 & \texttt{11010100} & $-r1 \rightarrow r2$ \\
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cmp r1, r2 & \texttt{11010101} & $r1 - r2, \textnormal{sets flags}$ \\
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addi r1, n4 & \texttt{11010110} & $r1 + n4 \rightarrow r1, -8 \leq n4 \leq 7$ \\
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cmpi r1, n4 & \texttt{11010111} & $r1 - n4, \textnormal{sets flags}, -8 \leq n4 \leq 7$ \\
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shl r1, r2 & \texttt{11011000} & $r1 \shl r2 \rightarrow r1$ \\
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shr r1, r2 & \texttt{11011001} & $r1 \shr r2 \rightarrow r1$ \\
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sar r1, r2 & \texttt{11011010} & $r1 \sar r2 \rightarrow r1$ \\
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rolc r1, r2 & \texttt{11011011} & $(r1 \shl r2) \vee (C \shl (r2-1)) \vee (r1 \shr (16-r2-1))$ \\
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rorc r1, r2 & \texttt{11011100} & $(r1 \shr r2) \vee (C \shl (16-r2)) \vee (r1 \shl (16-r2-1))$ \\
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bset r1, n4 & \texttt{11011101} & $r1 \vee (1 \shl n4) \rightarrow r1, 0 \leq n4 \leq 15$ \\
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bclr r1, n4 & \texttt{11011110} & $r1 \wedge \lnot (1 \shl n4) \rightarrow r1, 0 \leq n4 \leq 15$ \\
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btest r1, n4 & \texttt{11011111} & $(r1 \shr n4) \wedge 1 \rightarrow Z, 0 \leq n4 \leq 15$ \\
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\hline
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load r1, r2 & \texttt{11100000} & $[r2] \at [r2+1] \rightarrow r1$ \\
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store r1, r2 & \texttt{11100001} & $r1 \rightarrow [r2] \at [r2+1]$ \\
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loadl r1, r2 & \texttt{11100010} & $(r1 \wedge \texttt{0xff00}) \vee [r2] \rightarrow r1$ \\
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loadh r1, r2 & \texttt{11100011} & $(r1 \wedge \texttt{0x00ff}) \vee ([r2] \shl 8) \rightarrow r1$ \\
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loadb r1, r2 & \texttt{11100100} & $[r2] \rightarrow r1, \textnormal{signed}$ \\
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storel r1, r2 & \texttt{11100101} & $(r1 \wedge \texttt{0x00ff}) \rightarrow [r2]$ \\
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storeh r1, r2 & \texttt{11100110} & $(r1 \shr 8) \rightarrow [r2]$ \\
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call r1, r2 & \texttt{11101000} & $r1 \rightarrow pc, pc \rightarrow r2$ \\
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\hline
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br n8 & \texttt{11110000} & $pc + n8 \rightarrow pc, -128 \leq n8 \leq 127$ \\
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brz n8 & \texttt{11110001} & $Z = 1 \Rightarrow pc + n8 \rightarrow pc, -128 \leq n8 \leq 127$ \\
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brnz n8 & \texttt{11110010} & $Z = 0 \Rightarrow pc + n8 \rightarrow pc, -128 \leq n8 \leq 127$ \\
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brle n8 & \texttt{11110011} & $(Z = 1) \vee (N \not = V) \Rightarrow pc + n8 \rightarrow pc, -128 \leq n8 \leq 127$ \\
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brlt n8 & \texttt{11110100} & $(Z = 0) \wedge (N \not = V) \Rightarrow pc + n8 \rightarrow pc, -128 \leq n8 \leq 127$ \\
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brge n8 & \texttt{11110101} & $(Z = 1) \vee (N = V) \Rightarrow pc + n8 \rightarrow pc, -128 \leq n8 \leq 127$ \\
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brgt n8 & \texttt{11110110} & $(Z = 0) \wedge (N = V) \Rightarrow pc + n8 \rightarrow pc, -128 \leq n8 \leq 127$ \\
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brule n8 & \texttt{11110111} & $(Z = 1) \vee (C = 1) \Rightarrow pc + n8 \rightarrow pc, -128 \leq n8 \leq 127$ \\
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brult n8 & \texttt{11111000} & $(Z = 0) \wedge (C = 1) \Rightarrow pc + n8 \rightarrow pc, -128 \leq n8 \leq 127$ \\
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bruge n8 & \texttt{11111001} & $(Z = 1) \vee (C = 0) \Rightarrow pc + n8 \rightarrow pc, -128 \leq n8 \leq 127$ \\
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brugt n8 & \texttt{11111010} & $(Z = 0) \wedge (C = 0) \Rightarrow pc + n8 \rightarrow pc, -128 \leq n8 \leq 127$ \\
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sext r1, r2 & \texttt{11111011} & $(r1 \shl 8) \sar 8 \rightarrow r2$ \\
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ldvec r1, n4 & \texttt{11111100} & $\textnormal{interrupt vector}\ n4 \rightarrow r1, 0 \leq n4 \leq 15$ \\
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stvec r1, n4 & \texttt{11111101} & $r1 \rightarrow \textnormal{interrupt vector}\ n4, 0 \leq n4 \leq 15$ \\
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\hline
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jmp r1 & \texttt{111111100000} & $r1 \rightarrow pc$ \\
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jmpz r1 & \texttt{111111100001} & $Z = 1 \Rightarrow r1 \rightarrow pc$ \\
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jmpnz r1 & \texttt{111111100010} & $Z = 0 \Rightarrow r1 \rightarrow pc$ \\
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jmple r1 & \texttt{111111100011} & $(Z = 1) \vee (N \not = V) \Rightarrow r1 \rightarrow pc$ \\
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jmplt r1 & \texttt{111111100100} & $(Z = 0) \wedge (N \not = V) \Rightarrow r1 \rightarrow pc$ \\
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jmpge r1 & \texttt{111111100101} & $(Z = 1) \vee (N = V) \Rightarrow r1 \rightarrow pc$ \\
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jmpgt r1 & \texttt{111111100110} & $(Z = 0) \wedge (N = V) \Rightarrow r1 \rightarrow pc$ \\
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jmpule r1 & \texttt{111111100111} & $(Z = 1) \vee (C = 1) \Rightarrow r1 \rightarrow pc$ \\
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jmpult r1 & \texttt{111111101000} & $(Z = 0) \wedge (C = 1) \Rightarrow r1 \rightarrow pc$ \\
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jmpuge r1 & \texttt{111111101001} & $(Z = 1) \vee (C = 0) \Rightarrow r1 \rightarrow pc$ \\
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jmpugt r1 & \texttt{111111101010} & $(Z = 0) \wedge (C = 0) \Rightarrow r1 \rightarrow pc$ \\
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intr n4 & \texttt{111111101011} & $\textnormal{interrupt vector}\ n4 \rightarrow pc, pc \rightarrow ira, flags \rightarrow shflags, 0 \leq n4 \leq 15$ \\
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getira r1 & \texttt{111111101100} & $ira \rightarrow r1$ \\
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setira r1 & \texttt{111111101101} & $r1 \rightarrow ira$ \\
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getfl r1 & \texttt{111111101110} & $flags \rightarrow r1$ \\
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setfl r1 & \texttt{111111101111} & $r1 \rightarrow flags$ \\
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getshfl r1 & \texttt{111111110000} & $shflags \rightarrow r1$ \\
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setshfl r1 & \texttt{111111110001} & $r1 \rightarrow shflags$ \\
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\hline
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reti & \texttt{1111111111110000} & $ira \rightarrow pc, shflags \rightarrow flags$ \\
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nop & \texttt{1111111111110001} & $\textnormal{do nothing}$ \\
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sei & \texttt{1111111111110010} & $1 \rightarrow I$ \\
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cli & \texttt{1111111111110011} & $0 \rightarrow I$ \\
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error & \texttt{1111111111111111} & $\textnormal{invalid operation}$ \\
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\end{longtable}}
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\subsection{NOTES}
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\begin{itemize}
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\item Apart from the standard operators, the following notation is
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used in the table above:
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\begin{itemize}
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\item \shl, \shr, \sar are shifting operators, with semantics as in Java
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\item $[x]$ means accessing memory location $x$, 8 bits wide
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\item $x \at y$ means concatenating $x$ and $y$, in the sense of
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forming a 16-bit value from two 8-bit values
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\end{itemize}
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\item Modulo does not follow the patterns for ``div'' and ``udiv'',
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because there was not enough room for two more 3-operand
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operations. The assembler accepts the mnemonic with 3 registers as
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operands and substitute it with the according ``mov'' and ``mod''
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instructions.
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\end{itemize}
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\clearpage
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\subsection{Instruction formats}
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The following formats for instructions are to be used:
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\begin{center}
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\begin{tabular}{|p{1in}|p{1in}|p{1in}|p{1in}|}
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\hline
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Bits 15 \ldots 12 & Bits 11 \ldots 8 & Bits 7 \ldots 4 & Bits 3 \ldots 0 \\
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\hline
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Opcode & r3 & r2 & r1 \\
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\hline
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Opcode & \multicolumn{2}{|l|}{n8} & r1 \\
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\hline
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\multicolumn{2}{|l|}{Opcode} & r2 & r1 \\
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\hline
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\multicolumn{2}{|l|}{Opcode} & n4 & r1 \\
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\hline
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\multicolumn{2}{|l|}{Opcode} & \multicolumn{2}{|l|}{n8} \\
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\hline
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\multicolumn{3}{|l|}{Opcode} & r1 \\
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\hline
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\multicolumn{3}{|l|}{Opcode} & n4 \\
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\hline
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\multicolumn{4}{|l|}{Opcode} \\
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\hline
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\end{tabular}
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\end{center}
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\section{Versions Of This Document}
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2006-10-04: Draft version \textbf{0.1}
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\noindent
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2006-10-05: Draft version \textbf{0.2}
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\begin{itemize}
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\item rearrangement of some ops
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\end{itemize}
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\noindent
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2006-10-11: Draft version \textbf{0.3}
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\begin{itemize}
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\item replaced ``ror''/``rol'' with ``mod''/``umod''
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\item refined considerations of direction flag
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\item proposal for priorities of implementation
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\end{itemize}
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\noindent
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2006-10-28: Draft version \textbf{0.4}
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\begin{itemize}
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\item settled to singed loads
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\item settled to shifts by registers
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\item dropped ``push''/``pop''; the secondary result would cause a
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considerable overhead
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\item specified pipelining
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\end{itemize}
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\noindent
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2006-10-30: Draft version \textbf{0.5}
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\begin{itemize}
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\item added shflags to ease interrupt (and stack) handling
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\item a few refinements
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\end{itemize}
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\noindent
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2006-12-02: Draft version \textbf{0.6}
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\begin{itemize}
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\item the first register is the target with ``mov'' and ``not'' now.
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\item now the second register is always the address when accessing memory
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\item reversed order with immediate loads
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\item ``ldvec'' and ``stvec'' use the same order now
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\item fixed instruction format for immediate loads
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\end{itemize}
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\noindent
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2006-12-14: Draft version \textbf{0.7}
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\begin{itemize}
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\item dropped ``ldpgm'' in favor of a ROM which is mapped to the
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ordinary memory space
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\item moved section about pipelinign to the implementation document
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\item removed note about interrupts; they are implemented already
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\end{itemize}
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\end{document}
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