| 1 |
2 |
jeunes2 |
-- This file is part of the marca processor.
|
| 2 |
|
|
-- Copyright (C) 2007 Wolfgang Puffitsch
|
| 3 |
|
|
|
| 4 |
|
|
-- This program is free software; you can redistribute it and/or modify it
|
| 5 |
|
|
-- under the terms of the GNU Library General Public License as published
|
| 6 |
|
|
-- by the Free Software Foundation; either version 2, or (at your option)
|
| 7 |
|
|
-- any later version.
|
| 8 |
|
|
|
| 9 |
|
|
-- This program is distributed in the hope that it will be useful,
|
| 10 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 11 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
| 12 |
|
|
-- Library General Public License for more details.
|
| 13 |
|
|
|
| 14 |
|
|
-- You should have received a copy of the GNU Library General Public
|
| 15 |
|
|
-- License along with this program; if not, write to the Free Software
|
| 16 |
|
|
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
| 17 |
|
|
|
| 18 |
|
|
-------------------------------------------------------------------------------
|
| 19 |
|
|
-- MARCA decode stage
|
| 20 |
|
|
-------------------------------------------------------------------------------
|
| 21 |
|
|
-- architecture for the instruction-decode pipeline stage
|
| 22 |
|
|
-------------------------------------------------------------------------------
|
| 23 |
|
|
|
| 24 |
|
|
-------------------------------------------------------------------------------
|
| 25 |
|
|
-- Wolfgang Puffitsch
|
| 26 |
|
|
-- Computer Architecture Lab, Group 3
|
| 27 |
|
|
-------------------------------------------------------------------------------
|
| 28 |
|
|
|
| 29 |
|
|
library IEEE;
|
| 30 |
|
|
use IEEE.std_logic_1164.all;
|
| 31 |
|
|
use IEEE.numeric_std.all;
|
| 32 |
|
|
|
| 33 |
|
|
use work.marca_pkg.all;
|
| 34 |
|
|
|
| 35 |
|
|
architecture behaviour of decode is
|
| 36 |
|
|
|
| 37 |
|
|
signal pc_reg : std_logic_vector(REG_WIDTH-1 downto 0);
|
| 38 |
|
|
signal dest_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
|
| 39 |
|
|
signal instr_reg : std_logic_vector(PDATA_WIDTH-1 downto 0);
|
| 40 |
|
|
|
| 41 |
|
|
signal src1_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
|
| 42 |
|
|
signal src2_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
|
| 43 |
|
|
|
| 44 |
|
|
component regfile is
|
| 45 |
|
|
port (
|
| 46 |
|
|
clock : in std_logic;
|
| 47 |
|
|
reset : in std_logic;
|
| 48 |
|
|
hold : in std_logic;
|
| 49 |
|
|
rd1_addr : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
|
| 50 |
|
|
rd2_addr : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
|
| 51 |
|
|
rd1_val : out std_logic_vector(REG_WIDTH-1 downto 0);
|
| 52 |
|
|
rd2_val : out std_logic_vector(REG_WIDTH-1 downto 0);
|
| 53 |
|
|
wr_ena : in std_logic;
|
| 54 |
|
|
wr_addr : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
|
| 55 |
|
|
wr_val : in std_logic_vector(REG_WIDTH-1 downto 0));
|
| 56 |
|
|
end component;
|
| 57 |
|
|
|
| 58 |
|
|
begin -- behaviour
|
| 59 |
|
|
|
| 60 |
|
|
regfile_unit : regfile
|
| 61 |
|
|
port map (
|
| 62 |
|
|
clock => clock,
|
| 63 |
|
|
reset => reset,
|
| 64 |
|
|
hold => hold,
|
| 65 |
|
|
rd1_addr => src1_reg,
|
| 66 |
|
|
rd2_addr => src2_reg,
|
| 67 |
|
|
rd1_val => op1,
|
| 68 |
|
|
rd2_val => op2,
|
| 69 |
|
|
wr_ena => wr_ena,
|
| 70 |
|
|
wr_addr => wr_dest,
|
| 71 |
|
|
wr_val => wr_val);
|
| 72 |
|
|
|
| 73 |
|
|
syn_proc: process (clock, reset)
|
| 74 |
|
|
begin -- process syn_proc
|
| 75 |
|
|
if reset = RESET_ACTIVE then -- asynchronous reset (active low)
|
| 76 |
|
|
pc_reg <= (others => '0');
|
| 77 |
|
|
dest_reg <= (others => '0');
|
| 78 |
|
|
instr_reg <= OPC_PFX_C & OPC_PFX_C2 & OPC_PFX_C2a & OPC_NOP;
|
| 79 |
|
|
src1_reg <= (others => '0');
|
| 80 |
|
|
src2_reg <= (others => '0');
|
| 81 |
|
|
elsif clock'event and clock = '1' then -- rising clock edge
|
| 82 |
|
|
if hold = '0' then
|
| 83 |
|
|
if stall = '1' then
|
| 84 |
|
|
pc_reg <= (others => '0');
|
| 85 |
|
|
dest_reg <= (others => '0');
|
| 86 |
|
|
instr_reg <= OPC_PFX_C & OPC_PFX_C2 & OPC_PFX_C2a & OPC_NOP;
|
| 87 |
|
|
src1_reg <= (others => '0');
|
| 88 |
|
|
src2_reg <= (others => '0');
|
| 89 |
|
|
else
|
| 90 |
|
|
pc_reg <= pc_in;
|
| 91 |
|
|
dest_reg <= dest_in;
|
| 92 |
|
|
instr_reg <= instr;
|
| 93 |
|
|
src1_reg <= src1_in;
|
| 94 |
|
|
src2_reg <= src2_in;
|
| 95 |
|
|
end if;
|
| 96 |
|
|
end if;
|
| 97 |
|
|
end if;
|
| 98 |
|
|
end process syn_proc;
|
| 99 |
|
|
|
| 100 |
|
|
feedthrough: process (pc_reg, src1_reg, src2_reg)
|
| 101 |
|
|
begin -- process feedthrough
|
| 102 |
|
|
pc_out <= pc_reg;
|
| 103 |
|
|
src1_out <= src1_reg;
|
| 104 |
|
|
src2_out <= src2_reg;
|
| 105 |
|
|
end process feedthrough;
|
| 106 |
|
|
|
| 107 |
|
|
do_decode: process (instr_reg, src1_reg, src2_reg, dest_reg)
|
| 108 |
|
|
begin -- process
|
| 109 |
|
|
|
| 110 |
|
|
-- all unknown opcodes trigger interrupt EXC_ERR
|
| 111 |
|
|
imm <= std_logic_vector(to_unsigned(EXC_ERR, REG_WIDTH));
|
| 112 |
|
|
dest_out <= dest_reg;
|
| 113 |
|
|
aop <= ALU_INTR;
|
| 114 |
|
|
mop <= MEM_NOP;
|
| 115 |
|
|
iop <= INTR_INTR;
|
| 116 |
|
|
unit <= UNIT_INTR;
|
| 117 |
|
|
target <= TARGET_PC;
|
| 118 |
|
|
|
| 119 |
|
|
case instr_reg(PDATA_WIDTH-1 downto PDATA_WIDTH-4) is
|
| 120 |
|
|
when
|
| 121 |
|
|
OPC_ADD => aop <= ALU_ADD;
|
| 122 |
|
|
mop <= MEM_NOP;
|
| 123 |
|
|
iop <= INTR_NOP;
|
| 124 |
|
|
unit <= UNIT_ALU;
|
| 125 |
|
|
target <= TARGET_REGISTER;
|
| 126 |
|
|
dest_out <= dest_reg;
|
| 127 |
|
|
when
|
| 128 |
|
|
OPC_SUB => aop <= ALU_SUB;
|
| 129 |
|
|
mop <= MEM_NOP;
|
| 130 |
|
|
iop <= INTR_NOP;
|
| 131 |
|
|
unit <= UNIT_ALU;
|
| 132 |
|
|
target <= TARGET_REGISTER;
|
| 133 |
|
|
dest_out <= dest_reg;
|
| 134 |
|
|
when
|
| 135 |
|
|
OPC_ADDC => aop <= ALU_ADDC;
|
| 136 |
|
|
mop <= MEM_NOP;
|
| 137 |
|
|
iop <= INTR_NOP;
|
| 138 |
|
|
unit <= UNIT_ALU;
|
| 139 |
|
|
target <= TARGET_REGISTER;
|
| 140 |
|
|
dest_out <= dest_reg;
|
| 141 |
|
|
when
|
| 142 |
|
|
OPC_SUBC => aop <= ALU_SUBC;
|
| 143 |
|
|
mop <= MEM_NOP;
|
| 144 |
|
|
iop <= INTR_NOP;
|
| 145 |
|
|
unit <= UNIT_ALU;
|
| 146 |
|
|
target <= TARGET_REGISTER;
|
| 147 |
|
|
dest_out <= dest_reg;
|
| 148 |
|
|
when
|
| 149 |
|
|
OPC_AND => aop <= ALU_AND;
|
| 150 |
|
|
mop <= MEM_NOP;
|
| 151 |
|
|
iop <= INTR_NOP;
|
| 152 |
|
|
unit <= UNIT_ALU;
|
| 153 |
|
|
target <= TARGET_REGISTER;
|
| 154 |
|
|
dest_out <= dest_reg;
|
| 155 |
|
|
when
|
| 156 |
|
|
OPC_OR => aop <= ALU_OR;
|
| 157 |
|
|
mop <= MEM_NOP;
|
| 158 |
|
|
iop <= INTR_NOP;
|
| 159 |
|
|
unit <= UNIT_ALU;
|
| 160 |
|
|
target <= TARGET_REGISTER;
|
| 161 |
|
|
dest_out <= dest_reg;
|
| 162 |
|
|
when
|
| 163 |
|
|
OPC_XOR => aop <= ALU_XOR;
|
| 164 |
|
|
mop <= MEM_NOP;
|
| 165 |
|
|
iop <= INTR_NOP;
|
| 166 |
|
|
unit <= UNIT_ALU;
|
| 167 |
|
|
target <= TARGET_REGISTER;
|
| 168 |
|
|
dest_out <= dest_reg;
|
| 169 |
|
|
when
|
| 170 |
|
|
OPC_MUL => aop <= ALU_MUL;
|
| 171 |
|
|
mop <= MEM_NOP;
|
| 172 |
|
|
iop <= INTR_NOP;
|
| 173 |
|
|
unit <= UNIT_ALU;
|
| 174 |
|
|
target <= TARGET_REGISTER;
|
| 175 |
|
|
dest_out <= dest_reg;
|
| 176 |
|
|
when
|
| 177 |
|
|
OPC_DIV => aop <= ALU_DIV;
|
| 178 |
|
|
mop <= MEM_NOP;
|
| 179 |
|
|
iop <= INTR_NOP;
|
| 180 |
|
|
unit <= UNIT_ALU;
|
| 181 |
|
|
target <= TARGET_REGISTER;
|
| 182 |
|
|
dest_out <= dest_reg;
|
| 183 |
|
|
when
|
| 184 |
|
|
OPC_UDIV => aop <= ALU_UDIV;
|
| 185 |
|
|
mop <= MEM_NOP;
|
| 186 |
|
|
iop <= INTR_NOP;
|
| 187 |
|
|
unit <= UNIT_ALU;
|
| 188 |
|
|
target <= TARGET_REGISTER;
|
| 189 |
|
|
dest_out <= dest_reg;
|
| 190 |
|
|
when
|
| 191 |
|
|
OPC_LDIL => imm <= std_logic_vector(resize(signed(dest_reg & src2_reg), REG_WIDTH));
|
| 192 |
|
|
aop <= ALU_LDIL;
|
| 193 |
|
|
mop <= MEM_NOP;
|
| 194 |
|
|
iop <= INTR_NOP;
|
| 195 |
|
|
unit <= UNIT_ALU;
|
| 196 |
|
|
target <= TARGET_REGISTER;
|
| 197 |
|
|
dest_out <= src1_reg;
|
| 198 |
|
|
when
|
| 199 |
|
|
OPC_LDIH => imm <= std_logic_vector(resize(signed(dest_reg & src2_reg), REG_WIDTH));
|
| 200 |
|
|
aop <= ALU_LDIH;
|
| 201 |
|
|
mop <= MEM_NOP;
|
| 202 |
|
|
iop <= INTR_NOP;
|
| 203 |
|
|
unit <= UNIT_ALU;
|
| 204 |
|
|
target <= TARGET_REGISTER;
|
| 205 |
|
|
dest_out <= src1_reg;
|
| 206 |
|
|
when
|
| 207 |
|
|
OPC_LDIB => imm <= std_logic_vector(resize(signed(dest_reg & src2_reg), REG_WIDTH));
|
| 208 |
|
|
aop <= ALU_LDIB;
|
| 209 |
|
|
mop <= MEM_NOP;
|
| 210 |
|
|
iop <= INTR_NOP;
|
| 211 |
|
|
unit <= UNIT_ALU;
|
| 212 |
|
|
target <= TARGET_REGISTER;
|
| 213 |
|
|
dest_out <= src1_reg;
|
| 214 |
|
|
|
| 215 |
|
|
when
|
| 216 |
|
|
OPC_PFX_A =>
|
| 217 |
|
|
case instr_reg(PDATA_WIDTH-5 downto PDATA_WIDTH-8) is
|
| 218 |
|
|
when
|
| 219 |
|
|
OPC_MOV => aop <= ALU_MOV;
|
| 220 |
|
|
mop <= MEM_NOP;
|
| 221 |
|
|
iop <= INTR_NOP;
|
| 222 |
|
|
unit <= UNIT_ALU;
|
| 223 |
|
|
target <= TARGET_REGISTER;
|
| 224 |
|
|
dest_out <= src1_reg;
|
| 225 |
|
|
when
|
| 226 |
|
|
OPC_MOD => aop <= ALU_MOD;
|
| 227 |
|
|
mop <= MEM_NOP;
|
| 228 |
|
|
iop <= INTR_NOP;
|
| 229 |
|
|
unit <= UNIT_ALU;
|
| 230 |
|
|
target <= TARGET_REGISTER;
|
| 231 |
|
|
dest_out <= src1_reg;
|
| 232 |
|
|
when
|
| 233 |
|
|
OPC_UMOD => aop <= ALU_UMOD;
|
| 234 |
|
|
mop <= MEM_NOP;
|
| 235 |
|
|
iop <= INTR_NOP;
|
| 236 |
|
|
unit <= UNIT_ALU;
|
| 237 |
|
|
target <= TARGET_REGISTER;
|
| 238 |
|
|
dest_out <= src1_reg;
|
| 239 |
|
|
when
|
| 240 |
|
|
OPC_NOT => aop <= ALU_NOT;
|
| 241 |
|
|
mop <= MEM_NOP;
|
| 242 |
|
|
iop <= INTR_NOP;
|
| 243 |
|
|
unit <= UNIT_ALU;
|
| 244 |
|
|
target <= TARGET_REGISTER;
|
| 245 |
|
|
dest_out <= src1_reg;
|
| 246 |
|
|
when
|
| 247 |
|
|
OPC_NEG => aop <= ALU_NEG;
|
| 248 |
|
|
mop <= MEM_NOP;
|
| 249 |
|
|
iop <= INTR_NOP;
|
| 250 |
|
|
unit <= UNIT_ALU;
|
| 251 |
|
|
target <= TARGET_REGISTER;
|
| 252 |
|
|
dest_out <= src1_reg;
|
| 253 |
|
|
when
|
| 254 |
|
|
OPC_CMP => aop <= ALU_SUB; -- it's the same
|
| 255 |
|
|
mop <= MEM_NOP;
|
| 256 |
|
|
iop <= INTR_NOP;
|
| 257 |
|
|
unit <= UNIT_ALU;
|
| 258 |
|
|
target <= TARGET_NONE;
|
| 259 |
|
|
dest_out <= src1_reg;
|
| 260 |
|
|
when
|
| 261 |
|
|
OPC_ADDI => imm <= std_logic_vector(resize(signed(src2_reg), REG_WIDTH));
|
| 262 |
|
|
aop <= ALU_ADDI;
|
| 263 |
|
|
mop <= MEM_NOP;
|
| 264 |
|
|
iop <= INTR_NOP;
|
| 265 |
|
|
unit <= UNIT_ALU;
|
| 266 |
|
|
target <= TARGET_REGISTER;
|
| 267 |
|
|
dest_out <= src1_reg;
|
| 268 |
|
|
when
|
| 269 |
|
|
OPC_CMPI => imm <= std_logic_vector(resize(signed(src2_reg), REG_WIDTH));
|
| 270 |
|
|
aop <= ALU_CMPI;
|
| 271 |
|
|
mop <= MEM_NOP;
|
| 272 |
|
|
iop <= INTR_NOP;
|
| 273 |
|
|
unit <= UNIT_ALU;
|
| 274 |
|
|
target <= TARGET_NONE;
|
| 275 |
|
|
dest_out <= src1_reg;
|
| 276 |
|
|
when
|
| 277 |
|
|
OPC_SHL => aop <= ALU_SHL;
|
| 278 |
|
|
mop <= MEM_NOP;
|
| 279 |
|
|
iop <= INTR_NOP;
|
| 280 |
|
|
unit <= UNIT_ALU;
|
| 281 |
|
|
target <= TARGET_REGISTER;
|
| 282 |
|
|
dest_out <= src1_reg;
|
| 283 |
|
|
when
|
| 284 |
|
|
OPC_SHR => aop <= ALU_SHR;
|
| 285 |
|
|
mop <= MEM_NOP;
|
| 286 |
|
|
iop <= INTR_NOP;
|
| 287 |
|
|
unit <= UNIT_ALU;
|
| 288 |
|
|
target <= TARGET_REGISTER;
|
| 289 |
|
|
dest_out <= src1_reg;
|
| 290 |
|
|
when
|
| 291 |
|
|
OPC_SAR => aop <= ALU_SAR;
|
| 292 |
|
|
mop <= MEM_NOP;
|
| 293 |
|
|
iop <= INTR_NOP;
|
| 294 |
|
|
unit <= UNIT_ALU;
|
| 295 |
|
|
target <= TARGET_REGISTER;
|
| 296 |
|
|
dest_out <= src1_reg;
|
| 297 |
|
|
when
|
| 298 |
|
|
OPC_ROLC => aop <= ALU_ROLC;
|
| 299 |
|
|
mop <= MEM_NOP;
|
| 300 |
|
|
iop <= INTR_NOP;
|
| 301 |
|
|
unit <= UNIT_ALU;
|
| 302 |
|
|
target <= TARGET_REGISTER;
|
| 303 |
|
|
dest_out <= src1_reg;
|
| 304 |
|
|
when
|
| 305 |
|
|
OPC_RORC => aop <= ALU_RORC;
|
| 306 |
|
|
mop <= MEM_NOP;
|
| 307 |
|
|
iop <= INTR_NOP;
|
| 308 |
|
|
unit <= UNIT_ALU;
|
| 309 |
|
|
target <= TARGET_REGISTER;
|
| 310 |
|
|
dest_out <= src1_reg;
|
| 311 |
|
|
when
|
| 312 |
|
|
OPC_BSET => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
| 313 |
|
|
aop <= ALU_BSET;
|
| 314 |
|
|
mop <= MEM_NOP;
|
| 315 |
|
|
iop <= INTR_NOP;
|
| 316 |
|
|
unit <= UNIT_ALU;
|
| 317 |
|
|
target <= TARGET_REGISTER;
|
| 318 |
|
|
dest_out <= src1_reg;
|
| 319 |
|
|
when
|
| 320 |
|
|
OPC_BCLR => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
| 321 |
|
|
aop <= ALU_BCLR;
|
| 322 |
|
|
mop <= MEM_NOP;
|
| 323 |
|
|
iop <= INTR_NOP;
|
| 324 |
|
|
unit <= UNIT_ALU;
|
| 325 |
|
|
target <= TARGET_REGISTER;
|
| 326 |
|
|
dest_out <= src1_reg;
|
| 327 |
|
|
when
|
| 328 |
|
|
OPC_BTEST => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
| 329 |
|
|
aop <= ALU_BTEST;
|
| 330 |
|
|
mop <= MEM_NOP;
|
| 331 |
|
|
iop <= INTR_NOP;
|
| 332 |
|
|
unit <= UNIT_ALU;
|
| 333 |
|
|
target <= TARGET_NONE;
|
| 334 |
|
|
dest_out <= src1_reg;
|
| 335 |
|
|
when others => null;
|
| 336 |
|
|
end case;
|
| 337 |
|
|
|
| 338 |
|
|
when OPC_PFX_B =>
|
| 339 |
|
|
case instr_reg(PDATA_WIDTH-5 downto PDATA_WIDTH-8) is
|
| 340 |
|
|
when
|
| 341 |
|
|
OPC_LOAD => mop <= MEM_LOAD;
|
| 342 |
|
|
aop <= ALU_NOP;
|
| 343 |
|
|
iop <= INTR_NOP;
|
| 344 |
|
|
unit <= UNIT_MEM;
|
| 345 |
|
|
target <= TARGET_REGISTER;
|
| 346 |
|
|
dest_out <= src1_reg;
|
| 347 |
|
|
when
|
| 348 |
|
|
OPC_LOADL => mop <= MEM_LOADL;
|
| 349 |
|
|
aop <= ALU_NOP;
|
| 350 |
|
|
iop <= INTR_NOP;
|
| 351 |
|
|
unit <= UNIT_MEM;
|
| 352 |
|
|
target <= TARGET_REGISTER;
|
| 353 |
|
|
dest_out <= src1_reg;
|
| 354 |
|
|
when
|
| 355 |
|
|
OPC_LOADH => mop <= MEM_LOADH;
|
| 356 |
|
|
aop <= ALU_NOP;
|
| 357 |
|
|
iop <= INTR_NOP;
|
| 358 |
|
|
unit <= UNIT_MEM;
|
| 359 |
|
|
target <= TARGET_REGISTER;
|
| 360 |
|
|
dest_out <= src1_reg;
|
| 361 |
|
|
when
|
| 362 |
|
|
OPC_LOADB => mop <= MEM_LOADB;
|
| 363 |
|
|
aop <= ALU_NOP;
|
| 364 |
|
|
iop <= INTR_NOP;
|
| 365 |
|
|
unit <= UNIT_MEM;
|
| 366 |
|
|
target <= TARGET_REGISTER;
|
| 367 |
|
|
dest_out <= src1_reg;
|
| 368 |
|
|
when
|
| 369 |
|
|
OPC_STORE => mop <= MEM_STORE;
|
| 370 |
|
|
aop <= ALU_NOP;
|
| 371 |
|
|
iop <= INTR_NOP;
|
| 372 |
|
|
unit <= UNIT_MEM;
|
| 373 |
|
|
target <= TARGET_NONE;
|
| 374 |
|
|
dest_out <= src1_reg;
|
| 375 |
|
|
when
|
| 376 |
|
|
OPC_STOREL => mop <= MEM_STOREL;
|
| 377 |
|
|
aop <= ALU_NOP;
|
| 378 |
|
|
iop <= INTR_NOP;
|
| 379 |
|
|
unit <= UNIT_MEM;
|
| 380 |
|
|
target <= TARGET_NONE;
|
| 381 |
|
|
dest_out <= src1_reg;
|
| 382 |
|
|
when
|
| 383 |
|
|
OPC_STOREH => mop <= MEM_STOREH;
|
| 384 |
|
|
aop <= ALU_NOP;
|
| 385 |
|
|
iop <= INTR_NOP;
|
| 386 |
|
|
unit <= UNIT_MEM;
|
| 387 |
|
|
target <= TARGET_NONE;
|
| 388 |
|
|
dest_out <= src1_reg;
|
| 389 |
|
|
when
|
| 390 |
|
|
OPC_CALL => aop <= ALU_JMP; -- force alu_pcchg
|
| 391 |
|
|
mop <= MEM_NOP;
|
| 392 |
|
|
iop <= INTR_NOP;
|
| 393 |
|
|
unit <= UNIT_CALL;
|
| 394 |
|
|
target <= TARGET_BOTH;
|
| 395 |
|
|
dest_out <= src1_reg;
|
| 396 |
|
|
when others => null;
|
| 397 |
|
|
end case;
|
| 398 |
|
|
|
| 399 |
|
|
when OPC_PFX_C =>
|
| 400 |
|
|
case instr_reg(PDATA_WIDTH-5 downto PDATA_WIDTH-8) is
|
| 401 |
|
|
when
|
| 402 |
|
|
OPC_BR => aop <= ALU_NOP;
|
| 403 |
|
|
mop <= MEM_NOP;
|
| 404 |
|
|
iop <= INTR_NOP;
|
| 405 |
|
|
unit <= UNIT_ALU;
|
| 406 |
|
|
target <= TARGET_NONE;
|
| 407 |
|
|
dest_out <= src1_reg;
|
| 408 |
|
|
when
|
| 409 |
|
|
OPC_BRZ => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
| 410 |
|
|
aop <= ALU_BRZ;
|
| 411 |
|
|
mop <= MEM_NOP;
|
| 412 |
|
|
iop <= INTR_NOP;
|
| 413 |
|
|
unit <= UNIT_ALU;
|
| 414 |
|
|
target <= TARGET_PC;
|
| 415 |
|
|
dest_out <= src1_reg;
|
| 416 |
|
|
when
|
| 417 |
|
|
OPC_BRNZ => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
| 418 |
|
|
aop <= ALU_BRNZ;
|
| 419 |
|
|
mop <= MEM_NOP;
|
| 420 |
|
|
iop <= INTR_NOP;
|
| 421 |
|
|
unit <= UNIT_ALU;
|
| 422 |
|
|
target <= TARGET_PC;
|
| 423 |
|
|
dest_out <= src1_reg;
|
| 424 |
|
|
when
|
| 425 |
|
|
OPC_BRLE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
| 426 |
|
|
aop <= ALU_BRLE;
|
| 427 |
|
|
mop <= MEM_NOP;
|
| 428 |
|
|
iop <= INTR_NOP;
|
| 429 |
|
|
unit <= UNIT_ALU;
|
| 430 |
|
|
target <= TARGET_PC;
|
| 431 |
|
|
dest_out <= src1_reg;
|
| 432 |
|
|
when
|
| 433 |
|
|
OPC_BRLT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
| 434 |
|
|
aop <= ALU_BRLT;
|
| 435 |
|
|
mop <= MEM_NOP;
|
| 436 |
|
|
iop <= INTR_NOP;
|
| 437 |
|
|
unit <= UNIT_ALU;
|
| 438 |
|
|
target <= TARGET_PC;
|
| 439 |
|
|
dest_out <= src1_reg;
|
| 440 |
|
|
when
|
| 441 |
|
|
OPC_BRGE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
| 442 |
|
|
aop <= ALU_BRGE;
|
| 443 |
|
|
mop <= MEM_NOP;
|
| 444 |
|
|
iop <= INTR_NOP;
|
| 445 |
|
|
unit <= UNIT_ALU;
|
| 446 |
|
|
target <= TARGET_PC;
|
| 447 |
|
|
dest_out <= src1_reg;
|
| 448 |
|
|
when
|
| 449 |
|
|
OPC_BRGT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
| 450 |
|
|
aop <= ALU_BRGT;
|
| 451 |
|
|
mop <= MEM_NOP;
|
| 452 |
|
|
iop <= INTR_NOP;
|
| 453 |
|
|
unit <= UNIT_ALU;
|
| 454 |
|
|
target <= TARGET_PC;
|
| 455 |
|
|
dest_out <= src1_reg;
|
| 456 |
|
|
when
|
| 457 |
|
|
OPC_BRULE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
| 458 |
|
|
aop <= ALU_BRULE;
|
| 459 |
|
|
mop <= MEM_NOP;
|
| 460 |
|
|
iop <= INTR_NOP;
|
| 461 |
|
|
unit <= UNIT_ALU;
|
| 462 |
|
|
target <= TARGET_PC;
|
| 463 |
|
|
dest_out <= src1_reg;
|
| 464 |
|
|
when
|
| 465 |
|
|
OPC_BRULT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
| 466 |
|
|
aop <= ALU_BRULT;
|
| 467 |
|
|
mop <= MEM_NOP;
|
| 468 |
|
|
iop <= INTR_NOP;
|
| 469 |
|
|
unit <= UNIT_ALU;
|
| 470 |
|
|
target <= TARGET_PC;
|
| 471 |
|
|
dest_out <= src1_reg;
|
| 472 |
|
|
when
|
| 473 |
|
|
OPC_BRUGE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
| 474 |
|
|
aop <= ALU_BRUGE;
|
| 475 |
|
|
mop <= MEM_NOP;
|
| 476 |
|
|
iop <= INTR_NOP;
|
| 477 |
|
|
unit <= UNIT_ALU;
|
| 478 |
|
|
target <= TARGET_PC;
|
| 479 |
|
|
dest_out <= src1_reg;
|
| 480 |
|
|
when
|
| 481 |
|
|
OPC_BRUGT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
| 482 |
|
|
aop <= ALU_BRUGT;
|
| 483 |
|
|
mop <= MEM_NOP;
|
| 484 |
|
|
iop <= INTR_NOP;
|
| 485 |
|
|
unit <= UNIT_ALU;
|
| 486 |
|
|
target <= TARGET_PC;
|
| 487 |
|
|
dest_out <= src1_reg;
|
| 488 |
|
|
when
|
| 489 |
|
|
OPC_SEXT => aop <= ALU_SEXT;
|
| 490 |
|
|
mop <= MEM_NOP;
|
| 491 |
|
|
iop <= INTR_NOP;
|
| 492 |
|
|
unit <= UNIT_ALU;
|
| 493 |
|
|
target <= TARGET_REGISTER;
|
| 494 |
|
|
dest_out <= src1_reg;
|
| 495 |
|
|
when
|
| 496 |
|
|
OPC_LDVEC => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
| 497 |
|
|
iop <= INTR_LDVEC;
|
| 498 |
|
|
aop <= ALU_NOP;
|
| 499 |
|
|
mop <= MEM_NOP;
|
| 500 |
|
|
unit <= UNIT_INTR;
|
| 501 |
|
|
target <= TARGET_REGISTER;
|
| 502 |
|
|
dest_out <= src1_reg;
|
| 503 |
|
|
when
|
| 504 |
|
|
OPC_STVEC => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
| 505 |
|
|
iop <= INTR_STVEC;
|
| 506 |
|
|
aop <= ALU_NOP;
|
| 507 |
|
|
mop <= MEM_NOP;
|
| 508 |
|
|
unit <= UNIT_INTR;
|
| 509 |
|
|
target <= TARGET_NONE;
|
| 510 |
|
|
dest_out <= src1_reg;
|
| 511 |
|
|
when
|
| 512 |
|
|
OPC_PFX_C1 =>
|
| 513 |
|
|
case instr_reg(PDATA_WIDTH-9 downto PDATA_WIDTH-12) is
|
| 514 |
|
|
when
|
| 515 |
|
|
OPC_JMP => aop <= ALU_JMP;
|
| 516 |
|
|
mop <= MEM_NOP;
|
| 517 |
|
|
iop <= INTR_NOP;
|
| 518 |
|
|
unit <= UNIT_ALU;
|
| 519 |
|
|
target <= TARGET_PC;
|
| 520 |
|
|
dest_out <= src1_reg;
|
| 521 |
|
|
when
|
| 522 |
|
|
OPC_JMPZ => aop <= ALU_JMPZ;
|
| 523 |
|
|
mop <= MEM_NOP;
|
| 524 |
|
|
iop <= INTR_NOP;
|
| 525 |
|
|
unit <= UNIT_ALU;
|
| 526 |
|
|
target <= TARGET_PC;
|
| 527 |
|
|
dest_out <= src1_reg;
|
| 528 |
|
|
when
|
| 529 |
|
|
OPC_JMPNZ => aop <= ALU_JMPNZ;
|
| 530 |
|
|
mop <= MEM_NOP;
|
| 531 |
|
|
iop <= INTR_NOP;
|
| 532 |
|
|
unit <= UNIT_ALU;
|
| 533 |
|
|
target <= TARGET_PC;
|
| 534 |
|
|
dest_out <= src1_reg;
|
| 535 |
|
|
when
|
| 536 |
|
|
OPC_JMPLE => aop <= ALU_JMPLE;
|
| 537 |
|
|
mop <= MEM_NOP;
|
| 538 |
|
|
iop <= INTR_NOP;
|
| 539 |
|
|
unit <= UNIT_ALU;
|
| 540 |
|
|
target <= TARGET_PC;
|
| 541 |
|
|
dest_out <= src1_reg;
|
| 542 |
|
|
when
|
| 543 |
|
|
OPC_JMPLT => aop <= ALU_JMPLT;
|
| 544 |
|
|
mop <= MEM_NOP;
|
| 545 |
|
|
iop <= INTR_NOP;
|
| 546 |
|
|
unit <= UNIT_ALU;
|
| 547 |
|
|
target <= TARGET_PC;
|
| 548 |
|
|
dest_out <= src1_reg;
|
| 549 |
|
|
when
|
| 550 |
|
|
OPC_JMPGE => aop <= ALU_JMPGE;
|
| 551 |
|
|
mop <= MEM_NOP;
|
| 552 |
|
|
iop <= INTR_NOP;
|
| 553 |
|
|
unit <= UNIT_ALU;
|
| 554 |
|
|
target <= TARGET_PC;
|
| 555 |
|
|
dest_out <= src1_reg;
|
| 556 |
|
|
when
|
| 557 |
|
|
OPC_JMPGT => aop <= ALU_JMPGT;
|
| 558 |
|
|
mop <= MEM_NOP;
|
| 559 |
|
|
iop <= INTR_NOP;
|
| 560 |
|
|
unit <= UNIT_ALU;
|
| 561 |
|
|
target <= TARGET_PC;
|
| 562 |
|
|
dest_out <= src1_reg;
|
| 563 |
|
|
when
|
| 564 |
|
|
OPC_JMPULE => aop <= ALU_JMPULE;
|
| 565 |
|
|
mop <= MEM_NOP;
|
| 566 |
|
|
iop <= INTR_NOP;
|
| 567 |
|
|
unit <= UNIT_ALU;
|
| 568 |
|
|
target <= TARGET_PC;
|
| 569 |
|
|
dest_out <= src1_reg;
|
| 570 |
|
|
when
|
| 571 |
|
|
OPC_JMPULT => aop <= ALU_JMPULT;
|
| 572 |
|
|
mop <= MEM_NOP;
|
| 573 |
|
|
iop <= INTR_NOP;
|
| 574 |
|
|
unit <= UNIT_ALU;
|
| 575 |
|
|
target <= TARGET_PC;
|
| 576 |
|
|
dest_out <= src1_reg;
|
| 577 |
|
|
when
|
| 578 |
|
|
OPC_JMPUGE => aop <= ALU_JMPUGE;
|
| 579 |
|
|
mop <= MEM_NOP;
|
| 580 |
|
|
iop <= INTR_NOP;
|
| 581 |
|
|
unit <= UNIT_ALU;
|
| 582 |
|
|
target <= TARGET_PC;
|
| 583 |
|
|
dest_out <= src1_reg;
|
| 584 |
|
|
when
|
| 585 |
|
|
OPC_JMPUGT => aop <= ALU_JMPUGT;
|
| 586 |
|
|
mop <= MEM_NOP;
|
| 587 |
|
|
iop <= INTR_NOP;
|
| 588 |
|
|
unit <= UNIT_ALU;
|
| 589 |
|
|
target <= TARGET_PC;
|
| 590 |
|
|
dest_out <= src1_reg;
|
| 591 |
|
|
when
|
| 592 |
|
|
OPC_INTR => imm <= std_logic_vector(resize(unsigned(src1_reg), REG_WIDTH));
|
| 593 |
|
|
aop <= ALU_INTR;
|
| 594 |
|
|
iop <= INTR_INTR;
|
| 595 |
|
|
mop <= MEM_NOP;
|
| 596 |
|
|
unit <= UNIT_INTR;
|
| 597 |
|
|
target <= TARGET_PC;
|
| 598 |
|
|
dest_out <= src1_reg;
|
| 599 |
|
|
when
|
| 600 |
|
|
OPC_GETFL => aop <= ALU_GETFL;
|
| 601 |
|
|
mop <= MEM_NOP;
|
| 602 |
|
|
iop <= INTR_NOP;
|
| 603 |
|
|
unit <= UNIT_ALU;
|
| 604 |
|
|
target <= TARGET_REGISTER;
|
| 605 |
|
|
dest_out <= src1_reg;
|
| 606 |
|
|
when
|
| 607 |
|
|
OPC_SETFL => aop <= ALU_SETFL;
|
| 608 |
|
|
mop <= MEM_NOP;
|
| 609 |
|
|
iop <= INTR_NOP;
|
| 610 |
|
|
unit <= UNIT_ALU;
|
| 611 |
|
|
target <= TARGET_NONE;
|
| 612 |
|
|
dest_out <= src1_reg;
|
| 613 |
|
|
when
|
| 614 |
|
|
OPC_GETIRA => iop <= INTR_GETIRA;
|
| 615 |
|
|
aop <= ALU_NOP;
|
| 616 |
|
|
mop <= MEM_NOP;
|
| 617 |
|
|
unit <= UNIT_INTR;
|
| 618 |
|
|
target <= TARGET_REGISTER;
|
| 619 |
|
|
dest_out <= src1_reg;
|
| 620 |
|
|
|
| 621 |
|
|
when
|
| 622 |
|
|
OPC_SETIRA => iop <= INTR_SETIRA;
|
| 623 |
|
|
aop <= ALU_NOP;
|
| 624 |
|
|
mop <= MEM_NOP;
|
| 625 |
|
|
unit <= UNIT_INTR;
|
| 626 |
|
|
target <= TARGET_NONE;
|
| 627 |
|
|
dest_out <= src1_reg;
|
| 628 |
|
|
when others => null;
|
| 629 |
|
|
end case;
|
| 630 |
|
|
|
| 631 |
|
|
when
|
| 632 |
|
|
OPC_PFX_C2 =>
|
| 633 |
|
|
case instr_reg(PDATA_WIDTH-9 downto PDATA_WIDTH-12) is
|
| 634 |
|
|
when
|
| 635 |
|
|
OPC_GETSHFL => aop <= ALU_GETSHFL;
|
| 636 |
|
|
mop <= MEM_NOP;
|
| 637 |
|
|
iop <= INTR_NOP;
|
| 638 |
|
|
unit <= UNIT_ALU;
|
| 639 |
|
|
target <= TARGET_REGISTER;
|
| 640 |
|
|
dest_out <= src1_reg;
|
| 641 |
|
|
when
|
| 642 |
|
|
OPC_SETSHFL => aop <= ALU_SETSHFL;
|
| 643 |
|
|
mop <= MEM_NOP;
|
| 644 |
|
|
iop <= INTR_NOP;
|
| 645 |
|
|
unit <= UNIT_ALU;
|
| 646 |
|
|
target <= TARGET_NONE;
|
| 647 |
|
|
dest_out <= src1_reg;
|
| 648 |
|
|
when
|
| 649 |
|
|
OPC_PFX_C2a =>
|
| 650 |
|
|
case instr_reg(PDATA_WIDTH-13 downto PDATA_WIDTH-16) is
|
| 651 |
|
|
when
|
| 652 |
|
|
OPC_RETI => aop <= ALU_RETI;
|
| 653 |
|
|
iop <= INTR_RETI;
|
| 654 |
|
|
mop <= MEM_NOP;
|
| 655 |
|
|
unit <= UNIT_INTR;
|
| 656 |
|
|
target <= TARGET_PC;
|
| 657 |
|
|
dest_out <= src1_reg;
|
| 658 |
|
|
when
|
| 659 |
|
|
OPC_NOP => aop <= ALU_NOP;
|
| 660 |
|
|
mop <= MEM_NOP;
|
| 661 |
|
|
iop <= INTR_NOP;
|
| 662 |
|
|
unit <= UNIT_ALU;
|
| 663 |
|
|
target <= TARGET_NONE;
|
| 664 |
|
|
dest_out <= src1_reg;
|
| 665 |
|
|
when
|
| 666 |
|
|
OPC_SEI => aop <= ALU_SEI;
|
| 667 |
|
|
mop <= MEM_NOP;
|
| 668 |
|
|
iop <= INTR_NOP;
|
| 669 |
|
|
unit <= UNIT_ALU;
|
| 670 |
|
|
target <= TARGET_NONE;
|
| 671 |
|
|
dest_out <= src1_reg;
|
| 672 |
|
|
when
|
| 673 |
|
|
OPC_CLI => aop <= ALU_CLI;
|
| 674 |
|
|
mop <= MEM_NOP;
|
| 675 |
|
|
iop <= INTR_NOP;
|
| 676 |
|
|
unit <= UNIT_ALU;
|
| 677 |
|
|
target <= TARGET_NONE;
|
| 678 |
|
|
dest_out <= src1_reg;
|
| 679 |
|
|
when others => null;
|
| 680 |
|
|
end case;
|
| 681 |
|
|
when others => null;
|
| 682 |
|
|
end case;
|
| 683 |
|
|
when others => null;
|
| 684 |
|
|
end case;
|
| 685 |
|
|
when others => null;
|
| 686 |
|
|
end case;
|
| 687 |
|
|
|
| 688 |
|
|
end process;
|
| 689 |
|
|
|
| 690 |
|
|
end behaviour;
|
