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[/] [marca/] [trunk/] [vhdl/] [execute.vhd] - Blame information for rev 8

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1 2 jeunes2
--  This file is part of the marca processor.
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--  Copyright (C) 2007 Wolfgang Puffitsch
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--  This program is free software; you can redistribute it and/or modify it
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--  under the terms of the GNU Library General Public License as published
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--  by the Free Software Foundation; either version 2, or (at your option)
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--  any later version.
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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--  Library General Public License for more details.
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--  You should have received a copy of the GNU Library General Public
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--  License along with this program; if not, write to the Free Software
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--  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA
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-------------------------------------------------------------------------------
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-- MARCA execution stage
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-------------------------------------------------------------------------------
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-- architecture of the execution pipeline stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Wolfgang Puffitsch
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-- Computer Architecture Lab, Group 3
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.marca_pkg.all;
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architecture behaviour of execute is
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component alu is
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  port (
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    clock   : in  std_logic;
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    reset   : in  std_logic;
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    busy    : out std_logic;
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    op      : in  ALU_OP;
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    a       : in  std_logic_vector(REG_WIDTH-1 downto 0);
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    b       : in  std_logic_vector(REG_WIDTH-1 downto 0);
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    i       : in  std_logic_vector(REG_WIDTH-1 downto 0);
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    pc      : in  std_logic_vector(REG_WIDTH-1 downto 0);
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    intr    : in  std_logic;
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    exc     : out std_logic;
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    iena    : out std_logic;
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    pcchg   : out std_logic;
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    result  : out std_logic_vector(REG_WIDTH-1 downto 0));
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end component;
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component mem is
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  port (
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    clock   : in  std_logic;
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    reset   : in  std_logic;
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    op      : in  MEM_OP;
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    address : in  std_logic_vector(REG_WIDTH-1 downto 0);
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    data    : in  std_logic_vector(REG_WIDTH-1 downto 0);
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    exc     : out std_logic;
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    busy    : out std_logic;
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    result  : out std_logic_vector(REG_WIDTH-1 downto 0);
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    intrs   : out std_logic_vector(VEC_COUNT-1 downto 3);
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    ext_in  : in  std_logic_vector(IN_BITS-1 downto 0);
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    ext_out : out std_logic_vector(OUT_BITS-1 downto 0));
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end component;
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component intr is
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  port (
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    clock   : in  std_logic;
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    reset   : in  std_logic;
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    enable  : in  std_logic;
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    trigger : in  std_logic_vector(VEC_COUNT-1 downto 1);
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    op      : in  INTR_OP;
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    a       : in  std_logic_vector(REG_WIDTH-1 downto 0);
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    i       : in  std_logic_vector(REG_WIDTH-1 downto 0);
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    pc      : in  std_logic_vector(REG_WIDTH-1 downto 0);
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    exc     : out std_logic;
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    pcchg   : out std_logic;
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    result  : out std_logic_vector(REG_WIDTH-1 downto 0));
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end component;
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signal any_busy : std_logic;
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signal alu_iena   : std_logic;
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signal alu_exc    : std_logic;
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signal alu_busy   : std_logic;
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signal alu_pcchg  : std_logic;
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signal alu_result : std_logic_vector(REG_WIDTH-1 downto 0);
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signal mem_exc    : std_logic;
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signal mem_busy   : std_logic;
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signal mem_result : std_logic_vector(REG_WIDTH-1 downto 0);
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signal mem_intrs  : std_logic_vector(VEC_COUNT-1 downto 3);
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signal intr_enable : std_logic;
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signal intr_exc    : std_logic;
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signal intr_pcchg  : std_logic;
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signal intr_result : std_logic_vector(REG_WIDTH-1 downto 0);
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signal pc_reg   : std_logic_vector(REG_WIDTH-1 downto 0);
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signal src1_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
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signal src2_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
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signal dest_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
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signal op1_reg  : std_logic_vector(REG_WIDTH-1 downto 0);
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signal op2_reg  : std_logic_vector(REG_WIDTH-1 downto 0);
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signal imm_reg  : std_logic_vector(REG_WIDTH-1 downto 0);
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signal op1_fwed : std_logic_vector(REG_WIDTH-1 downto 0);
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signal op2_fwed : std_logic_vector(REG_WIDTH-1 downto 0);
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signal aop_reg  : ALU_OP;
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signal mop_reg  : MEM_OP;
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signal iop_reg  : INTR_OP;
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signal unit_reg   : UNIT_SELECTOR;
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signal target_reg : TARGET_SELECTOR;
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signal stall_cnt      : std_logic_vector(1 downto 0);  -- prohibiting                                                        
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signal next_stall_cnt : std_logic_vector(1 downto 0);  -- interrupts during reti
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begin  -- behaviour
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  -- interrupts do not work while jumping
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  intr_enable <= alu_iena and zero(stall_cnt) and not any_busy;
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  alu_unit : alu
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    port map (
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      clock => clock,
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      reset => reset,
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      op => aop_reg,
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      a => op1_fwed,
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      b => op2_fwed,
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      i => imm_reg,
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      pc => pc_reg,
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      intr => intr_exc,
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      exc => alu_exc,
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      busy => alu_busy,
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      iena => alu_iena,
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      pcchg => alu_pcchg,
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      result => alu_result);
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  mem_unit : mem
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    port map (
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      clock   => clock,
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      reset   => reset,
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      op      => mop_reg,
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      address => op2_fwed,
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      data    => op1_fwed,
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      exc     => mem_exc,
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      busy    => mem_busy,
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      result  => mem_result,
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      intrs   => mem_intrs,
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      ext_in  => ext_in,
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      ext_out => ext_out);
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  intr_unit : intr
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    port map (
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      clock            => clock,
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      reset            => reset,
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      enable           => intr_enable,
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      trigger(EXC_ALU) => alu_exc,
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      trigger(EXC_MEM) => mem_exc,
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      trigger(VEC_COUNT-1 downto 3) => mem_intrs,
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      op               => iop_reg,
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      a                => op1_fwed,
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      i                => imm_reg,
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      pc               => pc_reg,
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      exc              => intr_exc,
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      pcchg            => intr_pcchg,
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      result           => intr_result);
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  syn_proc: process (clock, reset)
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  begin  -- process syn_proc
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    if reset = RESET_ACTIVE then                 -- asynchronous reset (active low)
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      stall_cnt <= (others => '0');
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      pc_reg <= (others => '0');
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      src1_reg <= (others => '0');
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      src2_reg <= (others => '0');
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      dest_reg <= (others => '0');
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      aop_reg <= ALU_NOP;
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      mop_reg <= MEM_NOP;
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      iop_reg <= INTR_NOP;
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      op1_reg <= (others => '0');
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      op2_reg <= (others => '0');
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      imm_reg <= (others => '0');
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      unit_reg <= UNIT_ALU;
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      target_reg <= TARGET_NONE;
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    elsif clock'event and clock = '1' then  -- rising clock edge
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      if any_busy = '0' then
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        stall_cnt <= next_stall_cnt;
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        if stall = '1' then
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          pc_reg <= (others => '0');
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          src1_reg <= (others => '0');
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          src2_reg <= (others => '0');
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          dest_reg <= (others => '0');
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          aop_reg <= ALU_NOP;
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          mop_reg <= MEM_NOP;
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          iop_reg <= INTR_NOP;
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          op1_reg <= (others => '0');
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          op2_reg <= (others => '0');
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          imm_reg <= (others => '0');
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          unit_reg <= UNIT_ALU;
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          target_reg <= TARGET_NONE;
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        else
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          pc_reg <= pc_in;
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          dest_reg <= dest_in;
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          src1_reg <= src1;
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          src2_reg <= src2;
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          aop_reg <= aop;
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          mop_reg <= mop;
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          iop_reg <= iop;
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          op1_reg <= op1;
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          op2_reg <= op2;
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          imm_reg <= imm;
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          unit_reg <= unit;
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          target_reg <= target_in;
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        end if;
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      end if;
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    end if;
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  end process syn_proc;
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  stalling: process (stall, stall_cnt)
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  begin  -- process hold_pc
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    next_stall_cnt <= std_logic_vector(unsigned(stall_cnt) - 1);
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    if zero(stall_cnt) = '1' then
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      next_stall_cnt <= "00";
232
    end if;
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    if stall = '1' then
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      next_stall_cnt <= "11";
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    end if;
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  end process stalling;
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  business: process (any_busy, alu_busy, mem_busy)
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  begin  -- process business
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    any_busy <= alu_busy or mem_busy;
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    busy <= any_busy;
243
  end process business;
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  feedthrough: process (pc_reg, dest_reg, unit_reg, target_reg, op2_fwed, intr_exc)
246
  begin  -- process feedthrough
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    if unit_reg /= UNIT_CALL then
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      pc_out <= pc_reg;
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    else
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      pc_out <= op2_fwed;
251
    end if;
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    dest_out <= dest_reg;
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    if intr_exc = '1' then
254
      target_out <= TARGET_PC;
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    else
256
      target_out <= target_reg;
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    end if;
258
  end process feedthrough;
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  forward: process (src1_reg, src2_reg, op1_reg, op2_reg, fw_ena, fw_dest, fw_val)
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  begin  -- process forward
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    op1_fwed <= op1_reg;
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    op2_fwed <= op2_reg;
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    if fw_ena = '1' then
265
      if src1_reg = fw_dest then
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        op1_fwed <= fw_val;
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      end if;
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      if src2_reg = fw_dest then
269
        op2_fwed <= fw_val;
270
      end if;
271
    end if;
272
  end process forward;
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  select_result: process(unit_reg, alu_result, mem_result, intr_result, pc_reg,
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                         alu_pcchg, intr_pcchg,
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                         intr_exc)
277
  begin  -- process select_result
278
    case unit_reg is
279
      when UNIT_ALU => result <= alu_result;
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      when UNIT_MEM => result <= mem_result;
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      when UNIT_INTR => result <= intr_result;
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      when UNIT_CALL => result <= std_logic_vector(unsigned(pc_reg) + 1);
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      when others => null;
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    end case;
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    if intr_exc = '1' then
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      result <= intr_result;
287
    end if;
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    pcchg <= alu_pcchg or intr_pcchg;
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  end process select_result;
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end behaviour;

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