OpenCores
URL https://opencores.org/ocsvn/marca/marca/trunk

Subversion Repositories marca

[/] [marca/] [trunk/] [vhdl/] [uart_reverse.s] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jeunes2
.data
2
        data 0x0A
3
        data 0x0D
4
buffer:
5
 
6
.text
7
;;; initialization
8
        ldib    r0, -8          ; config/status
9
        ldib    r1, -6          ; data
10
 
11
        ldil    r2,  lo(buffer) ; buffer address
12
        ldih    r2,  hi(buffer) ; buffer address
13
 
14
        ldib    r3,  0x0A       ; newline character
15
        ldib    r4,  0x0D       ; carriage return
16
 
17
        ldib    r5,  0           ; mode
18
 
19
        ldib    r7,  isr        ; register isr
20
        stvec   r7,  3
21
 
22
        ldib    r7, (1 << 3)    ; enable receive interrupts
23
        store   r7,  r0
24
 
25
        sei                     ; enable interrupts
26
 
27
;;; loop forever
28
loop:   br loop
29
 
30
 
31
;;; ISR
32
isr:
33
        cmpi    r5, 0            ; check mode
34
        brnz    write_mode
35
 
36
;;; reading
37
read_mode:
38
        load    r7, r1          ; read data
39
 
40
        cmp     r7, r3          ; change mode upon newline
41
        brnz    read_CR
42
 
43
        ldib    r7, (1 << 2)    ; do the change
44
        store   r7, r0
45
        ldib    r5, 1
46
        reti
47
 
48
read_CR:
49
        cmp     r7, r4          ; ignore carriage return
50
        brnz    read_cont
51
        reti
52
 
53
read_cont:
54
        storel  r7, r2          ; store date
55
        addi    r2,  1
56
        reti
57
 
58
;;; writing
59
write_mode:
60
        addi    r2, -1
61
 
62
        cmpi    r2, -1          ; change mode if there is no more data
63
        brnz    write_cont
64
 
65
        ldil    r2,  lo(buffer) ; correct pointer to buffer
66
        ldih    r2,  hi(buffer)
67
 
68
        ldib    r7, (1 << 3)    ; do the change
69
        store   r7, r0
70
        ldib    r5, 0
71
        reti
72
 
73
write_cont:
74
        loadl   r7, r2          ; write data
75
        store   r7, r1
76
        reti
77
 
78
 
79
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.