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-- ***** BEGIN LICENSE BLOCK *****
----------------------------------------------------------------------
----                                                              ----
---- WISHBONE matrix 3x3 multiplier IP Core                       ----
----                                                              ----
---- This file is part of the matrix 3x3 multiplier project       ----
---- http://www.opencores.org/projects.cgi/web/matrix3x3/         ----
----                                                              ----
---- Description                                                  ----
---- Matrix 3x3 multiplier with WISHBONE interface                                ----
----                                                                  ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Michael Tsvetkov, michland@opencores.org                   ----
---- - Vyacheslav Gulyaev, vv_gulyaev@opencores.org               ----  
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2007 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU Lesser General Public License for more  ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/lgpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
-- * ***** END LICENSE BLOCK ***** */    
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity  multiplier3x3 is
generic(
        DATA_WIDTH      : INTEGER;
        F_FACTORS_PART  : INTEGER;
        INT_FACTORS_PART        : INTEGER
        );
 
port    (
        clk                             :       IN STD_LOGIC;
        rstn                    :       IN STD_LOGIC;
 
        DATA_ENA                :       IN STD_LOGIC;
        DOUT_RDY                :       OUT STD_LOGIC;
 
        -- input vector
        x1                              :       IN UNSIGNED( data_width-1 downto 0 );
        x2                              :       IN UNSIGNED( data_width-1 downto 0 );
        x3                              :       IN UNSIGNED( data_width-1 downto 0 );
 
        -- matrix factors
        a11,a12,a13             :       IN SIGNED( f_factors_part+int_factors_part-1 downto 0 );
        a21,a22,a23             :       IN SIGNED( f_factors_part+int_factors_part-1 downto 0 );
        a31,a32,a33             :       IN SIGNED( f_factors_part+int_factors_part-1 downto 0 );
 
        --shift vectors
        b1x,b2x,b3x             :       IN SIGNED( f_factors_part+int_factors_part-1 downto 0 );
        b1y,b2y,b3y             :       IN SIGNED( f_factors_part+int_factors_part-1 downto 0 );
 
        -- output vector
        y1c                             :       OUT SIGNED( int_factors_part-1 downto 0 );
        y2c                             :       OUT SIGNED( int_factors_part-1 downto 0 );
        y3c                             :       OUT SIGNED( int_factors_part-1 downto 0 );
        y1                              :       OUT UNSIGNED( data_width-1 downto 0 );
        y2                              :       OUT UNSIGNED( data_width-1 downto 0 );
        y3                              :       OUT UNSIGNED( data_width-1 downto 0 )
);
end multiplier3x3;
 
architecture a of multiplier3x3 is
 
constant factors_width  : integer := (f_factors_part + int_factors_part); -- one sign bit
-- the result full width will be
signal m11, m12, m13            : SIGNED( (data_width+factors_width) downto 0 );
signal m21, m22, m23            : SIGNED( (data_width+factors_width) downto 0 );
signal m31, m32, m33            : SIGNED( (data_width+factors_width) downto 0 );
 
signal x1sh, x2sh, x3sh         : SIGNED( data_width downto 0 );
 
signal x1s, x2s, x3s            : SIGNED( data_width downto 0 );
 
signal y1s, y2s, y3s            : SIGNED( data_width+int_factors_part-1 downto 0 );
 
signal y1sh, y2sh, y3sh         : SIGNED( data_width+int_factors_part-1 downto 0 );
 
signal y1r,  y2r,  y3r          : SIGNED( data_width+int_factors_part-1 downto 0 );
 
signal y1ro, y2ro,  y3ro        : SIGNED( data_width+int_factors_part-1 downto 0 );
 
signal s1w, s2w, s3w            : SIGNED( (data_width+factors_width) downto 0 );
 
signal d1, d2, d3                       : SIGNED( (data_width+factors_width) downto 0 );
 
signal y1w,y2w,y3w                      : SIGNED( (data_width+factors_width) downto 0 );
 
signal pipe_delay                       : STD_LOGIC_VECTOR( 7 downto 0 );
 
begin
 
x1s <= '0' & Signed(x1);
x2s <= '0' & Signed(x2);
x3s <= '0' & Signed(x3);
 
process(clk, rstn)
begin
        if rstn = '0' then
 
                m11      <= (others=>'0');
                m12      <= (others=>'0');
                m13      <= (others=>'0');
                m21      <= (others=>'0');
                m22      <= (others=>'0');
                m23      <= (others=>'0');
                m31      <= (others=>'0');
                m32      <= (others=>'0');
                m33      <= (others=>'0');
 
                s1w      <= (others=>'0');
                s2w      <= (others=>'0');
                s3w      <= (others=>'0');
 
                d1        <= (others=>'0');
                d2        <= (others=>'0');
                d3        <= (others=>'0');
 
                y1w      <= (others=>'0');
                y2w      <= (others=>'0');
                y3w      <= (others=>'0');
 
                y1sh <= (others=>'0');
                y2sh <= (others=>'0');
                y3sh <= (others=>'0');
 
                y1ro <=  (others=>'0');
                y2ro <=  (others=>'0');
                y3ro <=  (others=>'0');
 
        elsif rising_edge(clk) then
 
                x1sh <= x1s+b1x(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);
                x2sh <= x2s+b2x(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);
                x3sh <= x3s+b3x(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);
 
                m11 <= a11 * x1sh;
                m12 <= a12 * x2sh;
                m13 <= a13 * x3sh;
                m21 <= a21 * x1sh;
                m22 <= a22 * x2sh;
                m23 <= a23 * x3sh;
                m31 <= a31 * x1sh;
                m32 <= a32 * x2sh;
                m33 <= a33 * x3sh;
 
                s1w <= m11 + m12;
                s2w <= m21 + m22;
                s3w <= m31 + m32;
 
                d1 <= m13;
                d2 <= m23;
                d3 <= m33;
 
                y1w <= s1w + d1;
                y2w <= s2w + d2;
                y3w <= s3w + d3;
 
                y1s(data_width+int_factors_part-1 downto data_width) <= y1w(data_width+int_factors_part+f_factors_part-1 downto data_width+f_factors_part);
                y2s(data_width+int_factors_part-1 downto data_width) <= y2w(data_width+int_factors_part+f_factors_part-1 downto data_width+f_factors_part);
                y3s(data_width+int_factors_part-1 downto data_width) <= y3w(data_width+int_factors_part+f_factors_part-1 downto data_width+f_factors_part);
 
                y1s(data_width-1 downto 0) <= y1w(data_width+f_factors_part-1 downto f_factors_part);
                y2s(data_width-1 downto 0) <= y2w(data_width+f_factors_part-1 downto f_factors_part);
                y3s(data_width-1 downto 0) <= y3w(data_width+f_factors_part-1 downto f_factors_part);
 
                y1sh <= y1s + b1y(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);
                y2sh <= y2s + b2y(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);
                y3sh <= y3s + b3y(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);
 
                y1r <= y1sh+y1w(f_factors_part-1);
                y2r <= y2sh+y2w(f_factors_part-1);
                y3r <= y3sh+y3w(f_factors_part-1);
 
                if    (y1r(data_width+int_factors_part-1)='1' and y1r(data_width)='1')then y1ro(data_width-1 downto 0)<=(others=>'0');
                elsif (y1r(data_width+int_factors_part-1)='0' and y1r(data_width)='1')then y1ro(data_width-1 downto 0)<=(others=>'1');
                else y1ro<=y1r;
                end if;
 
                if    (y2r(data_width+int_factors_part-1)='1' and y2r(data_width)='1')then y2ro(data_width-1 downto 0)<=(others=>'0');
                elsif (y2r(data_width+int_factors_part-1)='0' and y2r(data_width)='1')then y2ro(data_width-1 downto 0)<=(others=>'1');
                else y2ro<=y2r;
                end if;
 
                if    (y3r(data_width+int_factors_part-1)='1' and y3r(data_width)='1')then y3ro(data_width-1 downto 0)<=(others=>'0');
                elsif (y3r(data_width+int_factors_part-1)='0' and y3r(data_width)='1')then y3ro(data_width-1 downto 0)<=(others=>'1');
                else y3ro<=y3r;
                end if;
 
        end if;
end process;
 
y1c <= y1r(data_width+int_factors_part-1 downto data_width);
y2c <= y2r(data_width+int_factors_part-1 downto data_width);
y3c <= y3r(data_width+int_factors_part-1 downto data_width);
 
y1 <= UNSIGNED(y1ro(data_width-1 downto 0));
y2 <= UNSIGNED(y2ro(data_width-1 downto 0));
y3 <= UNSIGNED(y3ro(data_width-1 downto 0));
 
-- this shift register is nessecary for generating RDY sig and easy integration with fifo
process(clk, rstn)
begin
        if rstn = '0' then
                pipe_delay <= (others=>'0');
        elsif rising_edge(clk) then
                pipe_delay(0) <= DATA_ENA;
                pipe_delay(7 downto 1) <= pipe_delay(6 downto 0);
        end if;
end process;
 
DOUT_RDY <= pipe_delay(7);
 
 
end a;

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Subversion Repositories matrix3x3

[/] [matrix3x3/] [trunk/] [rtl/] [vhdl/] [multiplier3x3.vhd] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	michland	`-- *** BEGIN LICENSE BLOCK ***`
2			`----------------------------------------------------------------------`
3			`---- ----`
4			`---- WISHBONE matrix 3x3 multiplier IP Core ----`
5			`---- ----`
6			`---- This file is part of the matrix 3x3 multiplier project ----`
7			`---- http://www.opencores.org/projects.cgi/web/matrix3x3/ ----`
8			`---- ----`
9			`---- Description ----`
10			`---- Matrix 3x3 multiplier with WISHBONE interface ----`
11			`---- ----`
12			`---- To Do: ----`
13			`---- - ----`
14			`---- ----`
15			`---- Author(s): ----`
16			`---- - Michael Tsvetkov, michland@opencores.org ----`
17			`---- - Vyacheslav Gulyaev, vv_gulyaev@opencores.org ----`
18			`---- ----`
19			`----------------------------------------------------------------------`
20			`---- ----`
21			`---- Copyright (C) 2007 Authors and OPENCORES.ORG ----`
22			`---- ----`
23			`---- This source file may be used and distributed without ----`
24			`---- restriction provided that this copyright statement is not ----`
25			`---- removed from the file and that any derivative work contains ----`
26			`---- the original copyright notice and the associated disclaimer. ----`
27			`---- ----`
28			`---- This source file is free software; you can redistribute it ----`
29			`---- and/or modify it under the terms of the GNU Lesser General ----`
30			`---- Public License as published by the Free Software Foundation; ----`
31			`---- either version 2.1 of the License, or (at your option) any ----`
32			`---- later version. ----`
33			`---- ----`
34			`---- This source is distributed in the hope that it will be ----`
35			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
36			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
37			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
38			`---- details. ----`
39			`---- ----`
40			`---- You should have received a copy of the GNU Lesser General ----`
41			`---- Public License along with this source; if not, download it ----`
42			`---- from http://www.gnu.org/licenses/lgpl.txt ----`
43			`---- ----`
44			`----------------------------------------------------------------------`
45			`-- * *** END LICENSE BLOCK *** */`
46
47			`library IEEE;`
48			`use IEEE.std_logic_1164.all;`
49			`use IEEE.std_logic_arith.all;`
50
51			`entity multiplier3x3 is`
52			`generic(`
53			`DATA_WIDTH : INTEGER;`
54			`F_FACTORS_PART : INTEGER;`
55			`INT_FACTORS_PART : INTEGER`
56			`);`
57
58			`port (`
59			`clk : IN STD_LOGIC;`
60			`rstn : IN STD_LOGIC;`
61
62			`DATA_ENA : IN STD_LOGIC;`
63			`DOUT_RDY : OUT STD_LOGIC;`
64
65			`-- input vector`
66			`x1 : IN UNSIGNED( data_width-1 downto 0 );`
67			`x2 : IN UNSIGNED( data_width-1 downto 0 );`
68			`x3 : IN UNSIGNED( data_width-1 downto 0 );`
69
70			`-- matrix factors`
71			`a11,a12,a13 : IN SIGNED( f_factors_part+int_factors_part-1 downto 0 );`
72			`a21,a22,a23 : IN SIGNED( f_factors_part+int_factors_part-1 downto 0 );`
73			`a31,a32,a33 : IN SIGNED( f_factors_part+int_factors_part-1 downto 0 );`
74
75			`--shift vectors`
76			`b1x,b2x,b3x : IN SIGNED( f_factors_part+int_factors_part-1 downto 0 );`
77			`b1y,b2y,b3y : IN SIGNED( f_factors_part+int_factors_part-1 downto 0 );`
78
79			`-- output vector`
80			`y1c : OUT SIGNED( int_factors_part-1 downto 0 );`
81			`y2c : OUT SIGNED( int_factors_part-1 downto 0 );`
82			`y3c : OUT SIGNED( int_factors_part-1 downto 0 );`
83			`y1 : OUT UNSIGNED( data_width-1 downto 0 );`
84			`y2 : OUT UNSIGNED( data_width-1 downto 0 );`
85			`y3 : OUT UNSIGNED( data_width-1 downto 0 )`
86			`);`
87			`end multiplier3x3;`
88
89			`architecture a of multiplier3x3 is`
90
91			`constant factors_width : integer := (f_factors_part + int_factors_part); -- one sign bit`
92			`-- the result full width will be`
93			`signal m11, m12, m13 : SIGNED( (data_width+factors_width) downto 0 );`
94			`signal m21, m22, m23 : SIGNED( (data_width+factors_width) downto 0 );`
95			`signal m31, m32, m33 : SIGNED( (data_width+factors_width) downto 0 );`
96
97			`signal x1sh, x2sh, x3sh : SIGNED( data_width downto 0 );`
98
99			`signal x1s, x2s, x3s : SIGNED( data_width downto 0 );`
100
101			`signal y1s, y2s, y3s : SIGNED( data_width+int_factors_part-1 downto 0 );`
102
103			`signal y1sh, y2sh, y3sh : SIGNED( data_width+int_factors_part-1 downto 0 );`
104
105			`signal y1r, y2r, y3r : SIGNED( data_width+int_factors_part-1 downto 0 );`
106
107			`signal y1ro, y2ro, y3ro : SIGNED( data_width+int_factors_part-1 downto 0 );`
108
109			`signal s1w, s2w, s3w : SIGNED( (data_width+factors_width) downto 0 );`
110
111			`signal d1, d2, d3 : SIGNED( (data_width+factors_width) downto 0 );`
112
113			`signal y1w,y2w,y3w : SIGNED( (data_width+factors_width) downto 0 );`
114
115			`signal pipe_delay : STD_LOGIC_VECTOR( 7 downto 0 );`
116
117			`begin`
118
119			`x1s <= '0' & Signed(x1);`
120			`x2s <= '0' & Signed(x2);`
121			`x3s <= '0' & Signed(x3);`
122
123			`process(clk, rstn)`
124			`begin`
125			`if rstn = '0' then`
126
127			`m11 <= (others=>'0');`
128			`m12 <= (others=>'0');`
129			`m13 <= (others=>'0');`
130			`m21 <= (others=>'0');`
131			`m22 <= (others=>'0');`
132			`m23 <= (others=>'0');`
133			`m31 <= (others=>'0');`
134			`m32 <= (others=>'0');`
135			`m33 <= (others=>'0');`
136
137			`s1w <= (others=>'0');`
138			`s2w <= (others=>'0');`
139			`s3w <= (others=>'0');`
140
141			`d1 <= (others=>'0');`
142			`d2 <= (others=>'0');`
143			`d3 <= (others=>'0');`
144
145			`y1w <= (others=>'0');`
146			`y2w <= (others=>'0');`
147			`y3w <= (others=>'0');`
148
149			`y1sh <= (others=>'0');`
150			`y2sh <= (others=>'0');`
151			`y3sh <= (others=>'0');`
152
153			`y1ro <= (others=>'0');`
154			`y2ro <= (others=>'0');`
155			`y3ro <= (others=>'0');`
156
157			`elsif rising_edge(clk) then`
158
159			`x1sh <= x1s+b1x(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);`
160			`x2sh <= x2s+b2x(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);`
161			`x3sh <= x3s+b3x(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);`
162
163			`m11 <= a11 * x1sh;`
164			`m12 <= a12 * x2sh;`
165			`m13 <= a13 * x3sh;`
166			`m21 <= a21 * x1sh;`
167			`m22 <= a22 * x2sh;`
168			`m23 <= a23 * x3sh;`
169			`m31 <= a31 * x1sh;`
170			`m32 <= a32 * x2sh;`
171			`m33 <= a33 * x3sh;`
172
173			`s1w <= m11 + m12;`
174			`s2w <= m21 + m22;`
175			`s3w <= m31 + m32;`
176
177			`d1 <= m13;`
178			`d2 <= m23;`
179			`d3 <= m33;`
180
181			`y1w <= s1w + d1;`
182			`y2w <= s2w + d2;`
183			`y3w <= s3w + d3;`
184
185			`y1s(data_width+int_factors_part-1 downto data_width) <= y1w(data_width+int_factors_part+f_factors_part-1 downto data_width+f_factors_part);`
186			`y2s(data_width+int_factors_part-1 downto data_width) <= y2w(data_width+int_factors_part+f_factors_part-1 downto data_width+f_factors_part);`
187			`y3s(data_width+int_factors_part-1 downto data_width) <= y3w(data_width+int_factors_part+f_factors_part-1 downto data_width+f_factors_part);`
188
189			`y1s(data_width-1 downto 0) <= y1w(data_width+f_factors_part-1 downto f_factors_part);`
190			`y2s(data_width-1 downto 0) <= y2w(data_width+f_factors_part-1 downto f_factors_part);`
191			`y3s(data_width-1 downto 0) <= y3w(data_width+f_factors_part-1 downto f_factors_part);`
192
193			`y1sh <= y1s + b1y(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);`
194			`y2sh <= y2s + b2y(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);`
195			`y3sh <= y3s + b3y(FACTORS_WIDTH-1 DOWNTO FACTORS_WIDTH-DATA_WIDTH-1);`
196
197			`y1r <= y1sh+y1w(f_factors_part-1);`
198			`y2r <= y2sh+y2w(f_factors_part-1);`
199			`y3r <= y3sh+y3w(f_factors_part-1);`
200
201			`if (y1r(data_width+int_factors_part-1)='1' and y1r(data_width)='1')then y1ro(data_width-1 downto 0)<=(others=>'0');`
202			`elsif (y1r(data_width+int_factors_part-1)='0' and y1r(data_width)='1')then y1ro(data_width-1 downto 0)<=(others=>'1');`
203			`else y1ro<=y1r;`
204			`end if;`
205
206			`if (y2r(data_width+int_factors_part-1)='1' and y2r(data_width)='1')then y2ro(data_width-1 downto 0)<=(others=>'0');`
207			`elsif (y2r(data_width+int_factors_part-1)='0' and y2r(data_width)='1')then y2ro(data_width-1 downto 0)<=(others=>'1');`
208			`else y2ro<=y2r;`
209			`end if;`
210
211			`if (y3r(data_width+int_factors_part-1)='1' and y3r(data_width)='1')then y3ro(data_width-1 downto 0)<=(others=>'0');`
212			`elsif (y3r(data_width+int_factors_part-1)='0' and y3r(data_width)='1')then y3ro(data_width-1 downto 0)<=(others=>'1');`
213			`else y3ro<=y3r;`
214			`end if;`
215
216			`end if;`
217			`end process;`
218
219			`y1c <= y1r(data_width+int_factors_part-1 downto data_width);`
220			`y2c <= y2r(data_width+int_factors_part-1 downto data_width);`
221			`y3c <= y3r(data_width+int_factors_part-1 downto data_width);`
222
223			`y1 <= UNSIGNED(y1ro(data_width-1 downto 0));`
224			`y2 <= UNSIGNED(y2ro(data_width-1 downto 0));`
225			`y3 <= UNSIGNED(y3ro(data_width-1 downto 0));`
226
227			`-- this shift register is nessecary for generating RDY sig and easy integration with fifo`
228			`process(clk, rstn)`
229			`begin`
230			`if rstn = '0' then`
231			`pipe_delay <= (others=>'0');`
232			`elsif rising_edge(clk) then`
233			`pipe_delay(0) <= DATA_ENA;`
234			`pipe_delay(7 downto 1) <= pipe_delay(6 downto 0);`
235			`end if;`
236			`end process;`
237
238			`DOUT_RDY <= pipe_delay(7);`
239
240
241			`end a;`