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/*******************************************************************
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*
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* CAUTION: This file is automatically generated by libgen.
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* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
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* DO NOT EDIT.
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*
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* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
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*
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* Description: Driver parameters
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*
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*******************************************************************/
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#define STDIN_BASEADDRESS 0x40600000
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#define STDOUT_BASEADDRESS 0x40600000
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/******************************************************************/
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#define XPAR_DLMB_CNTLR_BASEADDR 0x00000000
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#define XPAR_DLMB_CNTLR_HIGHADDR 0x0000FFFF
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#define XPAR_DATA_BRAM_IF_CNTLR_0_BASEADDR 0x70000000
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#define XPAR_DATA_BRAM_IF_CNTLR_0_HIGHADDR 0x7000FFFF
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#define XPAR_DATA_BRAM_IF_CNTLR_1_BASEADDR 0x70010000
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#define XPAR_DATA_BRAM_IF_CNTLR_1_HIGHADDR 0x7001FFFF
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#define XPAR_ILMB_CNTLR_BASEADDR 0x00000000
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#define XPAR_ILMB_CNTLR_HIGHADDR 0x0000FFFF
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/******************************************************************/
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#define XPAR_XUARTLITE_NUM_INSTANCES 2
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#define XPAR_DEBUG_MODULE_BASEADDR 0x41400000
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#define XPAR_DEBUG_MODULE_HIGHADDR 0x4140FFFF
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#define XPAR_DEBUG_MODULE_DEVICE_ID 0
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#define XPAR_DEBUG_MODULE_BAUDRATE 0
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#define XPAR_DEBUG_MODULE_USE_PARITY 0
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#define XPAR_DEBUG_MODULE_ODD_PARITY 0
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#define XPAR_DEBUG_MODULE_DATA_BITS 0
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#define XPAR_RS232_UART_1_BASEADDR 0x40600000
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#define XPAR_RS232_UART_1_HIGHADDR 0x4060FFFF
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#define XPAR_RS232_UART_1_DEVICE_ID 1
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#define XPAR_RS232_UART_1_BAUDRATE 9600
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#define XPAR_RS232_UART_1_USE_PARITY 0
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#define XPAR_RS232_UART_1_ODD_PARITY 0
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#define XPAR_RS232_UART_1_DATA_BITS 8
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/******************************************************************/
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#define XPAR_XSYSACE_MEM_WIDTH 16
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#define XPAR_XSYSACE_NUM_INSTANCES 1
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#define XPAR_SYSACE_COMPACTFLASH_BASEADDR 0x41800000
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#define XPAR_SYSACE_COMPACTFLASH_HIGHADDR 0x4180FFFF
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#define XPAR_SYSACE_COMPACTFLASH_DEVICE_ID 0
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#define XPAR_SYSACE_COMPACTFLASH_MEM_WIDTH 16
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/******************************************************************/
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#define XPAR_XGPIO_NUM_INSTANCES 3
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#define XPAR_LEDS_4BIT_BASEADDR 0x40020000
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#define XPAR_LEDS_4BIT_HIGHADDR 0x4002FFFF
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#define XPAR_LEDS_4BIT_DEVICE_ID 0
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#define XPAR_LEDS_4BIT_INTERRUPT_PRESENT 0
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#define XPAR_LEDS_4BIT_IS_DUAL 0
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#define XPAR_DIPSWS_4BIT_BASEADDR 0x40040000
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#define XPAR_DIPSWS_4BIT_HIGHADDR 0x4004FFFF
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#define XPAR_DIPSWS_4BIT_DEVICE_ID 1
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#define XPAR_DIPSWS_4BIT_INTERRUPT_PRESENT 0
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#define XPAR_DIPSWS_4BIT_IS_DUAL 0
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#define XPAR_PUSHBUTTONS_5BIT_BASEADDR 0x40000000
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#define XPAR_PUSHBUTTONS_5BIT_HIGHADDR 0x4000FFFF
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#define XPAR_PUSHBUTTONS_5BIT_DEVICE_ID 2
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#define XPAR_PUSHBUTTONS_5BIT_INTERRUPT_PRESENT 0
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#define XPAR_PUSHBUTTONS_5BIT_IS_DUAL 0
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/******************************************************************/
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#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 100000000
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/******************************************************************/
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#define XILFATFS_MAXFILES 5
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#define XILFATFS_BUFCACHE_SIZE 10240
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