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URL https://opencores.org/ocsvn/mb-jpeg/mb-jpeg/trunk

Subversion Repositories mb-jpeg

[/] [mb-jpeg/] [tags/] [STEP1_1/] [system.log] - Blame information for rev 4

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1 4 quickwayne 
Xilinx Platform Studio (XPS)
2 
Xilinx EDK 7.1.2 Build EDK_H.12.5.1
3 
 
4 
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
5 
 
6 
Created pcores directory
7 
Copied file bitgen.ut from $XILINX_EDK/data/xflow directory to etc directory
8 
Copied file bitgen_spartan3.ut from $XILINX_EDK/data directory to etc directory
9 
Copied file fast_runtime.opt from $XILINX_EDK/data/xflow directory to etc directory
10 
WARNING:MDT - Created an empty D:\mb-jpeg\data\system.ucf. If your design needs any constraints, please make changes to this UCF file.
11 
Project Opened.
12 
Assigned Driver bram 1.00.a for instance lmb_bram_if_cntlr_0
13 
Assigned Driver bram 1.00.a for instance lmb_bram_if_cntlr_1
14 
 
15 
Saving MSS changes, if any.
16 
 
17 
Loading Project File..
18 
No changes to be saved in XMP file
19 
Project Opened.
20 
At Local date and time: Fri Jun 23 16:07:28 2006
21 
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make netlist; exit;" Started...
22 
****************************************************
23 
Creating system netlist for hardware specification..
24 
****************************************************
25 
platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/  -st xst system.mhs
26 
 
27 
Release Xilinx EDK 7.1.2 - platgen EDK_H.12.5.1
28 
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
29 
 
30 
Command Line: platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xst
31 
system.mhs
32 
 
33 
Parse system.mhs ...
34 
 
35 
Read MPD definitions ...
36 
Sourcing tcl file
37 
C:/edk/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.
38 
tcl ...
39 
Sourcing tcl file
40 
C:/edk/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl
41 
...
42 
Sourcing tcl file
43 
C:/edk/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if
44 
_cntlr_v2_1_0.tcl ...
45 
Sourcing tcl file
46 
C:/edk/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.
47 
tcl ...
48 
 
49 
Overriding IP level properties ...
50 
microblaze (microblaze_0) -
51 
C:\edk\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
52 
mpd:60 - tool overriding c_family value virtex2 to virtex2p
53 
microblaze (microblaze_0) -
54 
C:\edk\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
55 
mpd:61 - tool overriding c_instance value microblaze to microblaze_0
56 
microblaze (microblaze_0) -
57 
C:\edk\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
58 
mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0
59 
microblaze (microblaze_0) -
60 
C:\edk\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
61 
mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0
62 
opb_mdm (debug_module) -
63 
C:\edk\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38
64 
- tool overriding c_family value virtex2 to virtex2p
65 
bram_block (lmb_bram) -
66 
C:\edk\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
67 
mpd:39 - tool overriding c_family value virtex2 to virtex2p
68 
opb_gpio (leds_4bit) -
69 
C:\edk\hw\XilinxProcessorIPLib\pcores\opb_gpio_v3_01_b\data\opb_gpio_v2_1_0.mpd:
70 
38 - tool overriding c_family value virtex2 to virtex2p
71 
opb_gpio (dipsws_4bit) -
72 
C:\edk\hw\XilinxProcessorIPLib\pcores\opb_gpio_v3_01_b\data\opb_gpio_v2_1_0.mpd:
73 
38 - tool overriding c_family value virtex2 to virtex2p
74 
opb_gpio (pushbuttons_5bit) -
75 
C:\edk\hw\XilinxProcessorIPLib\pcores\opb_gpio_v3_01_b\data\opb_gpio_v2_1_0.mpd:
76 
38 - tool overriding c_family value virtex2 to virtex2p
77 
dcm_module (dcm_0) -
78 
C:\edk\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
79 
mpd:56 - tool overriding c_family value virtex2 to virtex2p
80 
bram_block (data_bram_0) -
81 
C:\edk\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
82 
mpd:39 - tool overriding c_family value virtex2 to virtex2p
83 
bram_block (data_bram_1) -
84 
C:\edk\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
85 
mpd:39 - tool overriding c_family value virtex2 to virtex2p
86 
 
87 
Performing IP level DRCs on properties...
88 
 
89 
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
90 
Address Map for Processor microblaze_0
91 
  (0x00000000-0x0000ffff) dlmb_cntlr    dlmb
92 
  (0x00000000-0x0000ffff) ilmb_cntlr    ilmb
93 
  (0x40000000-0x4000ffff) PushButtons_5Bit      mb_opb
94 
  (0x40020000-0x4002ffff) LEDs_4Bit     mb_opb
95 
  (0x40040000-0x4004ffff) DIPSWs_4Bit   mb_opb
96 
  (0x40600000-0x4060ffff) RS232_Uart_1  mb_opb
97 
  (0x41400000-0x4140ffff) debug_module  mb_opb
98 
  (0x41800000-0x4180ffff) SysACE_CompactFlash   mb_opb
99 
  (0x70000000-0x7000ffff) data_bram_if_cntlr_0  dlmb
100 
  (0x70010000-0x7001ffff) data_bram_if_cntlr_1  dlmb
101 
 
102 
Check platform configuration ...
103 
opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:55 - 2 master(s) : 6 slave(s)
104 
lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:81 - 1 master(s) : 1 slave(s)
105 
lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:89 - 1 master(s) : 3 slave(s)
106 
 
107 
Check port drivers...
108 
 
109 
Check platform address map ...
110 
 
111 
Overriding system level properties ...
112 
opb_v20 (mb_opb) -
113 
C:\edk\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36
114 
- tool overriding c_num_masters value 4 to 2
115 
opb_v20 (mb_opb) -
116 
C:\edk\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:37
117 
- tool overriding c_num_slaves value 4 to 6
118 
lmb_v10 (ilmb) -
119 
C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
120 
- tool overriding c_lmb_num_slaves value 4 to 1
121 
lmb_v10 (dlmb) -
122 
C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
123 
- tool overriding c_lmb_num_slaves value 4 to 3
124 
lmb_bram_if_cntlr (dlmb_cntlr) -
125 
C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
126 
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x70c70000
127 
lmb_bram_if_cntlr (ilmb_cntlr) -
128 
C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
129 
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x70c70000
130 
bram_block (lmb_bram) -
131 
C:\edk\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
132 
mpd:35 - tool overriding c_memsize value 2048 to 65536
133 
bram_block (data_bram_0) - D:\mb-jpeg\system.mhs:214 - tool overriding c_memsize
134 
value 16384 to 65536
135 
lmb_bram_if_cntlr (data_bram_if_cntlr_0) -
136 
C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
137 
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x70c70000
138 
bram_block (data_bram_1) - D:\mb-jpeg\system.mhs:230 - tool overriding c_memsize
139 
value 16384 to 65536
140 
lmb_bram_if_cntlr (data_bram_if_cntlr_1) -
141 
C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
142 
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x70c70000
143 
 
144 
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
145 
 
146 
Performing System level DRCs on properties...
147 
 
148 
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
149 
 
150 
Modify defaults ...
151 
 
152 
Processing licensed instances ...
153 
Completion time: 0.00 seconds
154 
 
155 
Creating hardware output directories ...
156 
 
157 
Managing hardware (BBD-specified) netlist files ...
158 
 
159 
Managing cache ...
160 
 
161 
Elaborating instances ...
162 
bram_block (lmb_bram) - D:\mb-jpeg\system.mhs:115 - elaborating IP
163 
bram_block (data_bram_0) - D:\mb-jpeg\system.mhs:211 - elaborating IP
164 
bram_block (data_bram_1) - D:\mb-jpeg\system.mhs:227 - elaborating IP
165 
 
166 
Writing HDL for elaborated instances ...
167 
 
168 
Inserting wrapper level ...
169 
Completion time: 4.00 seconds
170 
 
171 
Constructing platform-level signal connectivity ...
172 
Completion time: 2.00 seconds
173 
 
174 
Writing (top-level) BMM ...
175 
Writing BMM - D:\mb-jpeg\implementation\system.bmm
176 
 
177 
Writing (top-level and wrappers) HDL ...
178 
 
179 
Generating synthesis project file ...
180 
 
181 
Running XST synthesis ...
182 
INFO:MDT - The following instances are synthesized with XST. The MPD option
183 
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
184 
   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
185 
microblaze_0_wrapper (microblaze_0) - D:\mb-jpeg\system.mhs:35 - Running XST
186 
synthesis
187 
mb_opb_wrapper (mb_opb) - D:\mb-jpeg\system.mhs:55 - Running XST synthesis
188 
debug_module_wrapper (debug_module) - D:\mb-jpeg\system.mhs:63 - Running XST
189 
synthesis
190 
ilmb_wrapper (ilmb) - D:\mb-jpeg\system.mhs:81 - Running XST synthesis
191 
dlmb_wrapper (dlmb) - D:\mb-jpeg\system.mhs:89 - Running XST synthesis
192 
dlmb_cntlr_wrapper (dlmb_cntlr) - D:\mb-jpeg\system.mhs:97 - Running XST
193 
synthesis
194 
ilmb_cntlr_wrapper (ilmb_cntlr) - D:\mb-jpeg\system.mhs:106 - Running XST
195 
synthesis
196 
lmb_bram_wrapper (lmb_bram) - D:\mb-jpeg\system.mhs:115 - Running XST synthesis
197 
rs232_uart_1_wrapper (rs232_uart_1) - D:\mb-jpeg\system.mhs:122 - Running XST
198 
synthesis
199 
sysace_compactflash_wrapper (sysace_compactflash) - D:\mb-jpeg\system.mhs:138 -
200 
Running XST synthesis
201 
leds_4bit_wrapper (leds_4bit) - D:\mb-jpeg\system.mhs:155 - Running XST
202 
synthesis
203 
dipsws_4bit_wrapper (dipsws_4bit) - D:\mb-jpeg\system.mhs:169 - Running XST
204 
synthesis
205 
pushbuttons_5bit_wrapper (pushbuttons_5bit) - D:\mb-jpeg\system.mhs:183 -
206 
Running XST synthesis
207 
dcm_0_wrapper (dcm_0) - D:\mb-jpeg\system.mhs:197 - Running XST synthesis
208 
data_bram_0_wrapper (data_bram_0) - D:\mb-jpeg\system.mhs:211 - Running XST
209 
synthesis
210 
data_bram_if_cntlr_0_wrapper (data_bram_if_cntlr_0) - D:\mb-jpeg\system.mhs:218
211 
- Running XST synthesis
212 
data_bram_1_wrapper (data_bram_1) - D:\mb-jpeg\system.mhs:227 - Running XST
213 
synthesis
214 
data_bram_if_cntlr_1_wrapper (data_bram_if_cntlr_1) - D:\mb-jpeg\system.mhs:234
215 
- Running XST synthesis
216 
 
217 
Running NGCBUILD ...
218 
 
219 
Rebuilding cache ...
220 
Total run time: 300.00 seconds
221 
Running synthesis...
222 
bash -c "cd synthesis; ./synthesis.sh; cd .."
223 
WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 33
224 
   days, this program will not operate. For more information about this product,
225 
   please refer to the Evaluation Agreement, which was shipped to you along with
226 
   the Evaluation CDs.
227 
   To purchase an annual license for this software, please contact your local
228 
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
229 
   or if we can assist in any way, please send an email to: eval@xilinx.com
230 
   Thank You!
231 
Release 7.1.02i - xst H.42
232 
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
233 
-->
234 
TABLE OF CONTENTS
235 
  1) Synthesis Options Summary
236 
  2) HDL Compilation
237 
  3) HDL Analysis
238 
  4) HDL Synthesis
239 
  5) Advanced HDL Synthesis
240 
     5.1) HDL Synthesis Report
241 
  6) Low Level Synthesis
242 
  7) Final Report
243 
     7.1) Device utilization summary
244 
     7.2) TIMING REPORT
245 
 
246 
 
247 
=========================================================================
248 
*                      Synthesis Options Summary                        *
249 
=========================================================================
250 
---- Source Parameters
251 
Input Format                       : MIXED
252 
Input File Name                    : "system_xst.prj"
253 
 
254 
---- Target Parameters
255 
Target Device                      : xc2vp30ff896-7
256 
Output File Name                   : "../implementation/system.ngc"
257 
 
258 
---- Source Options
259 
Top Module Name                    : system
260 
 
261 
---- Target Options
262 
Add IO Buffers                     : NO
263 
 
264 
---- General Options
265 
Optimization Goal                  : speed
266 
RTL Output                         : YES
267 
Hierarchy Separator                : /
268 
 
269 
=========================================================================
270 
 
271 
WARNING:Xst:29 - Optimization Effort not specified
272 
The following parameters have been added:
273 
Optimization Effort                : 1
274 
 
275 
=========================================================================
276 
 
277 
=========================================================================
278 
*                          HDL Compilation                              *
279 
=========================================================================
280 
Compiling vhdl file "d:/mb-jpeg/synthesis/../hdl/system.vhd" in Library work.
281 
Entity  compiled.
282 
Entity  (Architecture ) compiled.
283 
 
284 
=========================================================================
285 
*                            HDL Analysis                               *
286 
=========================================================================
287 
Analyzing Entity  (Architecture ).
288 
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1608: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1614: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1620: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1626: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1632: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1638: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1644: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1650: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1656: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1662: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1668: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1676: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1684: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1692: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1700: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1708: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1716: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1724: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1732: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1740: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1748: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1756: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1764: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1772: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1780: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1788: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1796: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1802: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1808: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1814: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1820: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1828: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1836: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1844: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1852: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1860: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1868: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1876: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1884: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1892: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1900: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1908: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1916: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1924: Generating a Black Box for component .
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WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1930: Generating a Black Box for component .
333 
Entity  analyzed. Unit  generated.
334 
 
335 
 
336 
=========================================================================
337 
*                           HDL Synthesis                               *
338 
=========================================================================
339 
 
340 
Synthesizing Unit .
341 
    Related source file is "d:/mb-jpeg/synthesis/../hdl/system.vhd".
342 
Unit  synthesized.
343 
 
344 
 
345 
=========================================================================
346 
*                       Advanced HDL Synthesis                          *
347 
=========================================================================
348 
 
349 
Advanced RAM inference ...
350 
Advanced multiplier inference ...
351 
Advanced Registered AddSub inference ...
352 
Dynamic shift register inference ...
353 
 
354 
=========================================================================
355 
HDL Synthesis Report
356 
 
357 
Found no macro
358 
=========================================================================
359 
 
360 
=========================================================================
361 
*                         Low Level Synthesis                           *
362 
=========================================================================
363 
Loading device for application Rf_Device from file '2vp30.nph' in environment c:/ISE.
364 
 
365 
Optimizing unit  ...
366 
 
367 
Mapping all equations...
368 
Building and optimizing final netlist ...
369 
 
370 
=========================================================================
371 
*                            Final Report                               *
372 
=========================================================================
373 
Final Results
374 
RTL Top Level Output File Name     : ../implementation/system.ngr
375 
Top Level Output File Name         : ../implementation/system.ngc
376 
Output Format                      : ngc
377 
Optimization Goal                  : speed
378 
Keep Hierarchy                     : no
379 
 
380 
Design Statistics
381 
# IOs                              : 45
382 
 
383 
Cell Usage :
384 
# BELS                             : 2
385 
#      GND                         : 1
386 
#      VCC                         : 1
387 
# IO Buffers                       : 45
388 
#      IBUF                        : 4
389 
#      IBUFG                       : 1
390 
#      IOBUF                       : 29
391 
#      OBUF                        : 11
392 
# Others                           : 18
393 
#      data_bram_0_wrapper         : 1
394 
#      data_bram_1_wrapper         : 1
395 
#      data_bram_if_cntlr_0_wrapper: 1
396 
#      data_bram_if_cntlr_1_wrapper: 1
397 
#      dcm_0_wrapper               : 1
398 
#      debug_module_wrapper        : 1
399 
#      dipsws_4bit_wrapper         : 1
400 
#      dlmb_cntlr_wrapper          : 1
401 
#      dlmb_wrapper                : 1
402 
#      ilmb_cntlr_wrapper          : 1
403 
#      ilmb_wrapper                : 1
404 
#      leds_4bit_wrapper           : 1
405 
#      lmb_bram_wrapper            : 1
406 
#      mb_opb_wrapper              : 1
407 
#      microblaze_0_wrapper        : 1
408 
#      pushbuttons_5bit_wrapper    : 1
409 
#      rs232_uart_1_wrapper        : 1
410 
#      sysace_compactflash_wrapper : 1
411 
=========================================================================
412 
 
413 
Device utilization summary:
414 
---------------------------
415 
 
416 
Selected Device : 2vp30ff896-7
417 
 
418 
 Number of bonded IOBs:                 45  out of    556     8%
419 
 
420 
=========================================================================
421 
TIMING REPORT
422 
 
423 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
424 
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
425 
      GENERATED AFTER PLACE-and-ROUTE.
426 
 
427 
Clock Information:
428 
------------------
429 
No clock signals found in this design
430 
 
431 
Timing Summary:
432 
---------------
433 
Speed Grade: -7
434 
 
435 
   Minimum period: No path found
436 
   Minimum input arrival time before clock: No path found
437 
   Maximum output required time after clock: No path found
438 
   Maximum combinational path delay: 2.924ns
439 
 
440 
Timing Detail:
441 
--------------
442 
All values displayed in nanoseconds (ns)
443 
 
444 
=========================================================================
445 
Timing constraint: Default path analysis
446 
  Total number of paths / destination ports: 2006 / 1977
447 
-------------------------------------------------------------------------
448 
Delay:               2.924ns (Levels of Logic = 1)
449 
  Source:            sysace_compactflash:SysACE_MPD_O<3> (PAD)
450 
  Destination:       fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> (PAD)
451 
 
452 
  Data Path: sysace_compactflash:SysACE_MPD_O<3> to fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3>
453 
                                Gate     Net
454 
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
455 
    ----------------------------------------  ------------
456 
    sysace_compactflash_wrapper:SysACE_MPD_O<3>    1   0.000   0.332  sysace_compactflash (fpga_0_SysACE_CompactFlash_SysACE_MPD_O<3>)
457 
     IOBUF:I->IO               2.592          iobuf_22 (fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3>)
458 
    ----------------------------------------
459 
    Total                      2.924ns (2.592ns logic, 0.332ns route)
460 
                                       (88.7% logic, 11.3% route)
461 
 
462 
=========================================================================
463 
CPU : 10.82 / 10.98 s | Elapsed : 11.00 / 11.00 s
464 
 
465 
-->
466 
 
467 
Total memory usage is 160856 kilobytes
468 
 
469 
Number of errors   :    0 (   0 filtered)
470 
Number of warnings :   47 (   0 filtered)
471 
Number of infos    :    0 (   0 filtered)
472 
Done.
473 
At Local date and time: Fri Jun 23 16:12:51 2006
474 
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make bits; exit;" Started...
475 
Copying Xilinx Implementation tool scripts..
476 
*********************************************
477 
Running Xilinx Implementation tools..
478 
*********************************************
479 
xflow -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt system.ngc
480 
Release 7.1.02i - Xflow H.38
481 
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
482 
xflow.exe -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt
483 
system.ngc
484 
.... Copying flowfile c:/ISE/xilinx/data/fpga.flw into working directory
485 
D:/mb-jpeg/implementation
486 
 
487 
Using Flow File: D:/mb-jpeg/implementation/fpga.flw
488 
Using Option File(s):
489 
 D:/mb-jpeg/implementation/fast_runtime.opt
490 
 
491 
Creating Script File ...
492 
 
493 
#----------------------------------------------#
494 
# Starting program ngdbuild
495 
# ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm
496 
D:/mb-jpeg/implementation/system.ngc -uc system.ucf system.ngd
497 
#----------------------------------------------#
498 
Release 7.1.02i - ngdbuild H.42
499 
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
500 
 
501 
Command Line: ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm -uc
502 
system.ucf D:/mb-jpeg/implementation/system.ngc system.ngd
503 
 
504 
Reading NGO file 'D:/mb-jpeg/implementation/system.ngc' ...
505 
Loading design module "D:/mb-jpeg/implementation/microblaze_0_wrapper.ngc"...
506 
Loading design module "D:/mb-jpeg/implementation/mb_opb_wrapper.ngc"...
507 
Loading design module "D:/mb-jpeg/implementation/debug_module_wrapper.ngc"...
508 
Loading design module "D:/mb-jpeg/implementation/ilmb_wrapper.ngc"...
509 
Loading design module "D:/mb-jpeg/implementation/dlmb_wrapper.ngc"...
510 
Loading design module "D:/mb-jpeg/implementation/dlmb_cntlr_wrapper.ngc"...
511 
Loading design module "D:/mb-jpeg/implementation/ilmb_cntlr_wrapper.ngc"...
512 
Loading design module "D:/mb-jpeg/implementation/lmb_bram_wrapper.ngc"...
513 
Loading design module "D:/mb-jpeg/implementation/rs232_uart_1_wrapper.ngc"...
514 
Loading design module
515 
"D:/mb-jpeg/implementation/sysace_compactflash_wrapper.ngc"...
516 
Loading design module "D:/mb-jpeg/implementation/leds_4bit_wrapper.ngc"...
517 
Loading design module "D:/mb-jpeg/implementation/dipsws_4bit_wrapper.ngc"...
518 
Loading design module
519 
"D:/mb-jpeg/implementation/pushbuttons_5bit_wrapper.ngc"...
520 
Loading design module "D:/mb-jpeg/implementation/dcm_0_wrapper.ngc"...
521 
Loading design module "D:/mb-jpeg/implementation/data_bram_0_wrapper.ngc"...
522 
Loading design module
523 
"D:/mb-jpeg/implementation/data_bram_if_cntlr_0_wrapper.ngc"...
524 
Loading design module "D:/mb-jpeg/implementation/data_bram_1_wrapper.ngc"...
525 
Loading design module
526 
"D:/mb-jpeg/implementation/data_bram_if_cntlr_1_wrapper.ngc"...
527 
 
528 
Applying constraints in "system.ucf" to the design...
529 
 
530 
Checking timing specifications ...
531 
INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification
532 
   "TS_sys_clk_pin", was traced into DCM instance "dcm_0/dcm_0/DCM_INST". The
533 
   following new TNM groups and period specifications were generated at the DCM
534 
   output(s):
535 
   CLK0: TS_dcm_0_dcm_0_CLK0_BUF=PERIOD dcm_0_dcm_0_CLK0_BUF
536 
TS_sys_clk_pin*1.000000 HIGH 50.000000%
537 
 
538 
Processing BMM file ...
539 
 
540 
Checking expanded design ...
541 
WARNING:NgdBuild:452 - logical net
542 
   'microblaze_0/microblaze_0/Data_Flow_I/word_r1_r2_unalignment' has no driver
543 
WARNING:NgdBuild:452 - logical net
544 
   'microblaze_0/microblaze_0/Data_Flow_I/word_r1_imm_unalignment' has no driver
545 
WARNING:NgdBuild:452 - logical net
546 
   'microblaze_0/microblaze_0/Data_Flow_I/halfword_unalignment' has no driver
547 
WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clock driver
548 
   debug_module/debug_module/BUFG_DRCK1 drives no clock pins
549 
 
550 
NGDBUILD Design Results Summary:
551 
  Number of errors:     0
552 
  Number of warnings:   4
553 
 
554 
Writing NGD file "system.ngd" ...
555 
 
556 
Writing NGDBUILD log file "system.bld"...
557 
 
558 
NGDBUILD done.
559 
 
560 
 
561 
 
562 
#----------------------------------------------#
563 
# Starting program map
564 
# map -o system_map.ncd -pr b system.ngd system.pcf
565 
#----------------------------------------------#
566 
Release 7.1.02i - Map H.42
567 
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
568 
Using target part "2vp30ff896-7".
569 
Mapping design into LUTs...
570 
Writing file system_map.ngm...
571 
Running directed packing...
572 
Running delay-based LUT packing...
573 
Running related packing...
574 
Writing design file "system_map.ncd"...
575 
 
576 
Design Summary:
577 
Number of errors:      0
578 
Number of warnings:    8
579 
Logic Utilization:
580 
  Number of Slice Flip Flops:       1,186 out of  27,392    4%
581 
  Number of 4 input LUTs:           1,466 out of  27,392    5%
582 
Logic Distribution:
583 
  Number of occupied Slices:        1,296 out of  13,696    9%
584 
  Number of Slices containing only related logic:   1,296 out of   1,296  100%
585 
  Number of Slices containing unrelated logic:          0 out of   1,296    0%
586 
        *See NOTES below for an explanation of the effects of unrelated logic
587 
Total Number 4 input LUTs:          1,899 out of  27,392    6%
588 
  Number used as logic:             1,466
589 
  Number used as a route-thru:         15
590 
  Number used for Dual Port RAMs:     256
591 
    (Two LUTs used per Dual Port RAM)
592 
  Number used as Shift registers:     162
593 
 
594 
  Number of bonded IOBs:               44 out of     556    7%
595 
    IOB Flip Flops:                    73
596 
  Number of PPC405s:                   0 out of       2    0%
597 
  Number of Block RAMs:                96 out of     136   70%
598 
  Number of MULT18X18s:                 3 out of     136    2%
599 
  Number of GCLKs:                      2 out of      16   12%
600 
  Number of DCMs:                       1 out of       8   12%
601 
  Number of BSCANs:                     1 out of       1  100%
602 
  Number of GTs:                        0 out of       8    0%
603 
  Number of GT10s:                      0 out of       0    0%
604 
 
605 
   Number of RPM macros:            5
606 
Total equivalent gate count for design:  6,374,492
607 
Additional JTAG gate count for IOBs:  2,112
608 
Peak Memory Usage:  193 MB
609 
 
610 
NOTES:
611 
 
612 
   Related logic is defined as being logic that shares connectivity - e.g. two
613 
   LUTs are "related" if they share common inputs.  When assembling slices,
614 
   Map gives priority to combine logic that is related.  Doing so results in
615 
   the best timing performance.
616 
 
617 
   Unrelated logic shares no connectivity.  Map will only begin packing
618 
   unrelated logic into a slice once 99% of the slices are occupied through
619 
   related logic packing.
620 
 
621 
   Note that once logic distribution reaches the 99% level through related
622 
   logic packing, this does not mean the device is completely utilized.
623 
   Unrelated logic packing will then begin, continuing until all usable LUTs
624 
   and FFs are occupied.  Depending on your timing budget, increased levels of
625 
   unrelated logic packing may adversely affect the overall timing performance
626 
   of your design.
627 
 
628 
Mapping completed.
629 
See MAP report file "system_map.mrp" for details.
630 
 
631 
 
632 
 
633 
#----------------------------------------------#
634 
# Starting program par
635 
# par -w -ol high system_map.ncd system.ncd system.pcf
636 
#----------------------------------------------#
637 
Release 7.1.02i - par H.42
638 
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
639 
 
640 
 
641 
 
642 
Constraints file: system.pcf.
643 
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 33
644 
   days, this program will not operate. For more information about this product,
645 
   please refer to the Evaluation Agreement, which was shipped to you along with
646 
   the Evaluation CDs.
647 
   To purchase an annual license for this software, please contact your local
648 
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
649 
   or if we can assist in any way, please send an email to: eval@xilinx.com
650 
   Thank You!
651 
Loading device for application Rf_Device from file '2vp30.nph' in environment
652 
c:/ISE.
653 
   "system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
654 
 
655 
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000
656 
Celsius)
657 
Initializing voltage to 1.500 Volts. (default - Range: 1.400 to 1.600 Volts)
658 
 
659 
Device speed data version:  "PRODUCTION 1.91 2005-07-22".
660 
 
661 
 
662 
Device Utilization Summary:
663 
 
664 
   Number of BSCANs                    1 out of 1     100%
665 
   Number of BUFGMUXs                  2 out of 16     12%
666 
   Number of DCMs                      1 out of 8      12%
667 
   Number of External IOBs            44 out of 556     7%
668 
      Number of LOCed IOBs            44 out of 44    100%
669 
 
670 
   Number of MULT18X18s                3 out of 136     2%
671 
   Number of RAMB16s                  96 out of 136    70%
672 
   Number of SLICEs                 1296 out of 13696   9%
673 
 
674 
 
675 
Overall effort level (-ol):   High (set by user)
676 
Placer effort level (-pl):    High (set by user)
677 
Placer cost table entry (-t): 1
678 
Router effort level (-rl):    High (set by user)
679 
 
680 
Starting initial Timing Analysis.  REAL time: 6 secs
681 
Finished initial Timing Analysis.  REAL time: 7 secs
682 
 
683 
 
684 
Starting Placer
685 
 
686 
Phase 1.1
687 
Phase 1.1 (Checksum:9b1b32) REAL time: 9 secs
688 
 
689 
Phase 2.31
690 
Phase 2.31 (Checksum:1312cfe) REAL time: 9 secs
691 
 
692 
WARNING:Place:414 - The input design contains local clock signal(s). To get the
693 
   better result, we recommend users run map with the "-timing" option set
694 
   before starting the placement.
695 
Phase 3.2
696 
.
697 
 
698 
 
699 
Phase 3.2 (Checksum:1c9c37d) REAL time: 15 secs
700 
 
701 
Phase 4.30
702 
Phase 4.30 (Checksum:26259fc) REAL time: 15 secs
703 
 
704 
Phase 5.3
705 
Phase 5.3 (Checksum:2faf07b) REAL time: 16 secs
706 
 
707 
Phase 6.5
708 
Phase 6.5 (Checksum:39386fa) REAL time: 16 secs
709 
 
710 
Phase 7.8
711 
.......................................................
712 
.......
713 
........................................................
714 
.........
715 
.......
716 
Phase 7.8 (Checksum:1036ece) REAL time: 30 secs
717 
 
718 
Phase 8.5
719 
Phase 8.5 (Checksum:4c4b3f8) REAL time: 30 secs
720 
 
721 
Phase 9.18
722 
Phase 9.18 (Checksum:55d4a77) REAL time: 37 secs
723 
 
724 
Phase 10.5
725 
Phase 10.5 (Checksum:5f5e0f6) REAL time: 37 secs
726 
 
727 
Phase 11.27
728 
Phase 11.27 (Checksum:68e7775) REAL time: 38 secs
729 
 
730 
Phase 12.24
731 
Phase 12.24 (Checksum:7270df4) REAL time: 38 secs
732 
Writing design to file system.ncd
733 
 
734 
 
735 
Total REAL time to Placer completion: 41 secs
736 
Total CPU time to Placer completion: 35 secs
737 
 
738 
Starting Router
739 
Phase 1: 15230 unrouted;       REAL time: 53 secs
740 
Phase 2: 13515 unrouted;       REAL time: 54 secs
741 
Phase 3: 3706 unrouted;       REAL time: 1 mins
742 
 
743 
Phase 4: 3706 unrouted; (71354)      REAL time: 1 mins 1 secs
744 
Phase 5: 3783 unrouted; (306)      REAL time: 1 mins 14 secs
745 
Phase 6: 3788 unrouted; (0)      REAL time: 1 mins 19 secs
746 
Phase 7: 0 unrouted; (0)      REAL time: 1 mins 35 secs
747 
Phase 8: 0 unrouted; (0)      REAL time: 1 mins 38 secs
748 
 
749 
Total REAL time to Router completion: 1 mins 44 secs
750 
Total CPU time to Router completion: 1 mins 32 secs
751 
 
752 
Generating "PAR" statistics.
753 
 
754 
**************************
755 
Generating Clock Report
756 
**************************
757 
 
758 
+---------------------+--------------+------+------+------------+-------------+
759 
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
760 
+---------------------+--------------+------+------+------------+-------------+
761 
|data_bram_0_port_BRA |              |      |      |            |             |
762 
|               M_Clk |     BUFGMUX7S| No   |  943 |  0.281     |  1.258      |
763 
+---------------------+--------------+------+------+------------+-------------+
764 
|           DBG_CLK_s |     BUFGMUX4P| No   |  139 |  0.267     |  1.257      |
765 
+---------------------+--------------+------+------+------------+-------------+
766 
|fpga_0_SysACE_Compac |              |      |      |            |             |
767 
|   tFlash_SysACE_CLK |         Local|      |   65 |  0.281     |  2.475      |
768 
+---------------------+--------------+------+------+------------+-------------+
769 
|debug_module/bscan_u |              |      |      |            |             |
770 
|               pdate |         Local|      |    1 |  0.000     |  0.356      |
771 
+---------------------+--------------+------+------+------------+-------------+
772 
Timing Score: 0
773 
 
774 
Asterisk (*) preceding a constraint indicates it was not met.
775 
   This may be due to a setup or hold violation.
776 
 
777 
--------------------------------------------------------------------------------
778 
  Constraint                                | Requested  | Actual     | Logic
779 
                                            |            |            | Levels
780 
--------------------------------------------------------------------------------
781 
  NET "fpga_0_SysACE_CompactFlash_SysACE_CL | 30.000ns   | 4.555ns    | 2
782 
  K" PERIOD = 30 ns HIGH 50%                |            |            |
783 
--------------------------------------------------------------------------------
784 
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | N/A        | N/A        | N/A
785 
  pin" 10 ns HIGH 50%                       |            |            |
786 
--------------------------------------------------------------------------------
787 
  TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP  | 10.000ns   | 9.935ns    | 11
788 
  "dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin     |            |            |
789 
       HIGH 50%                             |            |            |
790 
--------------------------------------------------------------------------------
791 
 
792 
 
793 
All constraints were met.
794 
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
795 
   constraint does not cover any paths or that it has no requested value.
796 
Generating Pad Report.
797 
 
798 
All signals are completely routed.
799 
 
800 
Total REAL time to PAR completion: 1 mins 48 secs
801 
Total CPU time to PAR completion: 1 mins 36 secs
802 
 
803 
Peak Memory Usage:  246 MB
804 
 
805 
Placement: Completed - No errors found.
806 
Routing: Completed - No errors found.
807 
Timing: Completed - No errors found.
808 
 
809 
Number of error messages: 0
810 
Number of warning messages: 2
811 
Number of info messages: 0
812 
 
813 
Writing design to file system.ncd
814 
 
815 
 
816 
PAR done!
817 
 
818 
 
819 
 
820 
#----------------------------------------------#
821 
# Starting program post_par_trce
822 
# trce -e 3 -xml system.twx system.ncd system.pcf
823 
#----------------------------------------------#
824 
Release 7.1.02i - Trace H.42
825 
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
826 
 
827 
 
828 
Loading device for application Rf_Device from file '2vp30.nph' in environment
829 
c:/ISE.
830 
   "system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
831 
--------------------------------------------------------------------------------
832 
Release 7.1.02i Trace H.42
833 
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
834 
 
835 
trce -e 3 -xml system.twx system.ncd system.pcf
836 
 
837 
 
838 
Design file:              system.ncd
839 
Physical constraint file: system.pcf
840 
Device,speed:             xc2vp30,-7 (PRODUCTION 1.91 2005-07-22)
841 
Report level:             error report
842 
--------------------------------------------------------------------------------
843 
 
844 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
845 
   option. All paths that are not constrained will be reported in the
846 
   unconstrained paths section(s) of the report.
847 
 
848 
 
849 
Timing summary:
850 
---------------
851 
 
852 
Timing errors: 0  Score: 0
853 
 
854 
Constraints cover 475026 paths, 0 nets, and 12068 connections
855 
 
856 
Design statistics:
857 
   Minimum period:   9.935ns (Maximum frequency: 100.654MHz)
858 
 
859 
 
860 
Analysis completed Fri Jun 23 16:15:21 2006
861 
--------------------------------------------------------------------------------
862 
 
863 
Generating Report ...
864 
 
865 
Number of warnings: 0
866 
Number of info messages: 1
867 
Total time: 10 secs
868 
 
869 
 
870 
xflow done!
871 
cd implementation; bitgen -w -f bitgen.ut system
872 
Release 7.1.02i - Bitgen H.42
873 
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
874 
Loading device for application Rf_Device from file '2vp30.nph' in environment
875 
c:/ISE.
876 
   "system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
877 
Opened constraints file system.pcf.
878 
 
879 
Fri Jun 23 16:15:26 2006
880 
Running DRC.
881 
WARNING:PhysDesignRules:367 - The signal  is
882 
   incomplete. The signal does not drive any load pins in the design.
883 
DRC detected 0 errors and 1 warnings.
884 
Creating bit map...
885 
Saving bit stream in "system.bit".
886 
Creating bit mask...
887 
Saving mask bit stream in "system.msk".
888 
Bitstream generation is complete.
889 
Done.
890 
At Local date and time: Fri Jun 23 16:18:55 2006
891 
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make clean; exit;" Started...
892 
rm -f implementation/system.ngc
893 
rm -f implementation/system.bmm
894 
rm -f implementation/system.bit
895 
rm -f implementation/system.ncd
896 
rm -f implementation/system_bd.bmm
897 
rm -rf implementation synthesis xst hdl
898 
rm -rf xst.srp system.srp
899 
rm -rf microblaze_0/lib/
900 
rm -f decoder/executable.elf
901 
rm -rf simulation/behavioral
902 
rm -rf virtualplatform
903 
rm -f _impact.cmd
904 
Done.

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