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[/] [mb-jpeg/] [tags/] [STEP1_2/] [system.mhs] - Blame information for rev 66

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1 55 quickwayne 
# ##############################################################################
2 
# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1
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# Wed Nov 01 18:23:34 2006
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# Target Board:  Xilinx XUP Virtex-II Pro Development System Rev C
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# Family:        virtex2p
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# Device:        xc2vp30
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# Package:       ff896
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# Speed Grade:   -7
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# Processor: Microblaze
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# System clock frequency: 100.000000 MHz
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# Debug interface: On-Chip HW Debug Module
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# On Chip Memory :   8 KB
13 
# Total Off Chip Memory : 256 MB
14 56 quickwayne 
# - DDR_SDRAM_32Mx64 Single Rank = 256 MB
15 55 quickwayne 
# ##############################################################################
16 
 
17 
 
18 
 PARAMETER VERSION = 2.1.0
19 
 
20 
 
21 
 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT
22 
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT
23 
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT
24 56 quickwayne 
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = OUTPUT
25 
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = INOUT
26 55 quickwayne 
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT
27 
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT
28 
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT
29 
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT
30 56 quickwayne 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, VEC = [0:2], DIR = OUTPUT
31 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, VEC = [0:2], DIR = OUTPUT
32 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, VEC = [0:12], DIR = OUTPUT
33 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, VEC = [0:1], DIR = OUTPUT
34 55 quickwayne 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT
35 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT
36 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT
37 56 quickwayne 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, VEC = [0:7], DIR = OUTPUT
38 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, VEC = [0:7], DIR = INOUT
39 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, VEC = [0:63], DIR = INOUT
40 55 quickwayne 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT
41 
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT
42 
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
43 
 PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
44 
 PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK
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 PORT sys_rst_pin = sys_rst_s, DIR = INPUT
46 
 
47 
 
48 
BEGIN microblaze
49 
 PARAMETER INSTANCE = microblaze_0
50 
 PARAMETER HW_VER = 4.00.a
51 
 PARAMETER C_DEBUG_ENABLED = 1
52 
 PARAMETER C_NUMBER_OF_PC_BRK = 2
53 
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
54 
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
55 
 BUS_INTERFACE DLMB = dlmb
56 
 BUS_INTERFACE ILMB = ilmb
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 BUS_INTERFACE DOPB = mb_opb
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 BUS_INTERFACE IOPB = mb_opb
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 PORT CLK = sys_clk_s
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 PORT DBG_CAPTURE = DBG_CAPTURE_s
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 PORT DBG_CLK = DBG_CLK_s
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 PORT DBG_REG_EN = DBG_REG_EN_s
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 PORT DBG_TDI = DBG_TDI_s
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 PORT DBG_TDO = DBG_TDO_s
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 PORT DBG_UPDATE = DBG_UPDATE_s
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END
67 
 
68 
BEGIN opb_v20
69 
 PARAMETER INSTANCE = mb_opb
70 
 PARAMETER HW_VER = 1.10.c
71 
 PARAMETER C_EXT_RESET_HIGH = 0
72 
 PORT SYS_Rst = sys_rst_s
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 PORT OPB_Clk = sys_clk_s
74 
END
75 
 
76 
BEGIN opb_mdm
77 
 PARAMETER INSTANCE = debug_module
78 
 PARAMETER HW_VER = 2.00.a
79 
 PARAMETER C_MB_DBG_PORTS = 1
80 
 PARAMETER C_USE_UART = 1
81 
 PARAMETER C_UART_WIDTH = 8
82 
 PARAMETER C_BASEADDR = 0x41400000
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 PARAMETER C_HIGHADDR = 0x4140ffff
84 
 BUS_INTERFACE SOPB = mb_opb
85 
 PORT OPB_Clk = sys_clk_s
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 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
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 PORT DBG_CLK_0 = DBG_CLK_s
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 PORT DBG_REG_EN_0 = DBG_REG_EN_s
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 PORT DBG_TDI_0 = DBG_TDI_s
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 PORT DBG_TDO_0 = DBG_TDO_s
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 PORT DBG_UPDATE_0 = DBG_UPDATE_s
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END
93 
 
94 
BEGIN lmb_v10
95 
 PARAMETER INSTANCE = ilmb
96 
 PARAMETER HW_VER = 1.00.a
97 
 PARAMETER C_EXT_RESET_HIGH = 0
98 
 PORT SYS_Rst = sys_rst_s
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 PORT LMB_Clk = sys_clk_s
100 
END
101 
 
102 
BEGIN lmb_v10
103 
 PARAMETER INSTANCE = dlmb
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 PARAMETER HW_VER = 1.00.a
105 
 PARAMETER C_EXT_RESET_HIGH = 0
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 PORT SYS_Rst = sys_rst_s
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 PORT LMB_Clk = sys_clk_s
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END
109 
 
110 
BEGIN lmb_bram_if_cntlr
111 
 PARAMETER INSTANCE = dlmb_cntlr
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 PARAMETER HW_VER = 1.00.b
113 
 PARAMETER C_BASEADDR = 0x00000000
114 56 quickwayne 
 PARAMETER C_HIGHADDR = 0x0000ffff
115 55 quickwayne 
 BUS_INTERFACE SLMB = dlmb
116 
 BUS_INTERFACE BRAM_PORT = dlmb_port
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END
118 
 
119 
BEGIN lmb_bram_if_cntlr
120 
 PARAMETER INSTANCE = ilmb_cntlr
121 
 PARAMETER HW_VER = 1.00.b
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 PARAMETER C_BASEADDR = 0x00000000
123 56 quickwayne 
 PARAMETER C_HIGHADDR = 0x0000ffff
124 55 quickwayne 
 BUS_INTERFACE SLMB = ilmb
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 BUS_INTERFACE BRAM_PORT = ilmb_port
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END
127 
 
128 
BEGIN bram_block
129 
 PARAMETER INSTANCE = lmb_bram
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 PARAMETER HW_VER = 1.00.a
131 
 BUS_INTERFACE PORTA = ilmb_port
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 BUS_INTERFACE PORTB = dlmb_port
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END
134 
 
135 
BEGIN opb_uartlite
136 
 PARAMETER INSTANCE = RS232_Uart_1
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 PARAMETER HW_VER = 1.00.b
138 
 PARAMETER C_BAUDRATE = 9600
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 PARAMETER C_DATA_BITS = 8
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 PARAMETER C_ODD_PARITY = 0
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 PARAMETER C_USE_PARITY = 0
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 PARAMETER C_CLK_FREQ = 100000000
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 PARAMETER C_BASEADDR = 0x40600000
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 PARAMETER C_HIGHADDR = 0x4060ffff
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 BUS_INTERFACE SOPB = mb_opb
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 PORT OPB_Clk = sys_clk_s
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 PORT RX = fpga_0_RS232_Uart_1_RX
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 PORT TX = fpga_0_RS232_Uart_1_TX
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END
150 
 
151 
BEGIN opb_sysace
152 
 PARAMETER INSTANCE = SysACE_CompactFlash
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 PARAMETER HW_VER = 1.00.c
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 PARAMETER C_MEM_WIDTH = 16
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 PARAMETER C_BASEADDR = 0x41800000
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 PARAMETER C_HIGHADDR = 0x4180ffff
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 BUS_INTERFACE SOPB = mb_opb
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 PORT OPB_Clk = sys_clk_s
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 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
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 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
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 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
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 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
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 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
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 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
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 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
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END
167 
 
168 
BEGIN opb_ddr
169 
 PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
170 
 PARAMETER HW_VER = 2.00.b
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 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
172 
 PARAMETER C_NUM_BANKS_MEM = 1
173 
 PARAMETER C_NUM_CLK_PAIRS = 4
174 
 PARAMETER C_REG_DIMM = 0
175 
 PARAMETER C_DDR_TMRD = 20000
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 PARAMETER C_DDR_TWR = 20000
177 
 PARAMETER C_DDR_TRAS = 60000
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 PARAMETER C_DDR_TRC = 90000
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 PARAMETER C_DDR_TRFC = 100000
180 
 PARAMETER C_DDR_TRCD = 30000
181 
 PARAMETER C_DDR_TRRD = 20000
182 
 PARAMETER C_DDR_TRP = 30000
183 
 PARAMETER C_DDR_TREFC = 70300000
184 
 PARAMETER C_DDR_AWIDTH = 13
185 
 PARAMETER C_DDR_COL_AWIDTH = 10
186 
 PARAMETER C_DDR_BANK_AWIDTH = 2
187 
 PARAMETER C_DDR_DWIDTH = 64
188 
 PARAMETER C_MEM0_BASEADDR = 0x30000000
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 PARAMETER C_MEM0_HIGHADDR = 0x3fffffff
190 
 BUS_INTERFACE SOPB = mb_opb
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 PORT OPB_Clk = sys_clk_s
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 PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
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 PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
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 PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
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 PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
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 PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
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 PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
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 PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
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 PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
200 
 PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
201 
 PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
202 
 PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
203 
 PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0
204 
 PORT Device_Clk90_in = clk_90_s
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 PORT Device_Clk90_in_n = clk_90_n_s
206 
 PORT Device_Clk = sys_clk_s
207 
 PORT Device_Clk_n = sys_clk_n_s
208 
 PORT DDR_Clk90_in = ddr_clk_90_s
209 
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
210 
END
211 
 
212 
BEGIN util_vector_logic
213 
 PARAMETER INSTANCE = sysclk_inv
214 
 PARAMETER HW_VER = 1.00.a
215 
 PARAMETER C_SIZE = 1
216 
 PARAMETER C_OPERATION = not
217 
 PORT Op1 = sys_clk_s
218 
 PORT Res = sys_clk_n_s
219 
END
220 
 
221 
BEGIN util_vector_logic
222 
 PARAMETER INSTANCE = clk90_inv
223 
 PARAMETER HW_VER = 1.00.a
224 
 PARAMETER C_SIZE = 1
225 
 PARAMETER C_OPERATION = not
226 
 PORT Op1 = clk_90_s
227 
 PORT Res = clk_90_n_s
228 
END
229 
 
230 
BEGIN util_vector_logic
231 
 PARAMETER INSTANCE = ddr_clk90_inv
232 
 PARAMETER HW_VER = 1.00.a
233 
 PARAMETER C_SIZE = 1
234 
 PARAMETER C_OPERATION = not
235 
 PORT Op1 = ddr_clk_90_s
236 
 PORT Res = ddr_clk_90_n_s
237 
END
238 
 
239 
BEGIN dcm_module
240 
 PARAMETER INSTANCE = dcm_0
241 
 PARAMETER HW_VER = 1.00.a
242 
 PARAMETER C_CLK0_BUF = TRUE
243 
 PARAMETER C_CLK90_BUF = TRUE
244 
 PARAMETER C_CLKIN_PERIOD = 10.000000
245 
 PARAMETER C_CLK_FEEDBACK = 1X
246 
 PARAMETER C_EXT_RESET_HIGH = 1
247 
 PORT CLKIN = dcm_clk_s
248 
 PORT CLK0 = sys_clk_s
249 
 PORT CLK90 = clk_90_s
250 
 PORT CLKFB = sys_clk_s
251 
 PORT RST = net_gnd
252 
 PORT LOCKED = dcm_0_lock
253 
END
254 
 
255 
BEGIN dcm_module
256 
 PARAMETER INSTANCE = dcm_1
257 
 PARAMETER HW_VER = 1.00.a
258 
 PARAMETER C_CLK0_BUF = TRUE
259 
 PARAMETER C_CLK90_BUF = TRUE
260 
 PARAMETER C_CLKIN_PERIOD = 10.000000
261 
 PARAMETER C_CLK_FEEDBACK = 1X
262 
 PARAMETER C_PHASE_SHIFT = 60
263 
 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
264 
 PARAMETER C_EXT_RESET_HIGH = 0
265 
 PORT CLKIN = ddr_feedback_s
266 
 PORT CLK90 = ddr_clk_90_s
267 
 PORT CLK0 = dcm_1_FB
268 
 PORT CLKFB = dcm_1_FB
269 
 PORT RST = dcm_0_lock
270 
 PORT LOCKED = dcm_1_lock
271 
END
272 
 

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