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[/] [mb-jpeg/] [tags/] [STEP1_2/] [system.mhs] - Blame information for rev 55

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#
# ##############################################################################
#
# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1
#
# Wed Nov 01 18:23:34 2006
#
# Target Board:  Xilinx XUP Virtex-II Pro Development System Rev C
# Family:        virtex2p
# Device:        xc2vp30
# Package:       ff896
# Speed Grade:   -7
#
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :   8 KB
# Total Off Chip Memory : 256 MB
#   - DDR_SDRAM_32Mx64 Single Rank = 256 MB
#
# ##############################################################################
 
 
 PARAMETER VERSION = 2.1.0
 
 
 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = OUTPUT, VEC = [6:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = INOUT, VEC = [15:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, DIR = OUTPUT, VEC = [0:2]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, DIR = OUTPUT, VEC = [0:2]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, DIR = OUTPUT, VEC = [0:12]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, DIR = OUTPUT, VEC = [0:1]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, DIR = OUTPUT, VEC = [0:7]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, DIR = INOUT, VEC = [0:7]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, DIR = INOUT, VEC = [0:63]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
 PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
 PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK
 PORT sys_rst_pin = sys_rst_s, DIR = INPUT
 
 
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT CLK = sys_clk_s
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
END
 
BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END
 
BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END
 
BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END
 
BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT RX = fpga_0_RS232_Uart_1_RX
 PORT TX = fpga_0_RS232_Uart_1_TX
END
 
BEGIN opb_sysace
 PARAMETER INSTANCE = SysACE_CompactFlash
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_MEM_WIDTH = 16
 PARAMETER C_BASEADDR = 0x41800000
 PARAMETER C_HIGHADDR = 0x4180ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END
 
BEGIN opb_ddr
 PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_NUM_CLK_PAIRS = 4
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_DDR_TMRD = 20000
 PARAMETER C_DDR_TWR = 20000
 PARAMETER C_DDR_TRAS = 60000
 PARAMETER C_DDR_TRC = 90000
 PARAMETER C_DDR_TRFC = 100000
 PARAMETER C_DDR_TRCD = 30000
 PARAMETER C_DDR_TRRD = 20000
 PARAMETER C_DDR_TRP = 30000
 PARAMETER C_DDR_TREFC = 70300000
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 10
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_DDR_DWIDTH = 64
 PARAMETER C_MEM0_BASEADDR = 0x30000000
 PARAMETER C_MEM0_HIGHADDR = 0x3fffffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
 PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
 PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
 PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
 PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
 PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0
 PORT Device_Clk90_in = clk_90_s
 PORT Device_Clk90_in_n = clk_90_n_s
 PORT Device_Clk = sys_clk_s
 PORT Device_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END
 
BEGIN util_vector_logic
 PARAMETER INSTANCE = sysclk_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = sys_clk_s
 PORT Res = sys_clk_n_s
END
 
BEGIN util_vector_logic
 PARAMETER INSTANCE = clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = clk_90_s
 PORT Res = clk_90_n_s
END
 
BEGIN util_vector_logic
 PARAMETER INSTANCE = ddr_clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = ddr_clk_90_s
 PORT Res = ddr_clk_90_n_s
END
 
BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLK90 = clk_90_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END
 
BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_PHASE_SHIFT = 60
 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT CLKIN = ddr_feedback_s
 PORT CLK90 = ddr_clk_90_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
END
 

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Subversion Repositories mb-jpeg

[/] [mb-jpeg/] [tags/] [STEP1_2/] [system.mhs] - Blame information for rev 55

Line No.	Rev	Author	Line
1	55	quickwayne	`#`
2			`# ##############################################################################`
3			`#`
4			`# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1`
5			`#`
6			`# Wed Nov 01 18:23:34 2006`
7			`#`
8			`# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C`
9			`# Family: virtex2p`
10			`# Device: xc2vp30`
11			`# Package: ff896`
12			`# Speed Grade: -7`
13			`#`
14			`# Processor: Microblaze`
15			`# System clock frequency: 100.000000 MHz`
16			`# Debug interface: On-Chip HW Debug Module`
17			`# On Chip Memory : 8 KB`
18			`# Total Off Chip Memory : 256 MB`
19			`# - DDR_SDRAM_32Mx64 Single Rank = 256 MB`
20			`#`
21			`# ##############################################################################`
22
23
24			`PARAMETER VERSION = 2.1.0`
25
26
27			`PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT`
28			`PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT`
29			`PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT`
30			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = OUTPUT, VEC = [6:0]`
31			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = INOUT, VEC = [15:0]`
32			`PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT`
33			`PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT`
34			`PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT`
35			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT`
36			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, DIR = OUTPUT, VEC = [0:2]`
37			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, DIR = OUTPUT, VEC = [0:2]`
38			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, DIR = OUTPUT, VEC = [0:12]`
39			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, DIR = OUTPUT, VEC = [0:1]`
40			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT`
41			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT`
42			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT`
43			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, DIR = OUTPUT, VEC = [0:7]`
44			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, DIR = INOUT, VEC = [0:7]`
45			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, DIR = INOUT, VEC = [0:63]`
46			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT`
47			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT`
48			`PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT`
49			`PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT`
50			`PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK`
51			`PORT sys_rst_pin = sys_rst_s, DIR = INPUT`
52
53
54			`BEGIN microblaze`
55			`PARAMETER INSTANCE = microblaze_0`
56			`PARAMETER HW_VER = 4.00.a`
57			`PARAMETER C_DEBUG_ENABLED = 1`
58			`PARAMETER C_NUMBER_OF_PC_BRK = 2`
59			`PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1`
60			`PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1`
61			`BUS_INTERFACE DLMB = dlmb`
62			`BUS_INTERFACE ILMB = ilmb`
63			`BUS_INTERFACE DOPB = mb_opb`
64			`BUS_INTERFACE IOPB = mb_opb`
65			`PORT CLK = sys_clk_s`
66			`PORT DBG_CAPTURE = DBG_CAPTURE_s`
67			`PORT DBG_CLK = DBG_CLK_s`
68			`PORT DBG_REG_EN = DBG_REG_EN_s`
69			`PORT DBG_TDI = DBG_TDI_s`
70			`PORT DBG_TDO = DBG_TDO_s`
71			`PORT DBG_UPDATE = DBG_UPDATE_s`
72			`END`
73
74			`BEGIN opb_v20`
75			`PARAMETER INSTANCE = mb_opb`
76			`PARAMETER HW_VER = 1.10.c`
77			`PARAMETER C_EXT_RESET_HIGH = 0`
78			`PORT SYS_Rst = sys_rst_s`
79			`PORT OPB_Clk = sys_clk_s`
80			`END`
81
82			`BEGIN opb_mdm`
83			`PARAMETER INSTANCE = debug_module`
84			`PARAMETER HW_VER = 2.00.a`
85			`PARAMETER C_MB_DBG_PORTS = 1`
86			`PARAMETER C_USE_UART = 1`
87			`PARAMETER C_UART_WIDTH = 8`
88			`PARAMETER C_BASEADDR = 0x41400000`
89			`PARAMETER C_HIGHADDR = 0x4140ffff`
90			`BUS_INTERFACE SOPB = mb_opb`
91			`PORT OPB_Clk = sys_clk_s`
92			`PORT DBG_CAPTURE_0 = DBG_CAPTURE_s`
93			`PORT DBG_CLK_0 = DBG_CLK_s`
94			`PORT DBG_REG_EN_0 = DBG_REG_EN_s`
95			`PORT DBG_TDI_0 = DBG_TDI_s`
96			`PORT DBG_TDO_0 = DBG_TDO_s`
97			`PORT DBG_UPDATE_0 = DBG_UPDATE_s`
98			`END`
99
100			`BEGIN lmb_v10`
101			`PARAMETER INSTANCE = ilmb`
102			`PARAMETER HW_VER = 1.00.a`
103			`PARAMETER C_EXT_RESET_HIGH = 0`
104			`PORT SYS_Rst = sys_rst_s`
105			`PORT LMB_Clk = sys_clk_s`
106			`END`
107
108			`BEGIN lmb_v10`
109			`PARAMETER INSTANCE = dlmb`
110			`PARAMETER HW_VER = 1.00.a`
111			`PARAMETER C_EXT_RESET_HIGH = 0`
112			`PORT SYS_Rst = sys_rst_s`
113			`PORT LMB_Clk = sys_clk_s`
114			`END`
115
116			`BEGIN lmb_bram_if_cntlr`
117			`PARAMETER INSTANCE = dlmb_cntlr`
118			`PARAMETER HW_VER = 1.00.b`
119			`PARAMETER C_BASEADDR = 0x00000000`
120			`PARAMETER C_HIGHADDR = 0x00001fff`
121			`BUS_INTERFACE SLMB = dlmb`
122			`BUS_INTERFACE BRAM_PORT = dlmb_port`
123			`END`
124
125			`BEGIN lmb_bram_if_cntlr`
126			`PARAMETER INSTANCE = ilmb_cntlr`
127			`PARAMETER HW_VER = 1.00.b`
128			`PARAMETER C_BASEADDR = 0x00000000`
129			`PARAMETER C_HIGHADDR = 0x00001fff`
130			`BUS_INTERFACE SLMB = ilmb`
131			`BUS_INTERFACE BRAM_PORT = ilmb_port`
132			`END`
133
134			`BEGIN bram_block`
135			`PARAMETER INSTANCE = lmb_bram`
136			`PARAMETER HW_VER = 1.00.a`
137			`BUS_INTERFACE PORTA = ilmb_port`
138			`BUS_INTERFACE PORTB = dlmb_port`
139			`END`
140
141			`BEGIN opb_uartlite`
142			`PARAMETER INSTANCE = RS232_Uart_1`
143			`PARAMETER HW_VER = 1.00.b`
144			`PARAMETER C_BAUDRATE = 9600`
145			`PARAMETER C_DATA_BITS = 8`
146			`PARAMETER C_ODD_PARITY = 0`
147			`PARAMETER C_USE_PARITY = 0`
148			`PARAMETER C_CLK_FREQ = 100000000`
149			`PARAMETER C_BASEADDR = 0x40600000`
150			`PARAMETER C_HIGHADDR = 0x4060ffff`
151			`BUS_INTERFACE SOPB = mb_opb`
152			`PORT OPB_Clk = sys_clk_s`
153			`PORT RX = fpga_0_RS232_Uart_1_RX`
154			`PORT TX = fpga_0_RS232_Uart_1_TX`
155			`END`
156
157			`BEGIN opb_sysace`
158			`PARAMETER INSTANCE = SysACE_CompactFlash`
159			`PARAMETER HW_VER = 1.00.c`
160			`PARAMETER C_MEM_WIDTH = 16`
161			`PARAMETER C_BASEADDR = 0x41800000`
162			`PARAMETER C_HIGHADDR = 0x4180ffff`
163			`BUS_INTERFACE SOPB = mb_opb`
164			`PORT OPB_Clk = sys_clk_s`
165			`PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK`
166			`PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA`
167			`PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD`
168			`PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN`
169			`PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN`
170			`PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN`
171			`PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ`
172			`END`
173
174			`BEGIN opb_ddr`
175			`PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5`
176			`PARAMETER HW_VER = 2.00.b`
177			`PARAMETER C_OPB_CLK_PERIOD_PS = 10000`
178			`PARAMETER C_NUM_BANKS_MEM = 1`
179			`PARAMETER C_NUM_CLK_PAIRS = 4`
180			`PARAMETER C_REG_DIMM = 0`
181			`PARAMETER C_DDR_TMRD = 20000`
182			`PARAMETER C_DDR_TWR = 20000`
183			`PARAMETER C_DDR_TRAS = 60000`
184			`PARAMETER C_DDR_TRC = 90000`
185			`PARAMETER C_DDR_TRFC = 100000`
186			`PARAMETER C_DDR_TRCD = 30000`
187			`PARAMETER C_DDR_TRRD = 20000`
188			`PARAMETER C_DDR_TRP = 30000`
189			`PARAMETER C_DDR_TREFC = 70300000`
190			`PARAMETER C_DDR_AWIDTH = 13`
191			`PARAMETER C_DDR_COL_AWIDTH = 10`
192			`PARAMETER C_DDR_BANK_AWIDTH = 2`
193			`PARAMETER C_DDR_DWIDTH = 64`
194			`PARAMETER C_MEM0_BASEADDR = 0x30000000`
195			`PARAMETER C_MEM0_HIGHADDR = 0x3fffffff`
196			`BUS_INTERFACE SOPB = mb_opb`
197			`PORT OPB_Clk = sys_clk_s`
198			`PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr`
199			`PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr`
200			`PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn`
201			`PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE`
202			`PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn`
203			`PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn`
204			`PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn`
205			`PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM`
206			`PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS`
207			`PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ`
208			`PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s`
209			`PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0`
210			`PORT Device_Clk90_in = clk_90_s`
211			`PORT Device_Clk90_in_n = clk_90_n_s`
212			`PORT Device_Clk = sys_clk_s`
213			`PORT Device_Clk_n = sys_clk_n_s`
214			`PORT DDR_Clk90_in = ddr_clk_90_s`
215			`PORT DDR_Clk90_in_n = ddr_clk_90_n_s`
216			`END`
217
218			`BEGIN util_vector_logic`
219			`PARAMETER INSTANCE = sysclk_inv`
220			`PARAMETER HW_VER = 1.00.a`
221			`PARAMETER C_SIZE = 1`
222			`PARAMETER C_OPERATION = not`
223			`PORT Op1 = sys_clk_s`
224			`PORT Res = sys_clk_n_s`
225			`END`
226
227			`BEGIN util_vector_logic`
228			`PARAMETER INSTANCE = clk90_inv`
229			`PARAMETER HW_VER = 1.00.a`
230			`PARAMETER C_SIZE = 1`
231			`PARAMETER C_OPERATION = not`
232			`PORT Op1 = clk_90_s`
233			`PORT Res = clk_90_n_s`
234			`END`
235
236			`BEGIN util_vector_logic`
237			`PARAMETER INSTANCE = ddr_clk90_inv`
238			`PARAMETER HW_VER = 1.00.a`
239			`PARAMETER C_SIZE = 1`
240			`PARAMETER C_OPERATION = not`
241			`PORT Op1 = ddr_clk_90_s`
242			`PORT Res = ddr_clk_90_n_s`
243			`END`
244
245			`BEGIN dcm_module`
246			`PARAMETER INSTANCE = dcm_0`
247			`PARAMETER HW_VER = 1.00.a`
248			`PARAMETER C_CLK0_BUF = TRUE`
249			`PARAMETER C_CLK90_BUF = TRUE`
250			`PARAMETER C_CLKIN_PERIOD = 10.000000`
251			`PARAMETER C_CLK_FEEDBACK = 1X`
252			`PARAMETER C_EXT_RESET_HIGH = 1`
253			`PORT CLKIN = dcm_clk_s`
254			`PORT CLK0 = sys_clk_s`
255			`PORT CLK90 = clk_90_s`
256			`PORT CLKFB = sys_clk_s`
257			`PORT RST = net_gnd`
258			`PORT LOCKED = dcm_0_lock`
259			`END`
260
261			`BEGIN dcm_module`
262			`PARAMETER INSTANCE = dcm_1`
263			`PARAMETER HW_VER = 1.00.a`
264			`PARAMETER C_CLK0_BUF = TRUE`
265			`PARAMETER C_CLK90_BUF = TRUE`
266			`PARAMETER C_CLKIN_PERIOD = 10.000000`
267			`PARAMETER C_CLK_FEEDBACK = 1X`
268			`PARAMETER C_PHASE_SHIFT = 60`
269			`PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED`
270			`PARAMETER C_EXT_RESET_HIGH = 0`
271			`PORT CLKIN = ddr_feedback_s`
272			`PORT CLK90 = ddr_clk_90_s`
273			`PORT CLK0 = dcm_1_FB`
274			`PORT CLKFB = dcm_1_FB`
275			`PORT RST = dcm_0_lock`
276			`PORT LOCKED = dcm_1_lock`
277			`END`
278