1 |
5 |
quickwayne |
############################################################################
|
2 |
|
|
## This system.ucf file is generated by Base System Builder based on the
|
3 |
|
|
## settings in the selected Xilinx Board Definition file. Please add other
|
4 |
|
|
## user constraints to this file based on customer design specifications.
|
5 |
|
|
############################################################################
|
6 |
|
|
|
7 |
|
|
Net sys_clk_pin LOC=AJ15;
|
8 |
|
|
Net sys_clk_pin IOSTANDARD = LVCMOS25;
|
9 |
|
|
Net sys_rst_pin LOC=AH5;
|
10 |
|
|
Net sys_rst_pin IOSTANDARD = LVTTL;
|
11 |
|
|
## System level constraints
|
12 |
|
|
Net sys_clk_pin TNM_NET = sys_clk_pin;
|
13 |
|
|
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
|
14 |
|
|
Net sys_rst_pin TIG;
|
15 |
|
|
|
16 |
|
|
## FPGA pin constraints
|
17 |
|
|
Net fpga_0_RS232_Uart_1_RX_pin LOC=AJ8;
|
18 |
|
|
Net fpga_0_RS232_Uart_1_RX_pin IOSTANDARD = LVCMOS25;
|
19 |
|
|
Net fpga_0_RS232_Uart_1_TX_pin LOC=AE7;
|
20 |
|
|
Net fpga_0_RS232_Uart_1_TX_pin IOSTANDARD = LVCMOS25;
|
21 |
|
|
Net fpga_0_RS232_Uart_1_TX_pin SLEW = SLOW;
|
22 |
|
|
Net fpga_0_RS232_Uart_1_TX_pin DRIVE = 12;
|
23 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH15;
|
24 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps;
|
25 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS25;
|
26 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=AF21;
|
27 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> IOSTANDARD = LVCMOS25;
|
28 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> SLEW = SLOW;
|
29 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> DRIVE = 8;
|
30 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=AG21;
|
31 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS25;
|
32 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> SLEW = SLOW;
|
33 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> DRIVE = 8;
|
34 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AC19;
|
35 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS25;
|
36 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> SLEW = SLOW;
|
37 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> DRIVE = 8;
|
38 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AD19;
|
39 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS25;
|
40 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> SLEW = SLOW;
|
41 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> DRIVE = 8;
|
42 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=AE22;
|
43 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS25;
|
44 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> SLEW = SLOW;
|
45 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> DRIVE = 8;
|
46 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AE21;
|
47 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS25;
|
48 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> SLEW = SLOW;
|
49 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> DRIVE = 8;
|
50 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=AH22;
|
51 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS25;
|
52 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> SLEW = SLOW;
|
53 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> DRIVE = 8;
|
54 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AE15;
|
55 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS25;
|
56 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> SLEW = SLOW;
|
57 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> DRIVE = 8;
|
58 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AD15;
|
59 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS25;
|
60 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> SLEW = SLOW;
|
61 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> DRIVE = 8;
|
62 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AG14;
|
63 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS25;
|
64 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> SLEW = SLOW;
|
65 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> DRIVE = 8;
|
66 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AF14;
|
67 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS25;
|
68 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> SLEW = SLOW;
|
69 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> DRIVE = 8;
|
70 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AE14;
|
71 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS25;
|
72 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> SLEW = SLOW;
|
73 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> DRIVE = 8;
|
74 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AD14;
|
75 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS25;
|
76 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> SLEW = SLOW;
|
77 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> DRIVE = 8;
|
78 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AC15;
|
79 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS25;
|
80 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> SLEW = SLOW;
|
81 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> DRIVE = 8;
|
82 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AB15;
|
83 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS25;
|
84 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> SLEW = SLOW;
|
85 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> DRIVE = 8;
|
86 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AJ9;
|
87 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS25;
|
88 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> SLEW = SLOW;
|
89 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> DRIVE = 8;
|
90 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AH9;
|
91 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS25;
|
92 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> SLEW = SLOW;
|
93 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> DRIVE = 8;
|
94 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AE10;
|
95 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS25;
|
96 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> SLEW = SLOW;
|
97 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> DRIVE = 8;
|
98 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AE9;
|
99 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS25;
|
100 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> SLEW = SLOW;
|
101 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> DRIVE = 8;
|
102 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AD12;
|
103 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS25;
|
104 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> SLEW = SLOW;
|
105 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> DRIVE = 8;
|
106 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AC12;
|
107 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS25;
|
108 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> SLEW = SLOW;
|
109 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> DRIVE = 8;
|
110 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AG10;
|
111 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS25;
|
112 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> SLEW = SLOW;
|
113 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> DRIVE = 8;
|
114 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AF10;
|
115 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS25;
|
116 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> SLEW = SLOW;
|
117 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> DRIVE = 8;
|
118 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AB16;
|
119 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS25;
|
120 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin SLEW = SLOW;
|
121 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin DRIVE = 8;
|
122 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AD17;
|
123 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS25;
|
124 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin SLEW = SLOW;
|
125 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin DRIVE = 8;
|
126 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=AC16;
|
127 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS25;
|
128 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin SLEW = SLOW;
|
129 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin DRIVE = 8;
|
130 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AD16;
|
131 |
|
|
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS25;
|
132 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=AC4;
|
133 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVTTL;
|
134 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;
|
135 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 12;
|
136 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=AC3;
|
137 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVTTL;
|
138 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;
|
139 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 12;
|
140 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=AA6;
|
141 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVTTL;
|
142 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;
|
143 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 12;
|
144 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=AA5;
|
145 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVTTL;
|
146 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;
|
147 |
|
|
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 12;
|
148 |
|
|
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<0> LOC=AC11;
|
149 |
|
|
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
|
150 |
|
|
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<1> LOC=AD11;
|
151 |
|
|
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
|
152 |
|
|
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<2> LOC=AF8;
|
153 |
|
|
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
|
154 |
|
|
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<3> LOC=AF9;
|
155 |
|
|
Net fpga_0_DIPSWs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
|
156 |
|
|
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<0> LOC=AG5;
|
157 |
|
|
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<0> IOSTANDARD = LVTTL;
|
158 |
|
|
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<1> LOC=AH4;
|
159 |
|
|
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<1> IOSTANDARD = LVTTL;
|
160 |
|
|
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<2> LOC=AG3;
|
161 |
|
|
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<2> IOSTANDARD = LVTTL;
|
162 |
|
|
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<3> LOC=AH1;
|
163 |
|
|
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<3> IOSTANDARD = LVTTL;
|
164 |
|
|
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<4> LOC=AH2;
|
165 |
|
|
Net fpga_0_PushButtons_5Bit_GPIO_IO_pin<4> IOSTANDARD = LVTTL;
|