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URL https://opencores.org/ocsvn/mb-jpeg/mb-jpeg/trunk

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[/] [mb-jpeg/] [tags/] [STEP2_2b/] [mb-bmp2jpg_linker_script] - Blame information for rev 61

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Line No. Rev Author Line
1 56 quickwayne 
/*******************************************************************/
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/*                                                                 */
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/* This file is automatically generated by linker script generator.*/
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/*                                                                 */
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/* Version: Xilinx EDK 7.1.2EDK_H.12.5.1                                  */
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/*                                                                 */
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/* Copyright (c) 2004 Xilinx, Inc.  All rights reserved.           */
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/*                                                                 */
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/* Description : MicroBlaze Linker Script                         */
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/*                                                                 */
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/*******************************************************************/
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_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
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_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
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/* Define Memories in the system */
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MEMORY
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{
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   DDR_256MB_32MX64_rank1_row13_col10_cl2_5_C_MEM0_BASEADDR : ORIGIN = 0x70000000, LENGTH = 0x0FFFFFFF
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   ilmb_cntlr_dlmb_cntlr : ORIGIN = 0x00000000, LENGTH = 0x0000FFFF
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}
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/* Specify the default entry point to the program */
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ENTRY(_start)
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/* Define the sections, and where they are mapped in memory */
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SECTIONS
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{
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.text : {
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   __text_start = .;
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   *(.text)
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   *(.text.*)
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   *(.gnu.linkonce.t*)
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   __text_end = .;
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} > ilmb_cntlr_dlmb_cntlr
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.rodata : {
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   __rodata_start = .;
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   *(.rodata)
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   *(.rodata.*)
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   *(.gnu.linkonce.r*)
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   __rodata_end = .;
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} > ilmb_cntlr_dlmb_cntlr
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.sdata2 : {
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   . = ALIGN(8);
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   __sdata2_start = .;
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   *(.sdata2)
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   . = ALIGN(8);
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   __sdata2_end = .;
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} > ilmb_cntlr_dlmb_cntlr
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.sbss2 : {
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   __sbss2_start = .;
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   *(.sbss2)
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   __sbss2_end = .;
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} > ilmb_cntlr_dlmb_cntlr
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.data : {
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   . = ALIGN(4);
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   __data_start = .;
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   *(.data)
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   *(.data.*)
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   *(.gnu.linkonce.d*)
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   __data_end = .;
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} > ilmb_cntlr_dlmb_cntlr
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.sdata : {
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   . = ALIGN(8);
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   __sdata_start = .;
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   *(.sdata)
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   __sdata_end = .;
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} > ilmb_cntlr_dlmb_cntlr
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.sbss : {
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   . = ALIGN(4);
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   __sbss_start = .;
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   *(.sbss)
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   . = ALIGN(8);
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   __sbss_end = .;
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} > ilmb_cntlr_dlmb_cntlr
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.bss : {
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   . = ALIGN(4);
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   __bss_start = .;
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   *(.bss)
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   *(COMMON)
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   . = ALIGN(4);
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   __bss_end = .;
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} > ilmb_cntlr_dlmb_cntlr
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.eh_frame : {
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   __eh_frame_start = .;
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   *(.eh_frame)
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   __eh_frame_end = .;
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} > ilmb_cntlr_dlmb_cntlr
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PROVIDE (_SDA_BASE_ = __sdata_start + (__sbss_end - __sdata_start / 2 ));
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PROVIDE (_SDA2_BASE_ = __sdata2_start + (__sbss2_end - __sdata2_start / 2 ));
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/* Generate Stack and Heap definitions */
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bss_stack : {
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   . = ALIGN(8);
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   _heap = .;
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   _heap_start = _heap;
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   . += _HEAP_SIZE;
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   . += _STACK_SIZE;
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   . = ALIGN(8);
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   _stack = .;
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   __stack = _stack;
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} > ilmb_cntlr_dlmb_cntlr
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}
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