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[/] [mb-jpeg/] [tags/] [STEP2_2b/] [system.mhs] - Blame information for rev 61

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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1
# Fri Jun 23 16:02:16 2006
# Target Board:  Xilinx XUP Virtex-II Pro Development System Rev C
# Family:        virtex2p
# Device:        xc2vp30
# Package:       ff896
# Speed Grade:   -7
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :  64 KB
# ##############################################################################
 
 
 PARAMETER VERSION = 2.1.0
 
 
 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = IO
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, VEC = [0:3], DIR = IO
 PORT fpga_0_DIPSWs_4Bit_GPIO_IO_pin = fpga_0_DIPSWs_4Bit_GPIO_IO, VEC = [0:3], DIR = IO
 PORT fpga_0_PushButtons_5Bit_GPIO_IO_pin = fpga_0_PushButtons_5Bit_GPIO_IO, VEC = [0:4], DIR = IO
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = DCMCLK
 PORT sys_rst_pin = sys_rst_s, DIR = I
 
 
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0
 PARAMETER C_FSL_LINKS = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 BUS_INTERFACE MFSL0 = microblaze_0_to_fsl_dct_0
 BUS_INTERFACE SFSL0 = fsl_dct_0_to_microblaze_0
 PORT CLK = sys_clk_s
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
END
 
BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END
 
BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00010000
 PARAMETER C_HIGHADDR = 0x00017FFF
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007FFF
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END
 
BEGIN bram_block
 PARAMETER INSTANCE = ilmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
END
 
BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT RX = fpga_0_RS232_Uart_1_RX
 PORT TX = fpga_0_RS232_Uart_1_TX
END
 
BEGIN opb_sysace
 PARAMETER INSTANCE = SysACE_CompactFlash
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_MEM_WIDTH = 16
 PARAMETER C_BASEADDR = 0x41800000
 PARAMETER C_HIGHADDR = 0x4180ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END
 
BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
END
 
BEGIN opb_gpio
 PARAMETER INSTANCE = DIPSWs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40040000
 PARAMETER C_HIGHADDR = 0x4004ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_DIPSWs_4Bit_GPIO_IO
END
 
BEGIN opb_gpio
 PARAMETER INSTANCE = PushButtons_5Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_PushButtons_5Bit_GPIO_IO
END
 
BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END
 
BEGIN bram_block
 PARAMETER INSTANCE = data_bram_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MEMSIZE = 16384
 BUS_INTERFACE PORTA = data_bram_0_port
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = data_bram_if_cntlr_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x70000000
 PARAMETER C_HIGHADDR = 0x7000ffff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = data_bram_0_port
END
 
BEGIN bram_block
 PARAMETER INSTANCE = dlmb_bram
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MEMSIZE = 16384
 BUS_INTERFACE PORTA = dlmb_port
END
 
BEGIN fsl_v20
 PARAMETER INSTANCE = microblaze_0_to_fsl_dct_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END
 
BEGIN fsl_dct
 PARAMETER INSTANCE = fsl_dct_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE SFSL = microblaze_0_to_fsl_dct_0
 BUS_INTERFACE MFSL = fsl_dct_0_to_microblaze_0
 PORT FSL_Clk = sys_clk_s
END
 
BEGIN fsl_v20
 PARAMETER INSTANCE = fsl_dct_0_to_microblaze_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END
 

Line No.	Rev	Author	Line
1	4	quickwayne	`# ##############################################################################`
2			`# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1`
3			`# Fri Jun 23 16:02:16 2006`
4			`# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C`
5			`# Family: virtex2p`
6			`# Device: xc2vp30`
7			`# Package: ff896`
8			`# Speed Grade: -7`
9			`# Processor: Microblaze`
10			`# System clock frequency: 100.000000 MHz`
11			`# Debug interface: On-Chip HW Debug Module`
12			`# On Chip Memory : 64 KB`
13			`# ##############################################################################`
14
15
16			`PARAMETER VERSION = 2.1.0`
17
18
19	5	quickwayne	`PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I`
20			`PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O`
21			`PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I`
22			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = O`
23			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = IO`
24			`PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O`
25			`PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O`
26			`PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O`
27			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I`
28			`PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, VEC = [0:3], DIR = IO`
29			`PORT fpga_0_DIPSWs_4Bit_GPIO_IO_pin = fpga_0_DIPSWs_4Bit_GPIO_IO, VEC = [0:3], DIR = IO`
30			`PORT fpga_0_PushButtons_5Bit_GPIO_IO_pin = fpga_0_PushButtons_5Bit_GPIO_IO, VEC = [0:4], DIR = IO`
31			`PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = DCMCLK`
32			`PORT sys_rst_pin = sys_rst_s, DIR = I`
33	4	quickwayne
34
35			`BEGIN microblaze`
36			`PARAMETER INSTANCE = microblaze_0`
37			`PARAMETER HW_VER = 4.00.a`
38			`PARAMETER C_DEBUG_ENABLED = 1`
39	38	quickwayne	`PARAMETER C_NUMBER_OF_PC_BRK = 2`
40			`PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0`
41			`PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0`
42			`PARAMETER C_FSL_LINKS = 1`
43	4	quickwayne	`BUS_INTERFACE DLMB = dlmb`
44			`BUS_INTERFACE ILMB = ilmb`
45			`BUS_INTERFACE DOPB = mb_opb`
46			`BUS_INTERFACE IOPB = mb_opb`
47	38	quickwayne	`BUS_INTERFACE MFSL0 = microblaze_0_to_fsl_dct_0`
48			`BUS_INTERFACE SFSL0 = fsl_dct_0_to_microblaze_0`
49	4	quickwayne	`PORT CLK = sys_clk_s`
50			`PORT DBG_CAPTURE = DBG_CAPTURE_s`
51			`PORT DBG_CLK = DBG_CLK_s`
52			`PORT DBG_REG_EN = DBG_REG_EN_s`
53			`PORT DBG_TDI = DBG_TDI_s`
54			`PORT DBG_TDO = DBG_TDO_s`
55			`PORT DBG_UPDATE = DBG_UPDATE_s`
56			`END`
57
58			`BEGIN opb_v20`
59			`PARAMETER INSTANCE = mb_opb`
60			`PARAMETER HW_VER = 1.10.c`
61			`PARAMETER C_EXT_RESET_HIGH = 0`
62			`PORT SYS_Rst = sys_rst_s`
63			`PORT OPB_Clk = sys_clk_s`
64			`END`
65
66			`BEGIN opb_mdm`
67			`PARAMETER INSTANCE = debug_module`
68			`PARAMETER HW_VER = 2.00.a`
69			`PARAMETER C_MB_DBG_PORTS = 1`
70			`PARAMETER C_USE_UART = 1`
71			`PARAMETER C_UART_WIDTH = 8`
72			`PARAMETER C_BASEADDR = 0x41400000`
73			`PARAMETER C_HIGHADDR = 0x4140ffff`
74			`BUS_INTERFACE SOPB = mb_opb`
75			`PORT OPB_Clk = sys_clk_s`
76			`PORT DBG_CAPTURE_0 = DBG_CAPTURE_s`
77			`PORT DBG_CLK_0 = DBG_CLK_s`
78			`PORT DBG_REG_EN_0 = DBG_REG_EN_s`
79			`PORT DBG_TDI_0 = DBG_TDI_s`
80			`PORT DBG_TDO_0 = DBG_TDO_s`
81			`PORT DBG_UPDATE_0 = DBG_UPDATE_s`
82			`END`
83
84			`BEGIN lmb_v10`
85			`PARAMETER INSTANCE = ilmb`
86			`PARAMETER HW_VER = 1.00.a`
87			`PARAMETER C_EXT_RESET_HIGH = 0`
88			`PORT SYS_Rst = sys_rst_s`
89			`PORT LMB_Clk = sys_clk_s`
90			`END`
91
92			`BEGIN lmb_v10`
93			`PARAMETER INSTANCE = dlmb`
94			`PARAMETER HW_VER = 1.00.a`
95			`PARAMETER C_EXT_RESET_HIGH = 0`
96			`PORT SYS_Rst = sys_rst_s`
97			`PORT LMB_Clk = sys_clk_s`
98			`END`
99
100			`BEGIN lmb_bram_if_cntlr`
101			`PARAMETER INSTANCE = dlmb_cntlr`
102			`PARAMETER HW_VER = 1.00.b`
103	21	quickwayne	`PARAMETER C_BASEADDR = 0x00010000`
104	42	quickwayne	`PARAMETER C_HIGHADDR = 0x00017FFF`
105	4	quickwayne	`BUS_INTERFACE SLMB = dlmb`
106			`BUS_INTERFACE BRAM_PORT = dlmb_port`
107			`END`
108
109			`BEGIN lmb_bram_if_cntlr`
110			`PARAMETER INSTANCE = ilmb_cntlr`
111			`PARAMETER HW_VER = 1.00.b`
112			`PARAMETER C_BASEADDR = 0x00000000`
113	42	quickwayne	`PARAMETER C_HIGHADDR = 0x00007FFF`
114	4	quickwayne	`BUS_INTERFACE SLMB = ilmb`
115			`BUS_INTERFACE BRAM_PORT = ilmb_port`
116			`END`
117
118			`BEGIN bram_block`
119	21	quickwayne	`PARAMETER INSTANCE = ilmb_bram`
120	4	quickwayne	`PARAMETER HW_VER = 1.00.a`
121			`BUS_INTERFACE PORTA = ilmb_port`
122			`END`
123
124			`BEGIN opb_uartlite`
125			`PARAMETER INSTANCE = RS232_Uart_1`
126			`PARAMETER HW_VER = 1.00.b`
127			`PARAMETER C_BAUDRATE = 9600`
128			`PARAMETER C_DATA_BITS = 8`
129			`PARAMETER C_ODD_PARITY = 0`
130			`PARAMETER C_USE_PARITY = 0`
131			`PARAMETER C_CLK_FREQ = 100000000`
132			`PARAMETER C_BASEADDR = 0x40600000`
133			`PARAMETER C_HIGHADDR = 0x4060ffff`
134			`BUS_INTERFACE SOPB = mb_opb`
135			`PORT OPB_Clk = sys_clk_s`
136			`PORT RX = fpga_0_RS232_Uart_1_RX`
137			`PORT TX = fpga_0_RS232_Uart_1_TX`
138			`END`
139
140			`BEGIN opb_sysace`
141			`PARAMETER INSTANCE = SysACE_CompactFlash`
142			`PARAMETER HW_VER = 1.00.c`
143			`PARAMETER C_MEM_WIDTH = 16`
144			`PARAMETER C_BASEADDR = 0x41800000`
145			`PARAMETER C_HIGHADDR = 0x4180ffff`
146			`BUS_INTERFACE SOPB = mb_opb`
147			`PORT OPB_Clk = sys_clk_s`
148			`PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK`
149			`PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA`
150			`PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD`
151			`PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN`
152			`PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN`
153			`PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN`
154			`PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ`
155			`END`
156
157			`BEGIN opb_gpio`
158			`PARAMETER INSTANCE = LEDs_4Bit`
159			`PARAMETER HW_VER = 3.01.b`
160			`PARAMETER C_GPIO_WIDTH = 4`
161			`PARAMETER C_IS_DUAL = 0`
162			`PARAMETER C_IS_BIDIR = 0`
163			`PARAMETER C_ALL_INPUTS = 0`
164			`PARAMETER C_BASEADDR = 0x40020000`
165			`PARAMETER C_HIGHADDR = 0x4002ffff`
166			`BUS_INTERFACE SOPB = mb_opb`
167			`PORT OPB_Clk = sys_clk_s`
168			`PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO`
169			`END`
170
171			`BEGIN opb_gpio`
172			`PARAMETER INSTANCE = DIPSWs_4Bit`
173			`PARAMETER HW_VER = 3.01.b`
174			`PARAMETER C_GPIO_WIDTH = 4`
175			`PARAMETER C_IS_DUAL = 0`
176			`PARAMETER C_IS_BIDIR = 1`
177			`PARAMETER C_ALL_INPUTS = 1`
178			`PARAMETER C_BASEADDR = 0x40040000`
179			`PARAMETER C_HIGHADDR = 0x4004ffff`
180			`BUS_INTERFACE SOPB = mb_opb`
181			`PORT OPB_Clk = sys_clk_s`
182			`PORT GPIO_IO = fpga_0_DIPSWs_4Bit_GPIO_IO`
183			`END`
184
185			`BEGIN opb_gpio`
186			`PARAMETER INSTANCE = PushButtons_5Bit`
187			`PARAMETER HW_VER = 3.01.b`
188			`PARAMETER C_GPIO_WIDTH = 5`
189			`PARAMETER C_IS_DUAL = 0`
190			`PARAMETER C_IS_BIDIR = 1`
191			`PARAMETER C_ALL_INPUTS = 1`
192			`PARAMETER C_BASEADDR = 0x40000000`
193			`PARAMETER C_HIGHADDR = 0x4000ffff`
194			`BUS_INTERFACE SOPB = mb_opb`
195			`PORT OPB_Clk = sys_clk_s`
196			`PORT GPIO_IO = fpga_0_PushButtons_5Bit_GPIO_IO`
197			`END`
198
199			`BEGIN dcm_module`
200			`PARAMETER INSTANCE = dcm_0`
201			`PARAMETER HW_VER = 1.00.a`
202			`PARAMETER C_CLK0_BUF = TRUE`
203			`PARAMETER C_CLKIN_PERIOD = 10.000000`
204			`PARAMETER C_CLK_FEEDBACK = 1X`
205			`PARAMETER C_EXT_RESET_HIGH = 1`
206			`PORT CLKIN = dcm_clk_s`
207			`PORT CLK0 = sys_clk_s`
208			`PORT CLKFB = sys_clk_s`
209			`PORT RST = net_gnd`
210			`PORT LOCKED = dcm_0_lock`
211			`END`
212
213			`BEGIN bram_block`
214			`PARAMETER INSTANCE = data_bram_0`
215			`PARAMETER HW_VER = 1.00.a`
216			`PARAMETER C_MEMSIZE = 16384`
217			`BUS_INTERFACE PORTA = data_bram_0_port`
218			`END`
219
220			`BEGIN lmb_bram_if_cntlr`
221			`PARAMETER INSTANCE = data_bram_if_cntlr_0`
222			`PARAMETER HW_VER = 1.00.b`
223			`PARAMETER C_BASEADDR = 0x70000000`
224			`PARAMETER C_HIGHADDR = 0x7000ffff`
225			`BUS_INTERFACE SLMB = dlmb`
226			`BUS_INTERFACE BRAM_PORT = data_bram_0_port`
227			`END`
228
229			`BEGIN bram_block`
230	21	quickwayne	`PARAMETER INSTANCE = dlmb_bram`
231	4	quickwayne	`PARAMETER HW_VER = 1.00.a`
232			`PARAMETER C_MEMSIZE = 16384`
233	21	quickwayne	`BUS_INTERFACE PORTA = dlmb_port`
234	4	quickwayne	`END`
235
236	38	quickwayne	`BEGIN fsl_v20`
237			`PARAMETER INSTANCE = microblaze_0_to_fsl_dct_0`
238			`PARAMETER HW_VER = 2.00.a`
239			`PARAMETER C_EXT_RESET_HIGH = 0`
240			`PORT FSL_Clk = sys_clk_s`
241			`PORT SYS_Rst = sys_rst_s`
242			`END`
243
244			`BEGIN fsl_dct`
245			`PARAMETER INSTANCE = fsl_dct_0`
246			`PARAMETER HW_VER = 1.00.a`
247			`BUS_INTERFACE SFSL = microblaze_0_to_fsl_dct_0`
248			`BUS_INTERFACE MFSL = fsl_dct_0_to_microblaze_0`
249			`PORT FSL_Clk = sys_clk_s`
250			`END`
251
252			`BEGIN fsl_v20`
253			`PARAMETER INSTANCE = fsl_dct_0_to_microblaze_0`
254			`PARAMETER HW_VER = 2.00.a`
255			`PARAMETER C_EXT_RESET_HIGH = 0`
256			`PORT FSL_Clk = sys_clk_s`
257			`PORT SYS_Rst = sys_rst_s`
258			`END`
259

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