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[/] [mb-jpeg/] [tags/] [Step2_2/] [system.mhs] - Blame information for rev 21

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1 4 quickwayne 
# ##############################################################################
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# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1
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# Fri Jun 23 16:02:16 2006
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# Target Board:  Xilinx XUP Virtex-II Pro Development System Rev C
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# Family:        virtex2p
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# Device:        xc2vp30
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# Package:       ff896
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# Speed Grade:   -7
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# Processor: Microblaze
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# System clock frequency: 100.000000 MHz
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# Debug interface: On-Chip HW Debug Module
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# On Chip Memory :  64 KB
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# ##############################################################################
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15 
 
16 
 PARAMETER VERSION = 2.1.0
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18 
 
19 5 quickwayne 
 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
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 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
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 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
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 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = O
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 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = IO
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 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
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 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
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 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
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 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
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 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, VEC = [0:3], DIR = IO
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 PORT fpga_0_DIPSWs_4Bit_GPIO_IO_pin = fpga_0_DIPSWs_4Bit_GPIO_IO, VEC = [0:3], DIR = IO
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 PORT fpga_0_PushButtons_5Bit_GPIO_IO_pin = fpga_0_PushButtons_5Bit_GPIO_IO, VEC = [0:4], DIR = IO
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 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = DCMCLK
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 PORT sys_rst_pin = sys_rst_s, DIR = I
33 4 quickwayne 
 
34 
 
35 
BEGIN microblaze
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 PARAMETER INSTANCE = microblaze_0
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 PARAMETER HW_VER = 4.00.a
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 PARAMETER C_DEBUG_ENABLED = 1
39 21 quickwayne 
 PARAMETER C_NUMBER_OF_PC_BRK = 4
40 4 quickwayne 
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
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 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
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 BUS_INTERFACE DLMB = dlmb
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 BUS_INTERFACE ILMB = ilmb
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 BUS_INTERFACE DOPB = mb_opb
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 BUS_INTERFACE IOPB = mb_opb
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 PORT CLK = sys_clk_s
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 PORT DBG_CAPTURE = DBG_CAPTURE_s
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 PORT DBG_CLK = DBG_CLK_s
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 PORT DBG_REG_EN = DBG_REG_EN_s
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 PORT DBG_TDI = DBG_TDI_s
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 PORT DBG_TDO = DBG_TDO_s
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 PORT DBG_UPDATE = DBG_UPDATE_s
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END
54 
 
55 
BEGIN opb_v20
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 PARAMETER INSTANCE = mb_opb
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 PARAMETER HW_VER = 1.10.c
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 PARAMETER C_EXT_RESET_HIGH = 0
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 PORT SYS_Rst = sys_rst_s
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 PORT OPB_Clk = sys_clk_s
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END
62 
 
63 
BEGIN opb_mdm
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 PARAMETER INSTANCE = debug_module
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 PARAMETER HW_VER = 2.00.a
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 PARAMETER C_MB_DBG_PORTS = 1
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 PARAMETER C_USE_UART = 1
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 PARAMETER C_UART_WIDTH = 8
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 PARAMETER C_BASEADDR = 0x41400000
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 PARAMETER C_HIGHADDR = 0x4140ffff
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 BUS_INTERFACE SOPB = mb_opb
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 PORT OPB_Clk = sys_clk_s
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 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
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 PORT DBG_CLK_0 = DBG_CLK_s
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 PORT DBG_REG_EN_0 = DBG_REG_EN_s
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 PORT DBG_TDI_0 = DBG_TDI_s
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 PORT DBG_TDO_0 = DBG_TDO_s
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 PORT DBG_UPDATE_0 = DBG_UPDATE_s
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END
80 
 
81 
BEGIN lmb_v10
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 PARAMETER INSTANCE = ilmb
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_EXT_RESET_HIGH = 0
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 PORT SYS_Rst = sys_rst_s
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 PORT LMB_Clk = sys_clk_s
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END
88 
 
89 
BEGIN lmb_v10
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 PARAMETER INSTANCE = dlmb
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_EXT_RESET_HIGH = 0
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 PORT SYS_Rst = sys_rst_s
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 PORT LMB_Clk = sys_clk_s
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END
96 
 
97 
BEGIN lmb_bram_if_cntlr
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 PARAMETER INSTANCE = dlmb_cntlr
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 PARAMETER HW_VER = 1.00.b
100 21 quickwayne 
 PARAMETER C_BASEADDR = 0x00010000
101 
 PARAMETER C_HIGHADDR = 0x0001ffff
102 4 quickwayne 
 BUS_INTERFACE SLMB = dlmb
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 BUS_INTERFACE BRAM_PORT = dlmb_port
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END
105 
 
106 
BEGIN lmb_bram_if_cntlr
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 PARAMETER INSTANCE = ilmb_cntlr
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 PARAMETER HW_VER = 1.00.b
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 PARAMETER C_BASEADDR = 0x00000000
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 PARAMETER C_HIGHADDR = 0x0000ffff
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 BUS_INTERFACE SLMB = ilmb
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 BUS_INTERFACE BRAM_PORT = ilmb_port
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END
114 
 
115 
BEGIN bram_block
116 21 quickwayne 
 PARAMETER INSTANCE = ilmb_bram
117 4 quickwayne 
 PARAMETER HW_VER = 1.00.a
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 BUS_INTERFACE PORTA = ilmb_port
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END
120 
 
121 
BEGIN opb_uartlite
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 PARAMETER INSTANCE = RS232_Uart_1
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 PARAMETER HW_VER = 1.00.b
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 PARAMETER C_BAUDRATE = 9600
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 PARAMETER C_DATA_BITS = 8
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 PARAMETER C_ODD_PARITY = 0
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 PARAMETER C_USE_PARITY = 0
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 PARAMETER C_CLK_FREQ = 100000000
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 PARAMETER C_BASEADDR = 0x40600000
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 PARAMETER C_HIGHADDR = 0x4060ffff
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 BUS_INTERFACE SOPB = mb_opb
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 PORT OPB_Clk = sys_clk_s
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 PORT RX = fpga_0_RS232_Uart_1_RX
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 PORT TX = fpga_0_RS232_Uart_1_TX
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END
136 
 
137 
BEGIN opb_sysace
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 PARAMETER INSTANCE = SysACE_CompactFlash
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 PARAMETER HW_VER = 1.00.c
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 PARAMETER C_MEM_WIDTH = 16
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 PARAMETER C_BASEADDR = 0x41800000
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 PARAMETER C_HIGHADDR = 0x4180ffff
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 BUS_INTERFACE SOPB = mb_opb
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 PORT OPB_Clk = sys_clk_s
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 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
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 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
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 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
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 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
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 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
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 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
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 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
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END
153 
 
154 
BEGIN opb_gpio
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 PARAMETER INSTANCE = LEDs_4Bit
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 PARAMETER HW_VER = 3.01.b
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 PARAMETER C_GPIO_WIDTH = 4
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 PARAMETER C_IS_DUAL = 0
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 PARAMETER C_IS_BIDIR = 0
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 PARAMETER C_ALL_INPUTS = 0
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 PARAMETER C_BASEADDR = 0x40020000
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 PARAMETER C_HIGHADDR = 0x4002ffff
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 BUS_INTERFACE SOPB = mb_opb
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 PORT OPB_Clk = sys_clk_s
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 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
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END
167 
 
168 
BEGIN opb_gpio
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 PARAMETER INSTANCE = DIPSWs_4Bit
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 PARAMETER HW_VER = 3.01.b
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 PARAMETER C_GPIO_WIDTH = 4
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 PARAMETER C_IS_DUAL = 0
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 PARAMETER C_IS_BIDIR = 1
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 PARAMETER C_ALL_INPUTS = 1
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 PARAMETER C_BASEADDR = 0x40040000
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 PARAMETER C_HIGHADDR = 0x4004ffff
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 BUS_INTERFACE SOPB = mb_opb
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 PORT OPB_Clk = sys_clk_s
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 PORT GPIO_IO = fpga_0_DIPSWs_4Bit_GPIO_IO
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END
181 
 
182 
BEGIN opb_gpio
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 PARAMETER INSTANCE = PushButtons_5Bit
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 PARAMETER HW_VER = 3.01.b
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 PARAMETER C_GPIO_WIDTH = 5
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 PARAMETER C_IS_DUAL = 0
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 PARAMETER C_IS_BIDIR = 1
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 PARAMETER C_ALL_INPUTS = 1
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 PARAMETER C_BASEADDR = 0x40000000
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 PARAMETER C_HIGHADDR = 0x4000ffff
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 BUS_INTERFACE SOPB = mb_opb
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 PORT OPB_Clk = sys_clk_s
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 PORT GPIO_IO = fpga_0_PushButtons_5Bit_GPIO_IO
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END
195 
 
196 
BEGIN dcm_module
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 PARAMETER INSTANCE = dcm_0
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_CLK0_BUF = TRUE
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 PARAMETER C_CLKIN_PERIOD = 10.000000
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 PARAMETER C_CLK_FEEDBACK = 1X
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 PARAMETER C_EXT_RESET_HIGH = 1
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 PORT CLKIN = dcm_clk_s
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 PORT CLK0 = sys_clk_s
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 PORT CLKFB = sys_clk_s
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 PORT RST = net_gnd
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 PORT LOCKED = dcm_0_lock
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END
209 
 
210 
BEGIN bram_block
211 
 PARAMETER INSTANCE = data_bram_0
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_MEMSIZE = 16384
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 BUS_INTERFACE PORTA = data_bram_0_port
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END
216 
 
217 
BEGIN lmb_bram_if_cntlr
218 
 PARAMETER INSTANCE = data_bram_if_cntlr_0
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 PARAMETER HW_VER = 1.00.b
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 PARAMETER C_BASEADDR = 0x70000000
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 PARAMETER C_HIGHADDR = 0x7000ffff
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 BUS_INTERFACE SLMB = dlmb
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 BUS_INTERFACE BRAM_PORT = data_bram_0_port
224 
END
225 
 
226 
BEGIN bram_block
227 21 quickwayne 
 PARAMETER INSTANCE = dlmb_bram
228 4 quickwayne 
 PARAMETER HW_VER = 1.00.a
229 
 PARAMETER C_MEMSIZE = 16384
230 21 quickwayne 
 BUS_INTERFACE PORTA = dlmb_port
231 4 quickwayne 
END
232 
 

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