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quickwayne |
############################################################################
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## This system.ucf file is generated by Base System Builder based on the
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## settings in the selected Xilinx Board Definition file. Please add other
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## user constraints to this file based on customer design specifications.
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############################################################################
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Net sys_clk_pin LOC=AJ15;
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Net sys_clk_pin IOSTANDARD = LVCMOS25;
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Net sys_rst_pin LOC=AH5;
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Net sys_rst_pin IOSTANDARD = LVTTL;
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## System level constraints
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Net sys_clk_pin TNM_NET = sys_clk_pin;
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TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
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Net sys_rst_pin TIG;
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## FPGA pin constraints
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Net fpga_0_RS232_Uart_1_RX_pin LOC=AJ8;
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Net fpga_0_RS232_Uart_1_RX_pin IOSTANDARD = LVCMOS25;
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Net fpga_0_RS232_Uart_1_TX_pin LOC=AE7;
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Net fpga_0_RS232_Uart_1_TX_pin IOSTANDARD = LVCMOS25;
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Net fpga_0_RS232_Uart_1_TX_pin SLEW = SLOW;
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Net fpga_0_RS232_Uart_1_TX_pin DRIVE = 12;
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Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH15;
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Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps;
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| 25 |
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Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS25;
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| 26 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=AF21;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> IOSTANDARD = LVCMOS25;
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| 28 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> SLEW = SLOW;
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| 29 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=AG21;
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| 31 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS25;
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| 32 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> SLEW = SLOW;
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| 33 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> DRIVE = 8;
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| 34 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AC19;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS25;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> SLEW = SLOW;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AD19;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS25;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> SLEW = SLOW;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> DRIVE = 8;
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| 42 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=AE22;
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| 43 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS25;
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| 44 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> SLEW = SLOW;
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| 45 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AE21;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS25;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> SLEW = SLOW;
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| 49 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> DRIVE = 8;
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| 50 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=AH22;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS25;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> SLEW = SLOW;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AE15;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS25;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> SLEW = SLOW;
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| 57 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AD15;
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| 59 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS25;
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| 60 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> SLEW = SLOW;
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| 61 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AG14;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS25;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> SLEW = SLOW;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AF14;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS25;
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| 68 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> SLEW = SLOW;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AE14;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS25;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> SLEW = SLOW;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AD14;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS25;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> SLEW = SLOW;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AC15;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS25;
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| 80 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> SLEW = SLOW;
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| 81 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> DRIVE = 8;
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| 82 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AB15;
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| 83 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS25;
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| 84 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> SLEW = SLOW;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AJ9;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS25;
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| 88 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> SLEW = SLOW;
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| 89 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AH9;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS25;
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| 92 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> SLEW = SLOW;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AE10;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS25;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> SLEW = SLOW;
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| 97 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> DRIVE = 8;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AE9;
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS25;
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| 100 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> SLEW = SLOW;
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| 101 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> DRIVE = 8;
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| 102 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AD12;
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| 103 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS25;
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| 104 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> SLEW = SLOW;
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| 105 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> DRIVE = 8;
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| 106 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AC12;
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| 107 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS25;
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| 108 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> SLEW = SLOW;
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| 109 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> DRIVE = 8;
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| 110 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AG10;
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| 111 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS25;
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| 112 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> SLEW = SLOW;
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| 113 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> DRIVE = 8;
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| 114 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AF10;
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| 115 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS25;
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| 116 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> SLEW = SLOW;
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| 117 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> DRIVE = 8;
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| 118 |
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Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AB16;
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| 119 |
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Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS25;
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| 120 |
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Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin SLEW = SLOW;
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| 121 |
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Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin DRIVE = 8;
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| 122 |
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Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AD17;
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| 123 |
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Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS25;
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| 124 |
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Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin SLEW = SLOW;
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| 125 |
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Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin DRIVE = 8;
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| 126 |
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Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=AC16;
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| 127 |
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Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS25;
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| 128 |
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Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin SLEW = SLOW;
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| 129 |
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Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin DRIVE = 8;
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| 130 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AD16;
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| 131 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS25;
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| 132 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<12> LOC=M25;
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| 133 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<12> IOSTANDARD = SSTL2_II;
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| 134 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<11> LOC=N25;
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| 135 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<11> IOSTANDARD = SSTL2_II;
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| 136 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<10> LOC=L26;
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| 137 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<10> IOSTANDARD = SSTL2_II;
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| 138 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<9> LOC=M29;
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| 139 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<9> IOSTANDARD = SSTL2_II;
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| 140 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<8> LOC=K30;
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| 141 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<8> IOSTANDARD = SSTL2_II;
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| 142 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<7> LOC=G25;
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| 143 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<7> IOSTANDARD = SSTL2_II;
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| 144 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<6> LOC=G26;
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| 145 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<6> IOSTANDARD = SSTL2_II;
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| 146 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<5> LOC=D26;
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| 147 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<5> IOSTANDARD = SSTL2_II;
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| 148 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<4> LOC=J24;
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| 149 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<4> IOSTANDARD = SSTL2_II;
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| 150 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<3> LOC=K24;
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| 151 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<3> IOSTANDARD = SSTL2_II;
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| 152 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<2> LOC=F28;
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| 153 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<2> IOSTANDARD = SSTL2_II;
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| 154 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<1> LOC=F30;
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| 155 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<1> IOSTANDARD = SSTL2_II;
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| 156 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<0> LOC=M24;
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| 157 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<0> IOSTANDARD = SSTL2_II;
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| 158 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<1> LOC=M26;
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| 159 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_II;
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| 160 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<0> LOC=K26;
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| 161 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_II;
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| 162 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin LOC=L27;
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| 163 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin IOSTANDARD = SSTL2_II;
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| 164 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin LOC=R26;
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| 165 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin IOSTANDARD = SSTL2_II;
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| 166 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin LOC=R24;
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| 167 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin IOSTANDARD = SSTL2_II;
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| 168 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin LOC=N29;
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| 169 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin IOSTANDARD = SSTL2_II;
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| 170 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin LOC=N26;
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| 171 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin IOSTANDARD = SSTL2_II;
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| 172 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<7> LOC=U26;
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| 173 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<7> IOSTANDARD = SSTL2_II;
|
| 174 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<6> LOC=V29;
|
| 175 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<6> IOSTANDARD = SSTL2_II;
|
| 176 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<5> LOC=W29;
|
| 177 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<5> IOSTANDARD = SSTL2_II;
|
| 178 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<4> LOC=T22;
|
| 179 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<4> IOSTANDARD = SSTL2_II;
|
| 180 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<3> LOC=W28;
|
| 181 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
|
| 182 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<2> LOC=W27;
|
| 183 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
|
| 184 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<1> LOC=W26;
|
| 185 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
|
| 186 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<0> LOC=W25;
|
| 187 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
|
| 188 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> LOC=E30;
|
| 189 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> IOSTANDARD = SSTL2_II;
|
| 190 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<6> LOC=J29;
|
| 191 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<6> IOSTANDARD = SSTL2_II;
|
| 192 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<5> LOC=M30;
|
| 193 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<5> IOSTANDARD = SSTL2_II;
|
| 194 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<4> LOC=P29;
|
| 195 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<4> IOSTANDARD = SSTL2_II;
|
| 196 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<3> LOC=V23;
|
| 197 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II;
|
| 198 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<2> LOC=AA25;
|
| 199 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II;
|
| 200 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<1> LOC=AC25;
|
| 201 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II;
|
| 202 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<0> LOC=AH26;
|
| 203 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II;
|
| 204 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<63> LOC=C27;
|
| 205 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<63> IOSTANDARD = SSTL2_II;
|
| 206 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<62> LOC=D28;
|
| 207 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<62> IOSTANDARD = SSTL2_II;
|
| 208 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<61> LOC=D29;
|
| 209 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<61> IOSTANDARD = SSTL2_II;
|
| 210 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<60> LOC=D30;
|
| 211 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<60> IOSTANDARD = SSTL2_II;
|
| 212 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<59> LOC=H25;
|
| 213 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<59> IOSTANDARD = SSTL2_II;
|
| 214 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<58> LOC=H26;
|
| 215 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<58> IOSTANDARD = SSTL2_II;
|
| 216 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<57> LOC=E27;
|
| 217 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<57> IOSTANDARD = SSTL2_II;
|
| 218 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<56> LOC=E28;
|
| 219 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<56> IOSTANDARD = SSTL2_II;
|
| 220 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<55> LOC=J26;
|
| 221 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<55> IOSTANDARD = SSTL2_II;
|
| 222 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<54> LOC=G27;
|
| 223 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<54> IOSTANDARD = SSTL2_II;
|
| 224 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<53> LOC=G28;
|
| 225 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<53> IOSTANDARD = SSTL2_II;
|
| 226 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<52> LOC=G30;
|
| 227 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<52> IOSTANDARD = SSTL2_II;
|
| 228 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<51> LOC=L23;
|
| 229 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<51> IOSTANDARD = SSTL2_II;
|
| 230 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<50> LOC=L24;
|
| 231 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<50> IOSTANDARD = SSTL2_II;
|
| 232 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<49> LOC=H27;
|
| 233 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<49> IOSTANDARD = SSTL2_II;
|
| 234 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<48> LOC=H28;
|
| 235 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<48> IOSTANDARD = SSTL2_II;
|
| 236 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<47> LOC=J27;
|
| 237 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<47> IOSTANDARD = SSTL2_II;
|
| 238 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<46> LOC=J28;
|
| 239 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<46> IOSTANDARD = SSTL2_II;
|
| 240 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<45> LOC=K29;
|
| 241 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<45> IOSTANDARD = SSTL2_II;
|
| 242 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<44> LOC=L29;
|
| 243 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<44> IOSTANDARD = SSTL2_II;
|
| 244 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<43> LOC=N23;
|
| 245 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<43> IOSTANDARD = SSTL2_II;
|
| 246 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<42> LOC=N24;
|
| 247 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<42> IOSTANDARD = SSTL2_II;
|
| 248 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<41> LOC=K27;
|
| 249 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<41> IOSTANDARD = SSTL2_II;
|
| 250 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<40> LOC=K28;
|
| 251 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<40> IOSTANDARD = SSTL2_II;
|
| 252 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<39> LOC=R22;
|
| 253 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<39> IOSTANDARD = SSTL2_II;
|
| 254 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<38> LOC=M27;
|
| 255 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<38> IOSTANDARD = SSTL2_II;
|
| 256 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<37> LOC=M28;
|
| 257 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<37> IOSTANDARD = SSTL2_II;
|
| 258 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<36> LOC=P30;
|
| 259 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<36> IOSTANDARD = SSTL2_II;
|
| 260 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<35> LOC=P23;
|
| 261 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<35> IOSTANDARD = SSTL2_II;
|
| 262 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<34> LOC=P24;
|
| 263 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<34> IOSTANDARD = SSTL2_II;
|
| 264 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<33> LOC=N27;
|
| 265 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<33> IOSTANDARD = SSTL2_II;
|
| 266 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<32> LOC=N28;
|
| 267 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<32> IOSTANDARD = SSTL2_II;
|
| 268 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<31> LOC=V27;
|
| 269 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II;
|
| 270 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<30> LOC=Y30;
|
| 271 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II;
|
| 272 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<29> LOC=U24;
|
| 273 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II;
|
| 274 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<28> LOC=U23;
|
| 275 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II;
|
| 276 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<27> LOC=V26;
|
| 277 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II;
|
| 278 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<26> LOC=V25;
|
| 279 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II;
|
| 280 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<25> LOC=Y29;
|
| 281 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II;
|
| 282 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<24> LOC=AA29;
|
| 283 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II;
|
| 284 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<23> LOC=Y26;
|
| 285 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II;
|
| 286 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<22> LOC=AA28;
|
| 287 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II;
|
| 288 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<21> LOC=AA27;
|
| 289 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II;
|
| 290 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<20> LOC=W24;
|
| 291 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II;
|
| 292 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<19> LOC=W23;
|
| 293 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II;
|
| 294 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<18> LOC=AB28;
|
| 295 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II;
|
| 296 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<17> LOC=AB27;
|
| 297 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II;
|
| 298 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<16> LOC=AC29;
|
| 299 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II;
|
| 300 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<15> LOC=AB25;
|
| 301 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II;
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| 302 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<14> LOC=AE29;
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| 303 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II;
|
| 304 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<13> LOC=AA24;
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| 305 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II;
|
| 306 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<12> LOC=AA23;
|
| 307 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II;
|
| 308 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<11> LOC=AD28;
|
| 309 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II;
|
| 310 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<10> LOC=AD27;
|
| 311 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II;
|
| 312 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<9> LOC=AF30;
|
| 313 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II;
|
| 314 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<8> LOC=AF29;
|
| 315 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II;
|
| 316 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<7> LOC=AF25;
|
| 317 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II;
|
| 318 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<6> LOC=AG30;
|
| 319 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II;
|
| 320 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<5> LOC=AG29;
|
| 321 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II;
|
| 322 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<4> LOC=AD26;
|
| 323 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II;
|
| 324 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<3> LOC=AD25;
|
| 325 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II;
|
| 326 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<2> LOC=AG28;
|
| 327 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II;
|
| 328 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<1> LOC=AH27;
|
| 329 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II;
|
| 330 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<0> LOC=AH29;
|
| 331 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II;
|
| 332 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<2> LOC=AC27;
|
| 333 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<2> IOSTANDARD = SSTL2_II;
|
| 334 |
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<1> LOC=AD29;
|
| 335 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<1> IOSTANDARD = SSTL2_II;
|
| 336 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<0> LOC=AB23;
|
| 337 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<0> IOSTANDARD = SSTL2_II;
|
| 338 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<2> LOC=AC28;
|
| 339 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<2> IOSTANDARD = SSTL2_II;
|
| 340 |
|
|
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<1> LOC=AD30;
|
| 341 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<1> IOSTANDARD = SSTL2_II;
|
| 342 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<0> LOC=AB24;
|
| 343 |
|
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Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<0> IOSTANDARD = SSTL2_II;
|
| 344 |
|
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Net fpga_0_DDR_CLK_FB LOC=C16;
|
| 345 |
|
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Net fpga_0_DDR_CLK_FB IOSTANDARD = SSTL2_II;
|
| 346 |
|
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Net fpga_0_DDR_CLK_FB_OUT LOC=G23;
|
| 347 |
|
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Net fpga_0_DDR_CLK_FB_OUT IOSTANDARD = SSTL2_II;
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