OpenCores
URL https://opencores.org/ocsvn/mblite/mblite/trunk

Subversion Repositories mblite

[/] [mblite/] [trunk/] [designs/] [core_decoder/] [testbench.vhd] - Blame information for rev 11

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 takar
----------------------------------------------------------------------------------------------
2
--
3
--      Input file         : config_Pkg.vhd
4
--      Design name        : config_Pkg
5
--      Author             : Tamar Kranenburg
6
--      Company            : Delft University of Technology
7
--                         : Faculty EEMCS, Department ME&CE
8
--                         : Systems and Circuits group
9
--
10
--      Description        : Testbench which instantiates instruction memory, data memory,
11
--                           core, core address decoder and stdio
12
--
13
----------------------------------------------------------------------------------------------
14
 
15 8 takar
library ieee;
16
use ieee.std_logic_1164.all;
17
use ieee.std_logic_unsigned.all;
18 2 takar
 
19 8 takar
library mblite;
20
use mblite.config_Pkg.all;
21
use mblite.core_Pkg.all;
22
use mblite.std_Pkg.all;
23 2 takar
 
24 8 takar
entity testbench is
25
end testbench;
26 2 takar
 
27 8 takar
architecture arch of testbench is
28 2 takar
 
29 8 takar
    component mblite_stdio is port
30 2 takar
    (
31 8 takar
        dmem_i : out dmem_in_type;
32
        dmem_o : in dmem_out_type;
33
        clk_i  : in std_logic
34 2 takar
    );
35 8 takar
    end component;
36 2 takar
 
37 8 takar
    signal dmem_o : dmem_out_type;
38
    signal dmem_i : dmem_in_type;
39
    signal imem_o : imem_out_type;
40
    signal imem_i : imem_in_type;
41
    signal s_dmem_o : dmem_out_array_type(CFG_NUM_SLAVES - 1 downto 0);
42
    signal s_dmem_i : dmem_in_array_type(CFG_NUM_SLAVES - 1 downto 0);
43 2 takar
 
44 8 takar
    signal sys_clk_i : std_logic := '0';
45
    signal sys_int_i : std_logic;
46
    signal sys_rst_i : std_logic;
47 2 takar
 
48 8 takar
    constant rom_size : integer := 16;
49
    constant ram_size : integer := 16;
50 2 takar
 
51 8 takar
    signal sel_o : std_logic_vector(3 downto 0);
52
    signal ena_o : std_logic;
53 2 takar
 
54
BEGIN
55
 
56 8 takar
    sys_clk_i <= not sys_clk_i after 10000 ps;
57
    sys_rst_i <= '1' after 0 ps, '0' after  150000 ps;
58
    sys_int_i <= '1' after 500000000 ps, '0' after 500040000 ps;
59 2 takar
 
60
    -- Warning: an infinite loop like while(1) {} triggers this timeout too!
61
    -- disable this feature when a premature finish occur.
62 8 takar
    timeout: process(sys_clk_i)
63
    begin
64
        if NOW = 10 ms then
65
            report "TIMEOUT" severity FAILURE;
66
        end if;
67 2 takar
        -- BREAK ON EXIT (0xB8000000)
68 8 takar
        if compare(imem_i.dat_i, "10111000000000000000000000000000") = '1' then
69 2 takar
            -- Make sure the simulator finishes when an error is encountered.
70
            -- For modelsim: see menu Simulate -> Runtime options -> Assertions
71 8 takar
            report "FINISHED" severity FAILURE;
72
        end if;
73
    end process;
74 2 takar
 
75 8 takar
    stdio : mblite_stdio port map
76 2 takar
    (
77
        dmem_i => s_dmem_i(1),
78
        dmem_o => s_dmem_o(1),
79
        clk_i  => sys_clk_i
80
    );
81
 
82
    s_dmem_i(0).ena_i <= '1';
83 8 takar
    sel_o <= s_dmem_o(0).sel_o when s_dmem_o(0).we_o = '1' else (others => '0');
84
    ena_o <= not sys_rst_i and s_dmem_o(0).ena_o;
85 2 takar
 
86 8 takar
    dmem : sram_4en generic map
87 2 takar
    (
88
        WIDTH => CFG_DMEM_WIDTH,
89
        SIZE => ram_size - 2
90
    )
91 8 takar
    port map
92 2 takar
    (
93
        dat_o => s_dmem_i(0).dat_i,
94
        dat_i => s_dmem_o(0).dat_o,
95 8 takar
        adr_i => s_dmem_o(0).adr_o(ram_size - 1 downto 2),
96 2 takar
        wre_i => sel_o,
97
        ena_i => ena_o,
98
        clk_i => sys_clk_i
99
    );
100
 
101 8 takar
    decoder : core_address_decoder generic map
102 2 takar
    (
103
        G_NUM_SLAVES => CFG_NUM_SLAVES
104
    )
105 8 takar
    port map
106 2 takar
    (
107
        m_dmem_i => dmem_i,
108
        s_dmem_o => s_dmem_o,
109
        m_dmem_o => dmem_o,
110
        s_dmem_i => s_dmem_i,
111
        clk_i    => sys_clk_i
112
    );
113
 
114 8 takar
    imem : sram generic map
115 2 takar
    (
116
        WIDTH => CFG_IMEM_WIDTH,
117
        SIZE => rom_size - 2
118
    )
119 8 takar
    port map
120 2 takar
    (
121
        dat_o => imem_i.dat_i,
122
        dat_i => "00000000000000000000000000000000",
123 8 takar
        adr_i => imem_o.adr_o(rom_size - 1 downto 2),
124 2 takar
        wre_i => '0',
125
        ena_i => imem_o.ena_o,
126
        clk_i => sys_clk_i
127
    );
128
 
129 8 takar
    core0 : core port map
130 2 takar
    (
131
        imem_o => imem_o,
132
        dmem_o => dmem_o,
133
        imem_i => imem_i,
134
        dmem_i => dmem_i,
135
        int_i  => sys_int_i,
136
        rst_i  => sys_rst_i,
137
        clk_i  => sys_clk_i
138
    );
139
 
140 8 takar
end arch;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.